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WO/2024/109870A1 |
Provided in the present invention is a manufacturing method for MOS devices. The method comprises: providing a substrate, wherein a gate region and a source/drain region are formed on the substrate, a through hole is formed in a dielectr...
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WO/2024/112426A1 |
A bidirectional field-effect transistor comprising a semiconductor channel positioned between device terminals providing current flow through the channel; at least one field-effect gate positioned along the semiconductor channel between ...
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WO/2024/108991A1 |
A semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises: at least one vertical-channel transistor arranged on a substrate (1); and a bit line (30). The transistor comprises...
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WO/2024/108420A1 |
An apparatus and method for measuring dynamic threshold voltage of a nitride-based device under test (DUT) is provided. The apparatus comprising: a DUT control circuit configured for providing a DUT control signal to turn on and off the ...
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WO/2024/111280A1 |
A light detection device according to one embodiment of the present disclosure comprises: a photoelectric conversion unit that photoelectrically converts light; and a read circuit that includes a first transistor and that can output a si...
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WO/2024/109459A1 |
Provided in the embodiments of the present application are a semiconductor structure, a semiconductor device, an electronic device, and a wafer bonding method. The wafer bonding method comprises: providing two wafers to be bonded, wherei...
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WO/2024/111243A1 |
The present invention provides a semiconductor device which is capable of suppressing destruction of elements that is caused by the concentration of carriers in the boundary part between a diode region and an IGBT region due to the inflo...
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WO/2024/086678A3 |
Various 3D cells, array structures and processes are disclosed. In an embodiment, a memory cell structure is provided that includes a vertical bit line, an insulator surrounding a first portion of vertical bit line, a continuous semicond...
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WO/2024/109192A1 |
The present invention provides a shielded gate power MOSFET and a manufacturing method therefor. The method comprises the following steps: forming a hard mask layer on an epitaxial layer, patterning the hard mask layer, and etching the e...
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WO/2024/110156A1 |
The invention relates to a memory cell which has a layer (101) for collecting charge carries at a surface of the layer (101), an electrically insulating layer (102) on the surface provided for collecting charge carriers, a low-doped, sem...
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WO/2024/108490A1 |
The semiconductor device includes a channel layer, a first barrier layer, a second barrier layer, and a gate electrode. The first barrier layer is disposed over the channel layer. The second barrier layer with separated portions covers t...
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WO/2024/109118A1 |
Provided in the present invention are a self-aligned trench power device having a controllable channel length, and a manufacturing method therefor. The device comprises a substrate, a body region, a source contact region, a trench, a sou...
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WO/2024/108488A1 |
The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source and a drain electrodes, and a gate electrode. The second nitride-based semiconductor layer is...
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WO/2024/108422A1 |
The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a n-type doped nitride-based semiconductor layer, a p-type doped nitride-based semiconductor layer, an...
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WO/2024/108647A1 |
The present invention relates to the technical field of semiconductor materials, and in particular to a two-dimensional photoelectric semiconductor material having high carrier mobility and a use thereof. The chemical formula of the semi...
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WO/2024/109030A1 |
The present invention relates to the technical field of semiconductors, and provides a gate-all-around transistor and a manufacturing method therefor, and an electronic device. For a gate-all-around transistor (1), a first epitaxial dope...
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WO/2024/110830A1 |
Provided is a semiconductor device which performs stable operation. The semiconductor device comprises first to fourth transistors. The first to fourth transistors have first insulators. The first and second transistors have first gate i...
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WO/2024/108491A1 |
A nitride-based semiconductor device (1A-1D) includes a first nitride-based semiconductor layer (12), a second nitride-based semiconductor layer (14), a first electrode (30) and a second electrode (32), a gate electrode (40) and a gate f...
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WO/2024/108799A1 |
A threshold-voltage-controllable ultrathin multi-bridge channel transistor and a preparation method therefor. The ultrathin multi-bridge channel transistor comprises a substrate and multiple layers of gate-all-around transistor structure...
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WO/2024/112606A1 |
A method of removing a solid-state die handle substrate from a solid-state die may include providing a substrate structure including a first substrate, a second substrate bonded to the first substrate and the solid-state die bonded to th...
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WO/2024/105497A1 |
Provided is a storage device with high data-reading reliability. The storage device has a first transistor and a second transistor in a memory cell, wherein for the two transistors, vertical transistors, which occupy a small area and hav...
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WO/2024/105907A1 |
The purpose of the present invention is to provide a thin-film inductor element that, when mounted within an electric circuit, exhibits sufficient emergent inductor functionality while reducing the operating current.　This thin-film ind...
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WO/2024/103198A1 |
The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a doped III-V semiconductor layer, a plurality of fillings, and a gate electrode. The second nitride-b...
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WO/2024/104074A1 |
The present disclosure provides a semiconductor device. The semiconductor device comprises a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a third nitride semiconductor layer, a gate electrode, and...
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WO/2024/106191A1 |
The present disclosure relates to a solid-state imaging element, a manufacturing method, and an electronic apparatus that make it possible to achieve higher performance. The solid-state imaging element includes: a first transistor provid...
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WO/2024/103727A1 |
The present disclosure relates to the field of semiconductor materials. Disclosed are a silicon carbide epitaxial wafer, and a preparation method therefor and a use thereof. The silicon carbide epitaxial wafer provided by the present dis...
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WO/2024/103199A1 |
The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a doped III-V semiconductor layer, and a gate electrode. The second nitride-based semiconductor layer ...
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WO/2024/105515A1 |
Provided is a semiconductor device that can be easily miniaturized. Provided is a semiconductor device in which parasitic capacitance is reduced. This semiconductor device comprises a transistor, a first insulation layer, and a second in...
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WO/2024/104626A1 |
The present invention relates to a method of forming a graphene layer structure, the method comprising: providing a growth substrate comprising a first layer on a support layer; and forming a graphene layer structure on a growth surface ...
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WO/2024/103252A1 |
The present disclosure provides a nitride-based semiconductor integrated circuit (IC) chip including at least one transistor and a built-in bypass diode configured for bypassing reverse current flowing through the transistor. The built-i...
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WO/2024/107935A1 |
An input selector for electrically connecting one of a plurality of test signals from one or more devices under test to a test and measurement instrument, the input selector includes a first multiplexer having a first set of multiple inp...
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WO/2024/107592A1 |
A FeFET transistor (600) is disclosed that has a source electrode (602), a drain electrode (602), and a channel structure (604). The first portion (606) is disposed parallel to the source electrode along the first length. The second port...
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WO/2024/105724A1 |
This bipolar transistor comprises a collector layer (103) formed on a substrate (101), a base layer (104) formed on the collector layer (103), an emitter layer (105) formed on the base layer (104), and an emitter cap layer (106) formed o...
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WO/2024/103281A1 |
The present disclosure provides a memory device that includes a film stack having functional tiers stacked in a first direction. Each functional tier includes a first dielectric layer and a conductive layer. The memory device also includ...
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WO/2024/107467A1 |
A high electron mobility heterostructure and a method of fabricating the heterostructure, wherein the high electron mobility heterostructure comprises a substrate, a buffer on the substrate, a doped charge compensation layer on the buffe...
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WO/2024/105004A1 |
An electronic device (10) in the form of a field effect transistor comprising a substrate (15) and a dielectric layer (20) on the substrate (15). The dielectric layer (20) comprises a polymeric dielectric layer (22) with a cyclic olefin ...
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WO/2024/105038A1 |
There is provided a method of forming partially-fluorinated-graphene on a substrate, the method comprising: (a) providing a crystalline substrate having a surface formed of a first metal oxide, and optionally treating the surface of the ...
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WO/2024/107583A2 |
An apparatus and method for efficiently routing power signals across a semiconductor die. In various implementations, an integrated circuit uses Cross field effect transistors (FETs) with a first device, such as n-type device, having a f...
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WO/2024/104287A1 |
The present invention relates to the technical field of semiconductor power devices. The present invention provides an IGBT device, comprising a substrate, a P-type well layer, a true gate, and dummy gates. The substrate has a front surf...
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WO/2024/103312A1 |
A nitride-based semiconductor circuit includes a carrier, a nitride-based semiconductor die, and connecting clips. The nitride-based semiconductor circuit has first connecting surfaces, and the first connecting surfaces located around th...
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WO/2024/104033A1 |
A semiconductor device, and a method for manufacturing the semiconductor device. The semiconductor device comprises: a substrate (101); a first nitride semiconductor layer (103) located on the substrate (101); a second nitride semiconduc...
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WO/2024/106671A1 |
A display device is provided. The display device comprises: a light-emitting element; a first transistor for controlling a driving current flowing through the light-emitting element; a second transistor for supplying a data voltage to th...
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WO/2024/104301A1 |
A high-stability GaN device and a GaN bridge integrated circuit. In the GaN device, on the basis of a traditional HEMT enhanced device structure, a back blocking layer is inserted between a channel layer and a buffer layer.
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WO/2024/105968A1 |
This thin-film transistor array comprises: a flexible substrate having a surface with insulating properties; and a plurality of thin-film transistors disposed on the flexible substrate. A thin-film transistor comprises: a semiconductor l...
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WO/2024/106938A1 |
A tunneling field-effect transistor is provided. The tunneling field-effect transistor comprises a semiconductor layer, which is disposed on a substrate and has a first semiconductor region and a second semiconductor region. The band gap...
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WO/2024/105516A1 |
Provided is a semiconductor device with which refinement is simple. Provided is a semiconductor device with which parasitic capacitance is reduced. This semiconductor device is provided with: an insulating layer that functions as a first...
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WO/2024/106620A1 |
The present invention relates to an oxide thin film transistor with improved performance and a method for manufacturing same. More specifically, the present invention relates to: a manufacturing method in which a gate insulating film is ...
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WO/2024/099851A1 |
A semiconductor memory cell comprising six vertical-transport field-effect transistors (VTFET) on a wafer. The six VTFET are in a first layer. The six VTFET are in a first row.
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WO/2024/099309A1 |
Provided are an array substrate and a display apparatus. The array substrate comprises: a base substrate, which comprises a main surface; a transistor, which is located on the main surface of the base substrate, and comprises an active l...
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WO/2024/101129A1 |
This semiconductor device includes: a chip that has a main surface; a trench electrode-type resistive structure that is formed on the main surface; and a resistive film that covers the resistive structure as a single coating target and i...
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