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WO/2024/118714A2 |
Aspects of the subject disclosure may include, for example, implementing a first stage including a first number of phase rotators in parallel generating respective clock phases off set by a fixed amount; a second stage including a second...
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WO/2024/113809A1 |
The present application relates to the technical field of electronics. Provided are a ring oscillator and a communication apparatus, which are used for reducing the phase noise of the ring oscillator and improving the performance of the ...
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WO/2024/108549A1 |
Provided in the present disclosure are a latch, a D-type flip-flop unit, and a frequency divider. The latch comprises a master amplification module, a slave latch module and a clock transmission gate module. The master amplification modu...
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WO/2024/109440A1 |
The present invention relates to the technical field of signal synchronization. Disclosed are a signal synchronization method and apparatus, and a plasma power supply system. The method comprises: successively acquiring reference frequen...
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WO/2024/103589A1 |
Disclosed in the present invention is a high-frequency crystal oscillator based on automatic phase error correction. The high-frequency crystal oscillator comprises a high-frequency crystal, a load capacitor, two single-pole double-throw...
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WO/2024/103766A1 |
Provided in the present application are a phase locked loop, a noise elimination method, a chip and an electronic device. A first reference clock signal and a first feedback clock signal are sent by means of a first signal switching circ...
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WO/2024/099557A1 |
An apparatus for processing first and second input signals is disclosed.The apparatus comprises first and second phase frequency detectors (PFDs), each configured to provide leading and subsequent intermediate signals based on two receiv...
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WO/2024/095236A1 |
A device to generate required energy frequency flux at a place or around the material, wherein the device comprises of a power supply module having outputs with X and Y adapters, a rechargeable battery unit, a power flow of 230 volts in ...
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WO/2024/059586A9 |
An example apparatus includes a phase detector, a digital discriminator, and a logic circuit. A status signal of the phase detector is at least partially based on a phase relationship between a reference clock and a feedback clock, the f...
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WO/2024/093297A1 |
The present application provides a phase-locked loop and a signal delay processing method. After receiving a reference clock signal inputted by an external device and a first input control codeword, a first delay circuit performs signal ...
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WO/2024/093417A1 |
A crystal oscillator starting control circuit (120) and method, a crystal oscillator apparatus, and an SOC chip. The circuit (120) comprises: a logic circuit (122); and a linear voltage regulator (124) for determining, according to a fir...
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WO/2024/096158A1 |
The present invention relates to a vapor cell structure manufactured by a micro-electro mechanical systems (MEMS) process. Disclosed is a vapor cell structure comprising: a frame having at least one hollow formed through one portion ther...
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WO/2024/091734A2 |
A delay buffer includes a delay device having an input, an output, and a current terminal. The delay buffer also includes a current circuit coupled between a rail and the current terminal. The current circuit includes transistors and swi...
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WO/2024/087694A1 |
Embodiments of the present application relate to the technical field of integrated circuits, and provide a phase detector and operating method thereof, a clock and data recovery circuit, and an electronic device, for use in solving the p...
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WO/2024/088137A1 |
A charge pump, a phase-locked loop, a radar sensor, and an electronic device. The charge pump is applicable to the phase-locked loop, and the phase-locked loop enters a locked state when two input clock signals are in the same frequency ...
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WO/2024/082527A1 |
Provided in the embodiments of the present disclosure are a delay phase-locked loop and a memory. When starting to operate, the delay phase-locked loop determines a phase difference between a reference clock signal and a feedback clock s...
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WO/2024/078230A1 |
The present application provides a crystal oscillator, a control method for a crystal oscillator, a device, and a storage medium. The crystal oscillator comprises: an external crystal, a capacitance tuning array connected to the external...
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WO/2024/081461A1 |
A delay cell for a delay locked loop, DLL, based serial link is disclosed. The delay cell has a first stage and a second stage, wherein an output of the first stage is an input to the second stage, the first stage comprising a resistive ...
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WO/2024/080571A1 |
A clock phase calibration device according to one embodiment of the present disclosure comprises: a clock generation module for generating a plurality of clocks on the basis of a reference clock; a clock sampling module for sampling sign...
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WO/2024/077088A1 |
A pathogen detection method. A sample that potentially contains a pathogen is collected. A triangle wave form output is produced. A signal associated with the triangle wave form is transmitted from a voltage-controlled oscillator over a ...
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WO/2024/067768A1 |
The present disclosure provides a burst mode clock and data recovery module, comprising: a data sampling sub-module configured to sample received data according to a clock signal, and output a sampling result to a phase determination sub...
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WO/2024/072977A1 |
A subordinate clock includes a first servo loop, a second servo loop, and a third servo loop, each include a respective digitally controlled oscillator (DCO). The first DCO receives (i) a first error signal that is associated with a phys...
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WO/2024/064574A1 |
Aspects described herein include devices and methods for phase tracking and correction using sampling. One aspect includes a wireless communication apparatus having an analog 1-bit sampler configured to sample a phase locked loop (PLL) o...
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WO/2024/064546A1 |
Methods and apparatus for storing a control voltage of a phased-locked loop (PLL) when switching from mission mode to standby mode for the PLL, and for restoring the control voltage of the PLL when switching back to mission mode. An exam...
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WO/2024/064528A1 |
Aspects of the present disclosure provide techniques and apparatus for synchronizing phase-locked loop (PLL) circuits. An example method of operating PLL circuits includes obtaining an indication to perform a synchronizing action at a fi...
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WO/2024/059587A1 |
An example apparatus includes a phase detector and a phase error detector. The phase detector may set a status signal to indicate status of phase difference between a reference clock and a feedback clock, the feedback clock generated by ...
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WO/2024/057606A1 |
A mechanical resonator-based oscillator comprises an input signal generator configured to output an input signal, a mechanical resonator comprising a body configured to vibrate according to the input signal and to output a vibration sign...
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WO/2024/055589A1 |
The present invention relates to a phase tracking circuit and method, and an electronic device. The phase tracking circuit may comprise: a frequency divider, which is used for performing frequency division processing on a first clock sig...
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WO/2024/051281A1 |
A frequency multiplier, a signal transmitter, and a radar chip. The frequency multiplier comprises: a signal generator, used for receiving a frequency modulated continuous wave (FMCM) signal, and outputting a square wave signal having th...
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WO/2024/051178A1 |
Provided is an oscillator circuit (100), comprising a frequency setting circuit (110), first and second clock signal generation circuits (120, 130), a clock synchronization circuit (150), a control circuit (140), and an output circuit (1...
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WO/2024/053527A1 |
A metal gas sealed cell 100 comprises: a cell body 10; a glass plate 11; an optical chamber 14 that is provided to at least one selected from the cell body 10 and the glass plate 11, and that is in communication with a gas generation uni...
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WO/2024/052063A1 |
A signal generating circuit (1100) comprising a series of cascade elements (1103a, 1103b), each comprising a cascade input, a cascade output; a clock input, a reset element (1115, 1117), and a first switch (1105a, 1107a) and a second swi...
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WO/2024/049732A1 |
A pulse generator circuit (210) includes a charge pump (114) having a charge pump output. A voltage divider (R1/R2) is coupled to the charge pump output. The voltage divider (R1/R2) has a voltage divider output. An error amplifier (116) ...
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WO/2024/044910A1 |
A photosensitive ring oscillator, its preparation method, and a flexible artificial retina. The photosensitive ring oscillators (PROs) based on 2D semiconducting materials have been fabricated on flexible biological compatible substrates...
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WO/2024/045130A1 |
Provided in the present invention are a measurement circuit and an operation method therefor. The measurement circuit comprises: a voltage source (V1); a ground (G1); a first resistor (R1), wherein a first end of the first resistor (R1) ...
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WO/2024/049968A1 |
A timing alignment circuit (108) includes detection circuitry (138, 142) to receive first and second output signals, and output an error sign signal indicating whether the second output signal leads or lags the first output signal and a ...
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WO/2024/049818A1 |
A digital-to-time converter circuit (200) includes a scrambling and noise shaping circuit (211), a digital-to-analog converter (DAC) (208), and a buffer circuit (218). The scrambling and noise shaping circuit (211) includes an input and ...
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WO/2024/043985A1 |
A peak detector comprises multiple small-size amplitude detection circuits coupled in parallel to signal inputs at which a signal is received from a VCO. Each amplitude detection circuit generates a voltage on an output, indicating a vol...
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WO/2024/031746A1 |
Provided in embodiments of the present disclosure are a delay phase-locked loop, a clock synchronization circuit and a memory. The delay phase-locked loop comprises a preprocessing module, which is configured to receive an initial clock ...
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WO/2024/031169A1 |
A module for modulation and demodulation using two substantially identical self-oscillating mixers (SOMs) injection-locked at a coupling frequency, providing a simple compact, low power, highly efficient receiver, transmitter or transcei...
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WO/2024/036322A2 |
A method includes: observing that a digitally controlled oscillator (DCO) frequency is at a boundary of a DCO frequency overlap region; and bypassing at least a portion of the DCO frequency overlap region.
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WO/2024/026054A1 |
In some examples, a circuit (104) includes a phase frequency detector (PFD) (206) having a first input, a second input, and an output. The circuit also includes a control circuit (208) having an input and an output, the control circuit i...
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WO/2024/016896A1 |
Disclosed in the present application are a multi-phase clock generation circuit and method. The circuit comprises: a frequency division module, wherein a signal input end of the frequency division module receives and connects to a clock ...
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WO/2024/016951A1 |
The present invention relates to a duty cycle adjuster, comprising: a first duty cycle adjustment (DCA) module, wherein the first DCA module comprises M adjustment units, which are connected in parallel, each adjustment unit comprises an...
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WO/2024/019493A1 |
An electronic device according to an embodiment disclosed in the present document may comprise an antenna, a transceiver, an amplifier disposed on a transmission path electrically connected to the antenna and the transceiver, a filter el...
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WO/2024/015151A1 |
A receive clock generated at a receiver coupled to a one-wire bus is synchronized in each clock cycle, permitting reception of a data frame of unlimited length without clock overrun or underrun. A base clock signal provided by an oscilla...
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WO/2024/011768A1 |
The embodiments of the present disclosure relate to the field of semi-conductors, in particular to a delay detection circuit of a delay-locked loop, a delay-locked loop circuit, and a storage apparatus. The delay detection circuit of the...
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WO/2024/015674A1 |
An apparatus for synchronizing frequency to a symbol timing, the apparatus including: a master oscillator to generate a master clock signal; an interpolator to accumulate a frequency error estimate between a symbol timing frequency and t...
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WO/2024/008579A1 |
A delay-locked loop, DLL, circuit (10) for generating a signal that has a defined delay or phase shift comprises a pulse generator (12) configured to generate a pulse signal (Spulse) that is input to a circuit (14) having an unknown dela...
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WO/2024/008299A1 |
A transmitter is disclosed for operation with restricted power consumption. The transmitter comprises a signal generation oscillator configured to provide a signal for transmission, a phase-locked loop (PLL) configured to calibrate an os...
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