DESCRIPTION

TECHNICAL FIELD

The present invention refers to the field of electronics. In more detail, the present invention concerns an electronic circuit that realises an analog artificial neuron for neuronal network and a related neuronal network comprising a plurality of such artificial neurons, as well as integrated devices comprising said neuronal network.

BACKGROUND

The use of artificial intelligence algorithms, abbreviated to Al, is widespread in a multitude of technological application fields, particularly where a large amount of information is available that is difficult to process efficiently by means of traditional analysis systems. An example of application in which the artificial intelligence algorithms are widely used is image processing.

In particular, algorithms based on artificial neural networks - referred to as ANN acronym for “Artificial Neural Network’ or, more simply, NN “Neural Network" - are particularly widespread. An NN is a mathematical model of computation based on the structure of the biological neural networks. The model comprises a plurality of artificial neurons organised in several levels in which the artificial neurons of one level are connected to one or more artificial neurons of the following level according to a structure derived from the information provided as input during a learning phase of the NN. The NNs are non-linear structures that make it possible to simulate complex relationships between inputs and outputs that are difficult to represent rigorously through analytical functions.

In general, the systems known in the art comprise NNs simulated by means of a computer - i.e., NNs implemented via software - or are realised via appropriately configured programmable logic devices (FPGAs, microcontrollers) - i.e., NNs implemented via hardware.

However, these solutions require a substantial processing of the input signals in order to enable them to be efficiently processed by the NN and ensure reliable results in output from the NN.

The need to process the input signals requires the provision of elements - software and/or hardware - for digitising and pre-processing the input signals, with a consequent need to provide the necessary computational capacitance - in particular, in the case of software implementation - and/or dedicated circuit elements - in particular, in the case of hardware implementation - to perform such input signal processing. This results in non-negligible energy consumptions and sizes of integration areas, which limit or at least complicate the direct use of NNs in sensor groups, especially when powered through batteries like in the case of loT systems.

In an attempt to solve the problems highlighted above, US 2021/051284 proposes an imaging circuit which comprises a circuit to extract features from subgroups of pixels of an image in analog mode. The imaging circuit includes pixels that generate respective signals, which are weighed by using adjustable weighing circuits. The weighted signals generated by the pixels are combined to obtain an output neuronal voltage for at least one layer in a neural network.

Although the circuit proposed by US 2021/051284 allows, to some extent, to reduce the energy and integration area consumptions compared to an all-digital circuit, the actual processing of the information is performed digitally and thus requires the analog-to-digital conversion of the signals pre-processed by the circuit that extracts the features from sub-groups of pixels.

Y. Tsividis, and D. Anastassiou “Switched-capacitor neural networks" Electronics Letters 23 pages 958-959, 1987, describes a neural network comprising a plurality of switched-capacitor circuits that sample an input signal and deliver it as input into a circuit block consisting of an inverter and a capacitor.

The circuit for neuronal network described is not sufficiently versatile from both an implementation and a production point of view. In fact, a precise knowledge of the neuronal network to be implemented is necessary before proceeding to realise the circuit itself.

B. Nursultan et al: “Perceptron Linear Function Design with CMOS-Memristive Cricuits", Cornell University Library, Ithaca, NY, 20 May 2018, proposes an analog perceptron comprising a precision half-wave rectifier and a plurality of memristors having a terminal connected to the input of the precision rectifier and a terminal connected to an input terminal to receive a signal.

W. Yang et al: “Programmable Switched-Capacitor Neural Network for MVDR Beamforming”, IEEE Journal of Oceanic Engineering, IEEE Service Center Piscataway, NJ, US, vol.21 , no.1 , 1 January 1996, describes an artificial analog neuron according to the preamble of claim 1.

OBJECTS AND SUMMARY OF THE INVENTION

It is an object of the present invention is to overcome the drawbacks of the prior art.

In particular, it is an object of the present invention is to provide an analog circuit capable of performing the operations of an artificial neuron adapted to form a neuronal network for artificial intelligence applications.

A further object of the present invention is to provide an artificial neuron adapted to form an analog neuronal network with low energy consumption by directly processing the analog signals coming from a sensor array without the need for analog/digital conversion.

A further object of the present invention is to propose an analog circuit capable of implementing a neuronal network that is efficient in terms of operations per second with respect to the absorbed power.

A further object of the present invention is to propose a compact and integrated electronic circuit capable of implementing a neuronal network.

A further object of the present invention is to propose a compact electronic device that integrates the pre- amplification circuits of the signals coming from the sensor array and an analog neuronal network in the same circuit, directly delivering the processing result.

A further object of the present invention is to present an efficient, compact and low-consumption artificial intelligence-based system for determining the gamma-ray interaction position.

A further object of the present invention is to present an efficient, compact and low-consumption artificial intelligence-based system for processing images from sensors.

These and other objects of the present invention are achieved by a system incorporating the features of the annexed claims, which form an integral part of the present description.

According to a first aspect, the present invention is directed to an artificial neuronal network.

The artificial neuron comprises a plurality of input terminals, each of which receives a respective analog input signal, a plurality of capacitors, each of which is programmable to exhibit a respective desired capacitance, and an operating element adapted to combine a plurality of voltage values according to a predetermined mathematical function. In particular, each voltage value is proportional to the electric charge accumulated in a respective capacitor of the plurality of capacitors. Furthermore, a plurality of switches configured to switch the artificial neuron between a first phase, in which the plurality of capacitors is charged by the corresponding analog input signal, and a second phase in which the plurality of capacitors is connected in parallel to the operating element combines the plurality of voltage values proportional to the plurality of electric charges accumulated in the plurality of capacitors.

Advantageously, a first terminal of each programmable capacitor can be selectively connected to a reference terminal, by means of a first switch of the plurality of switches or to an input terminal of the operating element by means of a second switch of the plurality of switches, and a second terminal of each programmable capacitor can be selectively connected to the input terminal of the operating element, by means of a third switch of the plurality of switches, or to the reference terminal by means of a fourth switch of the plurality of switches.

In addition, during the second phase, at least one programmable capacitor has the first terminal connected to the reference terminal by the first switch and the second terminal connected to the input terminal of the operating element by the third switch to deliver a first voltage value to the operating element.

Alternatively, during the second phase, at least one programmable capacitor has the first terminal connected to the input terminal of the operating element by the second switch and the second terminal connected to the reference terminal by the fourth switch to deliver a second voltage value to the operating element, the second voltage value being opposite to the first voltage value.

The artificial neuron according to the present invention comprises a plurality of switches that enable the charging and processing phases of the artificial neuron to be effectively controlled. Through a limited number of control signals, it is possible to simultaneously control the charging phase and the subsequent charge combination of a plurality of programmable capacitors. In particular, the artificial neuron according to the present invention allows each input to be weighed with both positive and negative weights with an extremely compact and simple, yet reliable structure.

In one embodiment, each programmable capacitor comprises a first terminal and a second terminal, a plurality of capacitors, and a plurality of programming switches. In particular, each capacitor is placed in series with a respective switch. Furthermore, a first capacitor-switch series is connected to the first terminal and to the second terminal, and the remaining capacitor-switch series are connected in parallel with each other and in series with a sharing switch, wherein the series of the sharing switch and of the parallel of the capacitor-switch series is connected to the first terminal and to the second terminal, in parallel to the first capacitor-switch series.

Each switch of this plurality of programming switches is kept closed or open in the second phase to define a desired value of the capacitance of the programmable capacitor. In detail, the desired value of the capacitance of the programmable capacitor corresponds to the combination of the capacitances of the capacitors connected by the closed programming switches.

The artificial neuron according to the present invention has a compact structure that is fully realisable in standard CMOS technology and is capable of performing a MAC function - an acronym for Multiply and Accumulate -, i.e. the elementary function of the artificial intelligence algorithms based on neuronal networks, in a fully analog manner. Furthermore, the Applicant has found that the artificial neuron according to the present invention operates more energy-efficiently than digitally implemented artificial neurons that require digitisation of the analog input signals.

The analog circuit according to the present invention thus allows the typical operations of an artificial neuron to be performed in the charge domain. In particular, the analog circuit allows the capacitance values of the programmable capacitors to be varied particularly efficiently.

In one embodiment, the plurality of switches connecting the capacitor of the first capacitor-switch series has a lower capacitance value than the capacitance value of the capacitors of the remaining capacitor-switch series.

Preferably, each capacitor of the remaining capacitor-switch series has a capacitance value that is a multiple of the capacitance value of the capacitor of the first capacitor-switch series. Advantageously, the multiplicative factor of the capacitance values can take on any value within the set of the positive rational numbers. Even more preferably, the capacitors included that form a programmable capacitor form a sequence of capacitors each of which has a capacitance greater than the capacitance of the previous capacitor of the sequence.

In a particularly advantageous embodiment, the capacitors forming a programmable capacitor have a capacitance equal to the capacitance of the capacitor of the first capacitor-switch series multiplied by a multiple of two.

Thanks to this structure of the programmable capacitors, it is possible to obtain a wide variety of capacitance values (2 ^N where N is the number of capacitors) which can be easily and efficiently selected. This in turn makes it easy to obtain the desired granularity of the weights to be assigned to each input signal received by the artificial neuron.

Preferably, during the first phase - in which the plurality of capacitors is charged by the corresponding analog input signal - the sharing switch is kept open, thereby accumulating electric charge only on the capacitor of the first capacitor-switch series, typically the one of lesser value, whose charge with the analog signal therefore involves the least expenditure of energy. Subsequently, the sharing switch and the switches of the capacitor-switch series are closed in a third phase - performed before switching in the second phase. This allows the charge accumulated on the capacitor of the first capacitor-switch series to be shared with each capacitor of the capacitor-switch series.

This sharing of the charge makes it possible to considerably reduce the energy absorbed by the artificial neuron during the charging phase, as well as the time required to complete the charging of the capacitor of lower capacitance among those forming the programmable capacitor.

The artificial neuron thus realized allows each input to be weighed with both positive and negative weights with a simple and reliable control system.

In one embodiment, a pair of supply voltage values of the operational amplifier are set to a maximum value and a minimum value so as to obtain an output voltage value limited to values between the maximum value and the minimum value.

This management of the supply voltage of the operational amplifier makes it possible to implement an activation function of the ReLU type - acronym for Rectified Linear Unit - in particular a clipped one in an extremely simple and effective manner, without the need for providing a dedicated circuitry.

In one embodiment, the operational amplifier comprises a compensation terminal to which is connected a further programmable capacitor, the further programmable capacitor being programmed to present a capacitance inversely proportional to the plurality of capacitors connected to the virtual ground terminal of the analog integrator circuit.

In this way, it is possible to guarantee a good stability in the operation of the operational amplifier despite the variability of the capacitance in input to it.

In one embodiment, during the second phase the first terminal of the at least one programmable capacitor of the plurality of capacitors is connected to the reference terminal and the second terminal of the at least one programmable capacitor is connected to the virtual reference terminal of the analog integrator circuit to add the electric charge accumulated in the at least one programmable capacitor to the electric charge accumulated in the other programmable capacitors of the plurality of capacitors. Alternatively, the first terminal of the at least one programmable capacitor of the plurality of capacitors is connected to the virtual reference terminal of the analog integrator circuit and the second terminal of the at least one programmable capacitor is connected to the reference terminal to subtract the charge accumulated in the at least one programmable capacitor from the charge accumulated in the other programmable capacitors of the plurality of capacitors.

The artificial neuron according to the present invention makes it possible to selectively add or subtract the electric charges accumulated in the capacitors in a simple and efficient manner.

A different aspect of the present invention concerns a neuronal network comprising a plurality of artificial neurons according to any one of the preceding embodiments organized in two or more levels. Each level receives as input a plurality of external input signals typically from a sensor array, or a plurality of internal output signals generated by a previous level of the neuronal network. Similarly, each level delivers as output a plurality of internal output signals or one or more external output signals.

In an alternative embodiment, the neuronal network comprises a plurality of artificial neurons according to any one of the preceding embodiments, wherein the artificial neurons are organized in a single level. Advantageously, the first terminal of each programmable capacitor of at least one artificial neuron is selectively connectable to a respective input terminal or to a respective level output terminal.

Preferably, the plurality of switches comprises an additional switch adapted to selectively connect the first terminal of at least one respective programmable capacitor to an output terminal of the operating element, corresponding to the respective level output terminal.

Even more preferably, during an initial first phase the first terminal of each programmable capacitor of the at least one artificial neuron is connected to the respective input terminal of the neuronal network to receive an input voltage value, and during at least a following first phase the first terminal of each programmable capacitor of the at least one artificial neuron is connected - by closing the further switch - to the respective output terminal. The output terminal corresponds to the output terminal of the same artificial neuron to which the at least one programmable capacitor belongs. Alternatively, the neuronal network comprises a routing module adapted to connect the output terminal of at least one first artificial neuron to the first terminal of each programmable capacitor of at least a second artificial neuron.

The neuronal network according to the present invention has a compact structure, easily scalable and adapted to be integrated by means of standard CMOS technology processes. Furthermore, the neuronal network is able to process analog signals directly, thereby eliminating the need for analog -to-digital conversion units for the input signals. This results in a reduction of the complexity, power consumption and the area required to integrate the neuronal network. In particular, the neuronal network comprising a single level of reprogrammable artificial neurons adapted to receive the outputs calculated by the level itself at the previous iteration offers a considerable advantage in terms of both versatility of use and space occupation on silicon, at the price of an extremely limited increase in control complexity.

A different aspect of the present invention concerns an integrated device in CMOS technology comprising the neuronal network described above, a control unit and a memory unit. In the device, the control unit regulates the value of each programmable capacitor of the artificial neurons according to information stored in the memory unit, and periodically switches the circuit between the first phase and the second phase.

The device described above can be easily realised through standard integration processes and lends itself to being integrated together with one or more sensors from which it receives the input signals to be processed, with great advantages from the point of view of the miniaturisation, power savings and ease of use.

Furthermore, in one embodiment, the device, or more generally the circuit that realises each artificial neuron, can be integrated monolithically (i.e. on the same silicon substrate) to other elements of an information acquisition and processing system. For example, the device can be integrated in a single substrate together with pre-amplification stages of the input signals and/or with post-processing stages of the output signals generated by the neuronal network.

A different aspect of the present invention concerns a system comprising a particle detector and the integrated device described above. The particle detector comprises an array of particle detector elements, each of which generates an electrical signal indicative of the detection of one or more particles. The electrical signals generated by the array of detector elements are input to the neural network as an external input signal. Advantageously, the neural network is trained to generate at least one pair of external output signals indicative of a position - e.g., with respect to a two- or three-dimensional coordinate system - where an interaction has taken place with the one or more detected particles and the particle detector.

In one embodiment, the system is a scintigraphy system and the particle detector is a gamma ray detector. In this case, the gamma ray detector comprises a scintillator crystal coupled to a photodetector array. Specifically, an interaction between a gamma ray and the scintillator crystal generates a plurality of photons and each photodetector generates an electrical signal proportional to a number of photons absorbed. In this system, the electrical signals generated by the photodetectors of the array are, preferably, pre-amplified (filtered and converted from current pulses to voltages corresponding to the peak amplitude) and input to the neural network, which is trained to generate at least one pair of external output signals indicative of a position where the interaction has taken place between the gamma ray and the scintillator crystal.

In other words, the output signals can directly report the spatial coordinates of the event that the system sets out to analyse.

The system according to the present invention makes it possible to detect the position of an interaction between gamma rays and the detector in a precise, accurate and quick manner. In addition, the high scalability of the neuronal network included in the system makes it possible to realise systems with a high number of channels, suitable for the realisation of e.g. scanners with a wide field of view, such as the “whole- body” PET systems like the Pet-Explorer systems currently under development.

The system according to the present invention makes it possible to detect the interaction position also more generally in systems for detecting ionising particles or other events being studied or applied in the field of physics, in a simple, compact and energetically advantageous manner.

Further features and objects of the present invention will become more evident from the description below.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be described below with reference to some examples, provided for explanatory and non- limiting purposes, and shown in the accompanying drawings. These drawings illustrate different aspects and embodiments of the present invention and reference numerals illustrating structures, components, materials and/or similar elements in different drawings are indicated by similar reference numerals, where appropriate.

Figure 1 is a schematic representation of a neuronal network that can be realised with the analog circuit according to an embodiment of the present invention;

Figures 2A and 2B are a side section view and a top view, respectively, of a gamma ray detector with a pixelated array of photodetectors according to a structure known in the art;

Figure 3 is a circuit diagram of a level of the neuronal network according to an embodiment of the present invention;

Figure 4 is a simplified circuit diagram of an artificial neuron used in the neuronal network according to an embodiment of the present invention illustrating in detail a set of control switches for the artificial neuron;

Figure 5 is a circuit diagram of an alternative programmable capacitor used in the artificial neuron of Figure 4 according to an embodiment of the present invention;

Figure 6 is a block diagram of a gamma ray detection system employing the neuronal network according to an embodiment of the present invention;

Figure 7 is a flow chart of the operation of the neuronal network included in the system in Figure 6, and

Figure 8 is a circuit diagram of principle of a single-level neural network according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

While the invention is susceptible to various modifications and alternative constructions, certain preferred embodiments are shown in the drawings and are described hereinbelow in detail. It must in any case be understood that there is no intention to limit the invention to the specific embodiment illustrated, but, on the contrary, the invention intends covering all the modifications, alternative and equivalent constructions that fall within the scope of the invention as defined in the claims.

The use of “for example”, “etc.”, “or” denotes non-exclusive alternatives without limitation, unless otherwise indicated. The use of “includes” means “includes, but not limited to” unless otherwise indicated.

With reference to Figure 1 , a generic artificial neuronal network, NN 1 in the following, comprises a plurality of input terminals In ₁ - In _N (with N positive integer), one or more outputs O ₁ - O _M (with M positive integer) and a plurality of hidden levels 10 (2 in the example considered), each comprising a plurality of nodes or artificial neurons 20 (each level comprising 32 artificial neurons in the example considered).

In this example, NN 1 is adapted to analyse signals delivered by a gamma ray sensor, e.g. for medical applications. As illustrated schematically in Figures 2A and 2B, a generic gamma ray detector 30 comprises a scintillator crystal 31 coupled to an array 32 of N photodetectors (64 photodetectors, for example). As is well known, when a gamma ray y (illustrated schematically in Figure 2A) strikes a portion of the scintillator, photons ph are generated (illustrated schematically in Figure 2A) that hit the photodetectors of the array 32, each of which generates an electrical signal proportional to the amount of photons absorbed. Generally, the charge generated by the photodetectors is converted into voltage by a multi-channel pre-amplification circuit (not illustrated) and delivered to the processing unit. In this case, each of the input terminals Ini-N of the NN 1 is connected to an output terminal of the gamma ray detector 30. On each input terminal Ini-N of the NN 1 there is, therefore, a voltage VINI-N indicative of the photons absorbed by a corresponding photodetector of the array 32. The NN 1 is configured to deliver via a pair of outputs O ₁ and O ₂ a pair of output voltages V _Out1 , V _out2 which provide an indication of an x,y coordinate of the array 32 of photodetectors representative of the position in the scintillator crystal 31 at which an interaction has taken place with a gamma ray.

In the embodiments of the present invention, each level 10 of the NN 1 is realised by an analog circuit illustrated in Figure 3.

In detail, the generic j-th level 10 comprises a plurality of level input terminals, or more briefly level inputs L _INi , each of which is connected to a first terminal of a plurality of programmable capacitors C _i,j Specifically, each level input L _INi is connected to a J number of programmable capacitors C _i,j corresponding to the number of artificial neurons 20 of the level 10. A second terminal of each programmable capacitor C _i,j is connected to the negative terminal of a corresponding operational amplifier OA _j . In other words, to the negative terminal of the generic j-th operational amplifier OA _j there are connected the second terminals of I capacitors C _i,j - C _I,j , each of which is coupled, via the first terminal, to also a respective level input L _INi - L _INi . TO the same negative terminal of the generic j-th operational amplifier OA _j there is connected a first terminal of a feedback capacitor C _Fj , which has a second terminal connected to the output terminal of the same operational amplifier OA _j . Conversely, the positive terminal of the generic j-th operational amplifier OA _j is connected to a reference terminal - e.g. a ground terminal. The amplifier OA _j and the feedback capacitor C _Fj , thus connected, implement the function of an integrator circuit.

In summary, each j-th artificial neuron 20 of the level 10 comprises the capacitors C _i.j , which are connected via the respective second terminal to the virtual ground of an integrator circuit 21 formed by the j-th operational amplifier OA _j and by the j-th feedback capacitor C _Fj .

Accordingly, each artificial neuron 20 combines the electrical signals - i.e., input voltage values - on the I level inputs L _INi into a corresponding electrical output signal - i.e., an output voltage value V _oj -delivered on a level output terminal L _Oj according to the following mathematical function: where is the electric charge accumulated in the i-th capacitor C _i,j corresponding to the voltage at the i-th level input L _INi of the artificial neuron considered, and wherein it has been set that all the feedback capacitors C _Fj have the same capacitance equal to C _F . In other words, each artificial neuron 20 outputs a corresponding voltage value V _Oj corresponding to a sum of the input values of voltage on the level inputs L _INi which has been weighted for a respective weight W _i,j defined by the ratio between the capacitances of the corresponding programmable capacitor Ci,j and of the feedback capacitor CF. This corresponds to a fully analog execution of a MAC operation - an acronym for Multiply And Accumulate - i.e. an elementary function for artificial intelligence algorithms.

Preferably, the operational amplifier OA _j is configured to perform a trigger function at the same time as the MAC operation. Specifically, the amplifier OA _j is adapted to perform a ReLU operation - acronym for Rectified Linear Unit - of the 'clipped' type on the voltage V _Oj in output from the operational amplifier OA _j . Specifically, the supply values V _DD and Vcc of the operational amplifier OA _j (illustrated in Figure 4), or any other pair of values outside the linear operating regime of the OA _j in which the output is saturated, are set equal to a maximum value V _OMAX and a minimum value V _Omin , respectively (i.e., V _DD = V _OMAX , V _CC = V _Omin ), so as to obtain a limitation of the output value of voltage V _Oj limited by the operational amplifier OA _j between the maximum value V _OMAX and minimum value V _Omin desired.

The analog circuit performs a charging phase of the programmable capacitor Ci j at the input voltage value ViNjLi and an operation phase in which the electric charge accumulated on the I programmable capacitor C _i,j is combined in the output voltage value V _Oj of the j-th artificial neuron 20. For this purpose, the analog circuit comprises a plurality of switches, five switches in the example in Figure 4, adapted to selectively connect each of the programmable capacitors C _i,j to the respective level input terminal L _INi and to the negative terminal of the operational amplifier OA _j . For example, the switches are realised by means of CMOS transistors in a way that is known in itself and not discussed further here for the sake of brevity.

In detail, a first switch is placed between the level input terminal L _INi and the first terminal of the programmable capacitor C _i,j , a second switch is placed between the second terminal of the programmable capacitor C _i,j and a reference terminal, e.g. a ground terminal. A third switch is placed between the first terminal of the programmable capacitor C _i,j and a reference terminal, e.g. a ground terminal. A fourth switch is placed between the second terminal of the programmable capacitor C _i,j and the negative terminal of the operational amplifier OA _j . Finally, a fifth switch is placed between the first terminal of the programmable capacitor C _i,j and the negative terminal of the operational amplifier OA _j .

In the charging phase, the programmable capacitor C _i,j is charged by the voltage present at the respective level input terminal L _INi,j by closing the first switch and the second switch Subsequently, in the operation phase, the charge accumulated in the programmable capacitor C _i,j is injected into the feedback capacitance C _Fj by closing the third and fourth switches. Alternatively, the operation phase provides for closing the second switch and the fifth switch in this case the charge accumulated in the programmable capacitor C _i,j is injected into the feedback capacitor C _Fj , with opposite sign. In other words, with a control signal it is possible to vary the sign of the accumulated charge, which makes it possible to substantially double the weight W _i,j that can be defined by means of the ratio between the feedback capacitor C _Fj and the programmable capacitor C _i,j . For example, using 4 bits for the definition of the value of C _i,j , the use of the switch and the consequent inversion of the sign of the charge effectively introduce a fifth bit into the weight W _i,j .

As will be evident to the person expert in the art, the control signals can be used to simultaneously control the switches of all the J artificial neurons 20 of the NN 1 at the same time, in order to execute the charging phases of the programmable capacitors C _i,j and the following operation phase in parallel for all the artificial neurons 20 of the NN 1 . In other words, with 5 bits, of our example, it is possible to coordinate the processing of information by the NN 1.

Figure 5 schematically illustrates a programmable capacitor C _i,j according to a non-limiting embodiment of the present invention.

The generic programmable capacitor comprises four capacitors and five switches Preferably, each capacito and has a different capacitance from the other capacitors included in the programmable capacitor C _i,j . For example, the capacitor has twice the capacitance of the capacitor _, , the capacitor has four times the capacitance of the capacitor , and the capacitor has eight times the capacitance of the capacitor

Each capacitor is placed in series with a respective switch The capacitor series is connected to the circuit node N1 which defines the first terminal of the programmable capacitor and to a second circuit node N2 (highlighted in Figure 5) which defines the second terminal of the programmable capacitor C _1, , _j while the remaining three capacitor-switch series are connected in parallel to each other and are connected in series to the switch Finally, the switch and parallel series of the three capacitor-switch series is connected to the circuit nodes N ₁ and N ₂ . In other words, the series comprising the switch and the parallel of the three capacitor-switch series is in parallel with the capacitor and switch series.

In this way, it is possible to define 16 different discrete values of the capacitance of the programmable capacitor C _i,j according to the control configuration of the switches - i.e., by selecting which switches to close and which ones to keep open. In other words, through 5 control bits it is possible to set a desired capacitance value of the programmable capacitor C _i,j among 16 available values obtained through the combination - the sum - of the electric charges accumulated on one or more of the capacitors In this way, it is possible to obtain a plurality of weights - 16, in the example considered - which can be easily configured for the artificial neuron 20.

In this embodiment, only the capacitance is charged to the input voltage during the charging phase of the programmable capacitor C _i,j . In other words, the switch remains open during the charging phase in which the switches are closed. Thereafter, a charge sharing phase before the operational phase is provided. In the charge sharing phase, the switches are open, while the switches are closed and also the switch is closed, so that the charge accumulated on (a charge created by the value of input voltage applied between the plates of the capacitor) is shared among the capacitors connected in parallel. Following the charge sharing phase, the switches required to obtain the desired value of the capacitance of the programmable capacitor C _i,j are closed in such a way that one or more of the capacitors are connected in parallel with each other and are connected to the integrator circuit. Hence, only the charge shared among the capacitors actually connected to each other will be integrated into C _Fj . In other words, through 5 control bits, it is possible to set a desired capacitance value of the programmable capacitor C _i,j among 16 available values.

The switch allows to counteract unwanted charge injections when switching the switches In fact, when the switches open, they inject into the respective capacitor unwanted charge - a phenomenon known as Charge Injection - which disrupts the final charge value accumulated on the capacitor In particular, in the embodiment considered, the charge accumulated on the capacitors is cancelled at the beginning of the operations, for example by actuating the switches and at least one of the switches so that the capacitors are connected to the ground of the system. Thanks to the presence of the switch it is possible to keep the switches closed after discharge (reset) by opening the switch Consequently, in the charge sharing phase, there is no charge injection due to the switches thereby cancelling, or at least significantly reducing, possible errors due to this non-ideality.

The programmable capacitor C _i,j just described operates with a small amount of electric charge and modifies formula 1 as follows:

The latter embodiment makes it possible to significantly reduce the energy cost required to perform the charging operation. In fact, charging a capacitor has a maximum energy cost equal to C-V _MAX - V _DD , where C is the value of the capacitor to be charged, V _MAX is the maximum voltage programmed on the capacitor, and V _DD is the supply voltage of the circuit. In the embodiment in Figure 5, the energy cost in the charging phase is constant and equal to C _LSB -V _MAX -V _DD , where C _LSB is the capacitance of the capacitor - i.e. the capacitor with the smallest capacitance.

In data processing through neural networks, a merit parameter is represented by the ratio between the speed of the elementary multiplication and addition operation (measured in OPS, i.e. operations per second) and the relative power consumption (measured in watts W). This ratio is then quoted in OPS/W.

In the case of the NN 1 using programmable capacitors C _i,j with the structure described and illustrated in Figure 5, the energy spent at each level input terminal L _INi to charge the capacitance C _i,j of each of the 32 artificial neurons 20 of a level 10 is equal to: considering a value of 100fF for the elementary capacitance a maximum voltage value V _max to be charged equal to 2.5V and a supply voltage V _DD of the circuit equal to 3.3V (i.e., standard values for integrated devices in CMOS technology).

In the case of the first level 10 of the NN 1, i.e. level 10 receiving the 64 input signals V _IN1-N , the total energy absorbed by the 64 inputs I m -N is therefore equal to

The power is equal to this energy, divided by the time T required for an operation of the NN 1 - comprising a charging phase and an operation phase -, assumed to be equal to 20ns, is equal to:

The number of operations performed per second by a level 10, for example the first level of the NN 1 , in the case of 64 input signals V _IN1-N , is equal to: where the time T equal to 20ns required to perform each pair of multiplication and addition operations has always been taken into account. Accordingly, the efficiency of the NN 1 is given by the following ratio:

The Applicant has compared these merit parameters with the same parameters relative to an NN corresponding to the NN 1 described above but implemented by means of an FPGA - Artix-7 family produced by Xilinx® -. The NN implemented on FPGA requires a power P = 0.25 W- calculated with the Vivado® program - in order to perform the same operation.

Furthermore, the efficiency of the NN implemented via FPGA is equal to: (8)

The efficiency of the analog NN 1 according to the embodiment of the present invention is much more efficient than a corresponding NN realised by means of an FPGA. In addition, it must be considered that in the fully digital processing - such as the one performed by the FPGA considered above or by other digital accelerators - there is an additional power consumption associated with the digitisation of the input signals (performed by one or more analog-to-digital converters, ADCs), which operation is not necessary in the fully analog processing obtained by means of the NN 1 according to the embodiment of the present invention (which requires an additional power consumption limited to the one ensuring the operation of the amplifiers OA _j - using the current microelectronic technologies - substantially lower than the above-mentioned additional electronics used in the known circuits).

The NN 1 can be trained in the same manner as used for the NN of the digital type, i.e. by iteratively delivering sets of known signals in input to the NN 1 and by regulating the weights Wi.j until an expected result with a desired confidence is obtained in output. At the end of the learning phase, the configurations of the switches of each programmable capacitor C _i,j of the NN 1 are, preferably, stored in a memory unit 40, illustrated in the block diagram of a scintigraphy system 100 of Figure 6. In addition, during the learning phase, the sign of the weight W _i,j is also selected, and therefore an indication is stored in the memory 40 which imposes, during the operation phase to close the pair of third and fourth switches, in the case of weight W _i,j with a positive sign or, alternatively, to close the second and fifth switches in the case of weight W _i,j with a negative sign.

In the scintigraphy system 100 of Figure 6, during operation 1000 of the NN 1 - of which Figure 7 is a flow chart -, the charging phase is initially performed. In particular, the first and second switches and the only switch of each programmable capacitor C _i,j of each artificial neuron 20 of the NN 1 are closed, so that the corresponding capacitor is charged to the corresponding input voltage V I (step 1001). For this purpose, the scintigraphy system 100 comprises a control unit 50 generating control signals S1-5 to control, preferably synchronously, the switches included in each node 20 of the levels 10 of the NN 1 and a set of programming signals p _0-4 to control, preferably synchronously, the switches and of each programmable capacitor C _i,j of each artificial neuron 20 of the NN 1 . Advantageously, the control S1-5 and programming p _0-4 signals are based on instructions stored in the memory unit 40.

At the end of the charging phase, the charge sharing phase is performed. The first and second switches are open, while the switches of each programmable capacitor C _i,j of each artificial neuron 20 of the NN 1 are closed, so as to share the charge accumulated on the capacitor among all the capacitors (step 1002).

Subsequently, the switches of each programmable capacitor C _i,j of the NN 1 are kept closed or open - by means of the set of programming signals p _0-4 generated by the control unit 50 on the basis of the configuration information stored in the memory unit 40 - so as to define the capacitance value of the programmable capacitor C _i,j which allows obtaining the modulus value of the corresponding weight W _i,j defined in the training phase (step 1003).

In addition, the closing of the third and fourth pair of switches or, alternatively, the closing of the second and fifth switches is performed in the operation phase in order to assign the sign - positive or negative, respectively - of the corresponding weight W _i,j defined in the training phase (step 1004). Also in this phase, the control signals S1-5 are generated by control unit 50 based on the configuration information stored in the memory unit 40.

At the end of the operation phase, the output terminal L _Oj of each artificial neuron 20 delivers a corresponding output voltage value V _Oj (step 1005).

Preferably, though not in a limiting manner, each node 20 performs the charging phases of the respective J programmable capacitors C _i,j the charge sharing phase, and the operational phase synchronously with the other nodes 20 of the NN 1 .

However, it is clear that the above examples must not be interpreted in a limiting sense and the invention thus conceived is susceptible of numerous modifications and variations. For example, although the embodiments described above refer to the nuclear imaging, there is nothing to prevent the NN according to the embodiments described above from being used for other types of sensors, whether for image processing or for other sectors, mutatis mutandis.

Similarly, alternative embodiments (not illustrated) comprise imaging systems or simply particle detector systems other than gamma particles. In a non-limiting manner, such alternative systems may comprise a detector of photons, alpha particles, beta particles, etc. connected to a neuronal network according to one of the embodiments described above, the weights of which are calibrated to detect the position of the interactions between the detector and one or more particles of the desired type.

More generally, the analog circuit described above can be used in different applications of neural networks, Machine Learning and Artificial Intelligence techniques regardless of the specific field of application.

In an alternative embodiment (not illustrated), the programmable capacitors comprise a different number, lower or higher, of capacitors and switches based on the desired granularity for the weights applicable to each input signal to a respective artificial neuron.

In addition or as an alternative, one or more programmable capacitors can be realized according to any known technique other than the specific structure described above.

In a simplified embodiment (not illustrated and not claimed), the switch is omitted.

In one embodiment (not illustrated), the neuronal network comprises a routing module adapted to deliver to the first terminal of one or more programmable capacitors of at least one artificial neuron one or more output signals delivered by the output terminals of one or more artificial neurons of at least one previous level of the neuronal network and/or an input signal.

In a compact embodiment - illustrated schematically in Figure 8 - a single level 10 of artificial neurons 20 is used to implement an entire neuronal network 1A.

I n particular, the neuronal network 1 A comprises a level 10 of artificial neurons 20 similar to the one described above. Furthermore, each programmable capacitor Ci,i - CIJ of the generic j-th artificial neuron 20 is selectively connectable to a respective input terminal L _INi -N or to a respective level output terminal L _O1-j . For example, in the neuronal network 1 A, in addition to the first switch which is placed between the generic level input terminal L _INi and the first terminal of the programmable capacitors an alternative first switch is provided, which is placed between the generic level output terminal L _Oj and the first terminal of the programmable capacitors Ci, 1 - Ci,j

The neuronal network 1A is controlled as described below. Initially, the weights are programmed for the artificial neurons 20 - by acting on the switches and on the switches so as to acquire the input voltage values VINII-I and weigh them according to a predetermined scheme - in other words, at this phase the level 10 operates as the first level of the neuronal network 1A.

Subsequently, the weights for the artificial neurons 20 are reprogrammed - by acting in particular on the switch instead of on the switch on the switches and on the switches in order to acquire the output voltage values and weigh them according to a predetermined scheme . In other words, in the phases following the first one the level 10 operates as an internal level or the output level of the neuronal network 1A. In particular, at the generic phase I (with /> 1 ) the level 10 operates as a corresponding /-th level of the neuronal network 1 A, in which the programmable capacitors C _1,1 - C _I,J receive as input voltage values in the /th phase, the corresponding output voltage values generated in the previous phase 1-1 by the same level 10. The neuronal network thus constituted offers a considerable advantage in terms of both versatility of use and space occupation on silicon, at the price of an extremely limited increase in control complexity.

I n a more complex compact embodiment (not illustrated), the artificial neurons comprise a pair of first switch (|>ki, first alternative switch <|)kiA for each programmable capacitor Ci,i - CI,J. In this way, it is possible to simply introduce new input signals also into intermediate levels of the neuronal network in addition to the outputs of the artificial neurons of the previous level.

In an alternative compact embodiment (not illustrated), the neuronal network comprises a routing module adapted to store and/or deliver to a first terminal of at least one programmable capacitor of at least one or more artificial neuron the output signal generated at one or more terminals of the neuronal network level configured to operate as one of the previous levels of the neuronal network and/or an input signal.

In one embodiment (not illustrated), it is envisaged to perform an adaptive compensation of the integrator circuit. In this case, a compensation of the amplifiers OAu, preferably a “Miller”-type compensation, is carried out.

Considering the generic operational amplifier OA _j , it is envisaged to determine the value of the capacitance connected in input to the same. In other words, the capacitance value assumed by each programmable capacitor Ci J-C _i,j that is connected to the input terminal of the integrator circuit of the j-th artificial neuron 20 during a processing of a set of input voltages is determined. Based on the capacitance values of the programmable capacitors Ci J-C _i,j a value of compensation capacitance is determined, which is connected to an appropriate compensation terminal of the operational amplifier OA _j . For example, a second programmable capacitor is coupled to the compensation terminal of the operational amplifier OA _j and is programmed to compensate the operational amplifier OA _j as a function of the capacitance exhibited by the programmable capacitors Ci, j-C _i,j connected to the input terminal of the operational amplifier OA _j . Since the operational amplifier OA _j has growing stability as the total capacitance connected to its input grows, the value of the compensation capacitance is substantially inversely proportional to the total capacitance value connected to the input of the operational amplifier OA _j .

Naturally, all the details can be replaced with other technically-equivalent elements.

For example, an alternative embodiment (not illustrated) comprises an imaging system provided with a particle detector that delivers electrical signals also indicative of an elevation in which an interaction with a particle takes place, in addition to the position in a plane. In this case, the neuronal network comprises a third output and is trained to deliver a third output signal indicative of an elevation position of the detected interactions. In other words, the system is configured to provide an indication of a position in a three- dimensional (rather than two-dimensional as described above) reference system in which an interaction with a particle has been detected.

In conclusion, the materials used, as well as the contingent shapes and dimensions of the aforementioned devices, apparatuses and terminals, may be any according to the specific implementation requirements without thereby abandoning the scope of protection of the following claims.