Title:
MEMORY
Document Type and Number:
WIPO Patent Application WO/2024/093045
Kind Code:
A1
Abstract:
A memory, comprising: N storage arrays, which are sequentially arranged, wherein at least one storage array is a redundant array, at least one storage array is a main storage array, and the redundant array is used for replacing a faulted storage unit in the main storage array; and N selection circuits, which receive N-1 groups of data, wherein a first selection circuit receives first data, and is used for outputting or not outputting the first data to a first storage array according to a first selection signal; an Nth selection circuit receives an (N-1)th piece of data, and is used for outputting or not outputting the (N-1)th piece of data to an Nth storage array according to an Nth selection signal; and an ith selection circuit receives an (i-1)th piece of data and an ith piece of data, and the ith selection circuit is used for outputting the (i-1)th piece of data or the ith piece of data to an ith storage array according to an ith selection signal. In the solution, a plurality of selection circuits are provided, and according to a faulted unit replacement condition of a memory, the selection circuits are controlled to output corresponding data, so as to realize data processing under fault replacement, thereby ensuring the accuracy and reliability of data processing.
Inventors:
LU YAOHUA (CN)
Application Number:
PCT/CN2023/076133
Publication Date:
May 10, 2024
Filing Date:
February 15, 2023
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
G11C29/00
Foreign References:
| US6320800B1 | 2001-11-20 | |||
| US5438546A | 1995-08-01 | |||
| CN102165533A | 2011-08-24 | |||
| CN106710635A | 2017-05-24 | |||
| US20180349222A1 | 2018-12-06 |
Attorney, Agent or Firm:
LEADER PATENT & TRADEMARK FIRM et al. (CN)
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