Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2024/089570
Kind Code:
A1
Abstract:
Provided is a new semiconductor device. This semiconductor device has: a memory cell circuit having a first transistor and a capacitive element; and a read-out circuit having a second transistor and a third transistor. An element layer including the third transistor is provided on a substrate. A first insulator is provided on the element layer. A second insulator is provided on the first insulator. The first insulator has a first opening that is provided so as to extend in a direction generally perpendicular to the surface of the substrate. The second insulator has a second opening that is provided so as to extend in a direction generally perpendicular to the surface of the substrate, and a third opening. The second opening has a region overlapping the first opening. At least a portion of a dielectric included in the capacitive element is provided in the first opening. At least a portion of a semiconductor included in the first transistor is provided in the second opening. At least a portion of a semiconductor included in the second transistor is provided in the third opening.
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Inventors:
KUROKAWA YOSHIYUKI
MATSUZAKI TAKANORI (JP)
KOBAYASHI HIDETOMO (JP)
MATSUZAKI TAKANORI (JP)
KOBAYASHI HIDETOMO (JP)
Application Number:
PCT/IB2023/060658
Publication Date:
May 02, 2024
Filing Date:
October 23, 2023
Export Citation:
Assignee:
SEMICONDUCTOR ENERGY LAB (JP)
International Classes:
H10B12/00; G11C11/4091; H01L21/336; H01L21/8234; H01L27/06; H01L27/088; H01L29/786; H01L29/788; H01L29/792; H10B10/00; H10B41/20; H10B53/30; H10B53/40
Domestic Patent References:
| WO2020152522A1 | 2020-07-30 |
Foreign References:
| JP2022049605A | 2022-03-29 | |||
| JP2016149552A | 2016-08-18 | |||
| JP2014142994A | 2014-08-07 |
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