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WO/1996/041256A1 |
The present invention is directed to a display FIFO module for use in DRAM interface that includes a DRAM controller sequencer which prioritizes requests for DRAM access received from various modules, such as a CPU, a blit engine module,...
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WO/1996/041266A1 |
A partitioned memory (45) is divided into a number of large buffers (60), and one or more of the large buffers is divided to create an equal number of small buffers (65). Each remaining large buffer is associated with one small buffer, a...
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WO/1996/038778A1 |
A large FIFO memory device has its total available memory capacity partitioned into memory sections. The partitions are in the form of programmable delimiters in order to determine flexibly the size of the memory sections.
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WO/1996/037821A1 |
An availability status indicator circuit simultaneously indicates which of N circular buffer cells (CBCx, for x = 0 through N-1) are available for access. N cell status circuits are provided that correspond to the separate circular buffe...
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WO/1996/037873A1 |
A display controller capable of accessing graphics data from a shared system memory includes a first-in-first-out (FIFO) memory which stores a first quantity of graphics data. A FIFO write control circuit is coupled to the FIFO memory wh...
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WO/1996/037819A1 |
A method for performing a "rotate through carry" operation, utilizing iteratively a single bit left/right shifter, as well as a set of dedicated status flags.
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WO/1996/037820A1 |
A barrel shifter comprising: an n-bit by n-bit transistor array arranged into n rows an n colums, wherein the source of a transistor in one row is connected to the source of a transistor in the next row; a first plurality of multiplexors...
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WO/1996/035986A1 |
A data to be processed by CPU (11) is sequentially read from an external storage device (21), and transferred to first and second memories (24, 25) alternatively. CPU (11) accesses the one of the first and second memories (24, 25) altern...
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WO/1996/033455A1 |
Described is a shifting structure which separates a shifting operation into partial shifts which can be executed in different pipeline stages. In a first pipe stage, an operand is read out and at least one partial shift is accomplished b...
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WO/1996/033457A1 |
Described is a floating point processor comprising a multiply section and an add section, for performing a multiplication-add operation comprised of a multiplication operation prior to an addition operation which is using the result of t...
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WO/1996/032672A1 |
An apparatus and methods are provided for pre-compressing data to be sent to peripheral device (30) in a computer system, sending the data to a peripheral device (30) as a compressed data stream, and decompressing the data for use in the...
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WO/1996/031820A1 |
A method for managing a buffer queue that stores a data queue, wherein the data queue comprises a set of n data elements, n being at least zero. A head pointer is stored at a first location, which may be in a cache controlled by a first ...
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WO/1996/030825A1 |
In a storage system with a store (SP) operable as a ring store, an address decoder (AD) which can be allocated thereto and an address counter (AZ) controlling the address decoder (AD) with an adjustable initial value, the store (SP) has ...
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WO/1996/029644A1 |
The invention relates to an arrangement and a method respectively for handling or getting access to a digital buffer in a digital buffer memory (JBUM) wherein to each digital buffer a set of pointers is arranged in a reference memory (RE...
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WO/1996/025703A1 |
The invention concerns a method and a device for buffering between two synchronously clocked devices which send and receive data word packets, output being enabled as soon as the number of output clock pulses after the beginning of a dat...
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WO/1996/024208A1 |
This invention makes it possible to improve the speed of data transfer between LSIs operating by the same reference clock CKs. An internal clock CK1 of an LSI (14) is outputted from a circuit (41) to a clock line (42) at the timing at wh...
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WO/1996/023252A1 |
A data buffer includes a number of data storing elements (202), a tree shaped structure (218) of multiplexer elements (216), a write address generator (21), and a read address generator (214). The data storing elements have data inputs c...
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WO/1996/023359A1 |
A data encoder, data decoder, data encoding method, and data decoding method for encoding and decoding original data by using a simple algorithm while minimizing encoding errors. A means (1a) divides original data, such as sound data, in...
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WO/1996/022569A1 |
A self-diagnostic asynchronous data buffer includes an addressable buffer having a write address determined by a write counter and a read address determined by a read counter. A write clock controls storage into the buffer and updating o...
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WO/1996/021897A1 |
A data transmission system, in which data streams shall be transmitted with great speed between a sending clock domain and a receiving clock domain, which operate with mutually different clock speeds, includes two system part circuits (2...
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WO/1996/017293A1 |
A processor (109) includes a decoder (202) being coupled to receive a control signal (207). The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address c...
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WO/1996/017289A1 |
The processor (109) includes a decoder (202) being coupled to receive a control signal (207). The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address...
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WO/1996/010788A1 |
A variable-length bit data processing circuit includes first, second and third one-word registers (12, 20, 22). Data from a memory is loaded to the first register (12), and variable-length bit data is taken out from the third register (2...
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WO/1996/002095A1 |
A two stage desynchronizer (10) is provided to receive a gapped data component of an STS-3C(STM-1) signal and provide therefrom an ungapped DS-4NA (E4) data signal. The first stage (10a) includes a data byte formation block which takes t...
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WO/1996/000418A1 |
A system and method for storing data in a linked list memory architecture maintains several key list parameters. When data to be stored is received, a memory manager determines the list in which the data belongs and retrieves several of ...
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WO/1995/032477A1 |
A system for database (62) compression by selection (54) and application (52) of one or more data compaction methods to the fields of a database. A compaction method is applied to a field if the field data characteristics satisfy the com...
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WO/1995/022819A1 |
A method and apparatus for implementing a vocoder in an application specific integrated circuit (ASIC) is disclosed. The apparatus contains a DSP core (4) that performs computations in accordance with a reduced instruction set (RISC) arc...
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WO/1995/020198A1 |
A method and system for formatting numerical information. An object-based operating system provides various number formatting services. Some objects scan text and convert the text to numerical information, and convert non-text numerical ...
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WO/1995/010897A1 |
The present invention relates to a method for carrying out buffering in a digital telecommunication system, wherein data is transferred in frames the length of which is F bits. According to the method, data is written into the buffer mem...
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WO/1995/009398A1 |
A system for transmitting instructions in a processor node (200), where the communications processor (3) has a cache memory (6) of known capacity, comprises means for copying instructions (9) directly on the fly via the memory bus (4) to...
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WO/1995/006285A2 |
A data aligner transfers data from an input having N+1 byte lanes to an output having N+1 byte lanes. The data aligner includes a write data aligner and a read data aligner. The write data aligner includes a write shifter coupled to the ...
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WO/1994/019743A1 |
An intermediate processor (22) includes a main processor coupled to a plurality of front end circuits, and each front end circuit is coupled to a plurality of control unit interface circuits. Each control unit interface circuit is couple...
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WO/1994/017476A1 |
Interface apparatus for connection between a data handling device and a data communication medium to enable data to be transferred between the device and the medium, comprises a data alignment device (7, 8) coupled in use to the data han...
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WO/1994/017470A1 |
A queue system comprising a plurality of queues (20-23) where each is defined by a set of criteria, the queue system comprises a plurality of header registers (1-3) where each header register defines a queue in the queue system and a plu...
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WO/1994/015269A2 |
A system and method for allowing a component having a first byte ordering to effectively transfer information to another component having a second byte ordering. The present invention envisions embodiments where facilitation of the infor...
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WO/1994/012983A1 |
The invention provides fast generation of flag signals for devices, such as first-in first-out buffers, by looking-ahead and predetermining flag signals for possible future states of the device. The look-ahead signal generator, in one em...
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WO/1994/011811A1 |
A method and system for creating multi-lingual computer programs by dynamically loading messages is provided. In a preferred embodiment, a user specifies a preferred language in which the computer program will communicate. The computer p...
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WO/1994/011800A2 |
A low cost, high speed data storage system provides word-by-word stale data detection while avoiding the need to both read and write a single memory location during a memory read operation. Two flag data storage bits are provided for eac...
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WO/1994/009434A1 |
A method and apparatus is disclosed for partitioning a data buffer to create separate read and write buffers, wherein the boundaries between the buffers and the sizes of the buffers change dynamically depending upon the command mix recei...
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WO/1994/007199A1 |
A data path aligner transfer data from an input having N byte lanes with byte enable bits to an outpout having N byte lanes. The aligner includes first stage (S1(0) - S1(2)) having N-1 selector/registers, and a second stage (S2(0) - S2(3...
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WO/1994/003983A1 |
A single clock cycle adaptive data compressor/decompressor (1/2) with a string reversal mechanism (6) is described which can perform data compression and decompression at the rate of one uncompressed symbol per clock cycle. The compresso...
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WO/1993/025031A1 |
The invention relates to a method and an equipment for monitoring the fill rate of an elastic buffer memory used in a synchronous digital telecommunication system, such as the SDH or SONET system. To enable the monitoring of the fill rat...
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WO/1993/021575A1 |
A buffer memory architecture, method, and chip floor plan allows for significant reduction in the physical area required for a buffer memory of any given size in a microelectronic device. Buffer applications wherein random access to the ...
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WO/1993/021595A1 |
Method and apparatus for selecting samples for presentation on an output device, such as a display (24) or speaker (18), from a sequence of stored media samples, such as audio or video information. Position information is received from a...
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WO/1993/020516A1 |
A system and method for queuing, control and transfer of data between a host processor and a peripheral processor using an architecture and a data flow strategy of one or more virtual FIFO data structures stored in main memory and a hard...
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WO/1993/020506A1 |
A semiconductor floor plan layout for integrating a Data Dependency Checker (DDC) circuit and a Tag Assignment Logic (TAL) of a Register Renaming Circuit (RRC) circuit to conserve valuable semiconductor real estate. Floor plans of the pr...
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WO/1993/018922A1 |
An additional control device is mounted on an electronic equipment, and a large amount of data is transferred from the electronic equipment to the additional control device. An electronic control equipment in a printer outputs data to a ...
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WO/1993/018595A1 |
The SPE of an incoming STS-3 type signal is demultiplexed into three STS-1 payloads and fed to three FIFOs (45-1, 45-2, 45-3), and a byte which is synchronous with the TOH is tracked through the three FIFOs (45-1, 45-2, 45-3) to provide ...
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WO/1993/017381A1 |
A system performs dynamic segmentation analysis of attributes of a linear network, when the attributes are stored in a computer readable relational database. An embodiment of the system has an arrangement for converting data in the relat...
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WO/1993/014456A1 |
A barrel shifter capable of shifting input data in both directions, left and right, without increasing its circuit scale. In a barrel shifter unit circuit of a plural-stage barrel shifter, provided are a tristate buffer (11X) for left-sh...
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