| Document |
Document Title |
|
JP3700561 |
To solve such a problem that a device driver matching with the access management of two buffers becomes necessary undesirably accompanying the change of a speed difference absorbing buffer from single one to double buffers. A switcher 8 ...
|
|
JP2005196591 |
To provide a memory management method, and a memory management device capable of properly carrying out error correction by specifying a loss position even when there is a block in a ring buffer wherein sequential data is not stored and m...
|
|
JP3698869 |
To obtain an arithmetic circuit capable of reducing circuit scale. This arithmetic and logic unit is provided with a first holding part R1 to receive first input A1 and to hold it, a second holding part R2 to receive second input B1 and ...
|
|
JP3698987 |
To solve a problem that transferring cannot be performed before busy is released when an output destination port at the head of a queue buffer is busy even in the case of data requiring no order assurance when designating an output desti...
|
|
JP3693748 |
To obtain an OR gate with controllable width. The OR gate with a controllable width adopts plural controllable OR gate cells 100. Each cell 100 is provided with four data inputs of OR0, ST0, OR1, and ST1, single control input C0, and two...
|
|
JP3694339 |
PURPOSE: To provide an adaptive bit stream demultiplexing device used in a decoding system. CONSTITUTION: This device includes FIFO buffer modules 20, 60 and 80 having many buffers which temporarily store a bit stream, flag state detecto...
|
|
JP2005173775 |
To provide a data processor by which a decoding destination can start decoding operation in earlier timing than before and in which the storage capacity required for a storage means of storing previously inputted encoded data until the e...
|
|
JP2005174105 |
To provide a data collection system not requiring shift operation of a bit in a transfer device.The transfer device 20 has: a means generating a bit string 13 wherein bit strings 14q (q = A, B, C) are arranged in prescribed order by oper...
|
|
JP2005174090 |
To prevent an erroneous operation of data transfer caused by a collision of accesses between two devices.When a collision detection part 10 detects a state reading signal SR1 for reading a count value CNT of a counter 2 from a first devi...
|
|
JP2005175940 |
To provide a data compressor processing the selection of character string candidates shifted by one character and candidates composed of an original start character at a high speed without performing a complicated arithmetic operation.A ...
|
|
JP3691878 |
To transfer required data in respective conversion servers corresponding to original data at the time of converting the original data into target data successively through many kinds of the conversion servers. This system converts source...
|
|
JP2005157444 |
To improve the operation efficiency of a first-in first-out (FIFO) buffer in an FIFO control circuit.The FIFO control circuit can receive and transmit different kinds of data for each kind of the data in first-in first-out form. In addit...
|
|
JP2005148970 |
To reduce the size of tree-structure data, thereby rendering the data convertible into readable character-string data and vice versa.A data conversion part 2 converts the tree-structure data 1 into character-string data by converting it ...
|
|
JP2005141282 |
To provide an encryption system for normally performing processing, even when character data are encrypted, on the assumption that the encrypted character data are character data.This character data encryption program is provided with a ...
|
|
JP3680763 |
To provide a data transfer control unit which is capable of improving a bus in effective transfer rate and an electronic apparatus. When information such as CSW and data is allocated so as to be transferred through an end point EP2, a bu...
|
|
JP3680119 |
To solve the problem that it is necessary to update the number of MAXSTEP indicating a transition timing to the next processing each time the cycle of an output signal is changed for switching processing based on the result of the compar...
|
|
JP3681773 |
PURPOSE: To provide a first-in first-out buffer system which has an error detection and correction unit which detects and corrects an error generated in the first-in first-out buffer system. CONSTITUTION: M data storage modules 20A to 20...
|
|
JP2005134965 |
To shorten the time needed for normalization by accurately detecting a head non-zero position from input of carry propagation addition in a floating-point calculation.A step function Fi is defined which properly selects as a function val...
|
|
JP3679025 |
To pass data between asynchronous time bases using a universal memory. An A/D conversion section 1 converts an analog input image signal to digital input data by an input system CLK. An asynchronous buffer 2 converts input data being dri...
|
|
JP3675948 |
To provide a data converting method and its device efficiently converting data through the use of a single buffer memory by writing only valid data after arithmetic processing in a buffer memory. This device arithmetically processes a pr...
|
|
JP3671120 |
To greatly lighten the load on a host CPU when data are transferred from the host CPU to a sound processor which reproduces musical sound in real time. When the host CPU 14 as a transfer source transfers musical sound data, the host CPU ...
|
|
JP3670303 |
PURPOSE: To provide a data conversion method and a data conversion device by which data can automatically be converted into data of a system that is to be used. CONSTITUTION: Information on various conversion converters, which include th...
|
|
JP2005110291 |
To provide a video server system including a new architecture which generates a number of video output streams at relatively low cost, and controls them.The video server receives a user requirement through a distribution network. This re...
|
|
JP3666580 |
To efficiently transfer data according to a handshake method without shortening the internal clock cycle based on a burst transfer method. This DMA transfer control device includes a plurality of buffer memories 103 accumulating data, a ...
|
|
JP2005102242 |
To provide a video server system including a novel architecture capable of generating and controlling a number of video output streams at comparatively low cost.A video server receives a user request via a distribution network. The reque...
|
|
JP3665636 |
To realize reliable data transfer by maintaining matching of input and output pointers, especially without structural complexity, in a first-in, first-out (FIFO) system buffer device used, for example, in a disk controller. In the FIFO s...
|
|
JP3664054 |
To obtain a communication system that can efficiently transfer data with a comparatively large capacity from a wired block via a wireless block. A mobile phone 101 can access a contents server 105 from a base station 102 via mobile commu...
|
|
JP2005092412 |
To share a FIFO in a plurality of data paths without need to set FIFO capacity for each data path.A FIFO section 130 is constituted of a shift selector for shifting data of FIFO in a shape of N steps of a ring, and N pieces of FIFO with ...
|
|
JP2005084766 |
To provide a data conversion device for performing high speed data conversion in a small-scaled circuit configuration.DATA1(i) to DATAn(i) obtained by dividing DATA1 to DATAn by every u bits are continuously inputted by a variable cyclic...
|
|
JP3659408 |
To provide a data processor suitable for reducing a circuit scale and improving critical path to reduce operation load in performing multiplication and accumulation by a block floating system. This data processor is formed by a first shi...
|
|
JP2005078483 |
To reduce software process load by dispensing with access for one-bite unit in data access with arbitrary size of an FIFO memory.This FIFO memory controller comprises a size specifying means 106 capable of setting software specifying an ...
|
|
JP2005071366 |
To control a clock speed so as to optimize performance of a device within power/heat budgets of a system.Frequency managers (158, 180, 200) automatically select (408, 506, 708, 810, 812) a clock frequency to each of devices (146 to 156, ...
|
|
JP2005072832 |
To provide a data processing apparatus and a processing method for improving operability by preferably processing both jobs, if a job request by compression means or a decompression means concerning an external job transmitted from the o...
|
|
JP3655403 |
To enable more complicated digital signal processing by constituting a digital signal processing unit so as to handle fixed point data. A CPU 100 and a digital signal processing unit 104 whose operation is controlled by decoding an instr...
|
|
JP2005056106 |
To provide an integrated circuit for reducing a time required for the download of a program without using a high speed interface.A slave device 2 receives a program from a master device 1 in a burst mode, and judges that an address field...
|
|
JP3646644 |
To provide data transfer controller and electronic equipment, with which data exchanged on a high speed bus can be processed in a circuit to be operated at a low frequency. The data transfer controller is provided with a converting circu...
|
|
JP3645584 |
PURPOSE: To decrease an error, and to attain synchronous data transfer across an area boundary by using two single stage synchronous FIFO first-in first-out and N-2 stage multistage asynchronous FIFO instead of an N word multistage FIFO ...
|
|
JP3645298 |
PURPOSE: To reduce the accumulation of rounding errors in a series of arithmetic operations by rounding the result of division by a power of 2. CONSTITUTION: Words X=XN-1, XN-2ψ, X0 applied from an input terminal 111 in the figure are r...
|
|
JP3643270 |
To provide a data processor capable of easily operating other data for data processor with a different byte polarity. A byte order inverting circuit 14 inverts the order of arranging four linked bytes in the data of 32 bits expressing on...
|
|
JP3643822 |
To reduce the power consumption of a USB (Universal Serial Bus) interface circuit having OTG (On-The-Go) function. The noise removal and detection of a signal VBUS are performed in a detection part 100 according to a low-frequency clock ...
|
|
JP2005031868 |
To provide an electronic device capable of storing many pieces of character information, a display device for displaying a number of characters, and a character code compression method for compressing character information.A control part...
|
|
JP3641371 |
To provide a buffer memory circuit capable of accelerating a processing speed, reducing the number of parallel processings, performing high integration and preventing the generation of the stagnation of cells even in the case of handling...
|
|
JP2005025718 |
To provide a method, a device and a system for performing a packed multiply high with round and shift processing, and to provide a machine readable medium.The method comprises: a step for receiving a 1st operand having a 1st set of L dat...
|
|
JP2005025151 |
To provide a bidirectional shift register capable of judging whether the register operates normally in any bidirection without increasing inspection terminals, and a display device equipped with the bidirectional shift register.The bidir...
|
|
JP2005025680 |
To provide a method and device for precisely fetching a BCD signal to a controller regardless of the presence of a strobe signal or reading process in a change in voltage.The device for fetching the BCD signal to the controller comprises...
|
|
JP2005025637 |
To provide a method for compressing a program, the method distinguishing a command code region from a data region and compressing a program by means of a compression method suitable for each region.The method for compressing a program co...
|
|
JP3637586 |
To suppress missing in image data to be recorded on a prescribed recording medium. Image data sent from a digital video cassette recorder(DVCR) 2 are received by a 1394 communication section 11 and outputted to a FIF0 memory 12. When the...
|
|
JP3639713 |
To speedily actualize character code conversion by a single read of character data and to automatically reflect it on subsequent code conversion by outputting an alternative character and storing the character code and position in a conv...
|
|
JP2005018768 |
To provide a dual-port function which is operated as a double-port memory but can be realized from a conventional single-port memory cell to enable the production of a large FIFO memory.A network node 5 including a line card 20 for packe...
|
|
JP2005018672 |
To provide a method for storing in compact, analyzing at a high speed, updating, and preparing a structured document having the giant number of storages of information containing much graphical information and giant data size.The structu...
|
