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Patent Searching and Data


Matches 51 - 100 out of 9,226

Document Document Title
WO/2013/049764A2
An apparatus includes a register file including a logical circuit. The register file is configured to perform one or more logical operations in conjunction with the logical circuit. The logical operation is performed in response to the r...  
WO/2013/040708A1
In embodiments, the present invention provides method and system for determining if an existing pass log may be reused. The method may include associating an existing pass log with an encoding profile. The method may further include comp...  
WO/2013/033334A1
Systems and methods for adaptive bitrate streaming of alternative streams of video encoded at resolution and sample aspect ratio combinations and maximum bitrates in accordance with embodiments of the invention are disclosed. In one embo...  
WO/2013/026155A1
Systems and methods are provided for structuring information, including analyzing an original digital information file (DIF) to determine an information quantity (IQ) and an information value (IV). An initial manipulation process is appl...  
WO/2013/025637A1
According to an embodiment, an apparatus includes a data storage device. Data to be stored in the data storage device is level shifted from a first voltage domain to a second voltage domain prior to being stored within the data storage d...  
WO/2012/169032A1
The invention is a buffer apparatus provided with multiple input ports (3), multiple buffers (5) from which information input from the multiple input ports (3) is written, and at least one output port (7). The invention is provided with:...  
WO/2012/164813A1
Upon reading data from the main memory, an input unit (110) repeatedly starts and stops inputting the data to a compression execution unit (120) that executes lossless compression. A start address holding section (112) stores the start a...  
WO/2012/160108A1
Embodiments of the present invention provide an apparatus for synchronizing a data handover between a first clock domain and a second clock domain. The apparatus includes a calculator, a first-in-first-out storage, a synchronization puls...  
WO/2012/149742A1
Embodiments of the present invention relate to a signal order-preserving method and device. When data of a request signal from a corresponding first upstream device is written in a first FIFO storage, in the same clock cycle, invalid dat...  
WO/2012/127590A1
The purpose of the present invention is to perform endian conversion without affecting the internal processing performance of a system, and to perform endian conversion having a complex data structure. A CPU (101) is assumed to perform d...  
WO/2012/124100A1
The objective of the present invention is to achieve both the effect of reducing the amount of data stored in a storage device and the effect of shortening the processing time for the storage. A write control unit (14) executes in parall...  
WO/2012/116759A1
The invention provides microprocessor extensions for cooperating with a sequential arithmetic-logic unit (ALU) to execute a multiply-and-accumulate operation (MAc). The ALU performs a continuous sequence of accumulation instructions sync...  
WO/2012/117291A2
Various embodiments are provided for fully digital chaotic differential equation- based systems and methods. In one embodiment, among others, a digital circuit includes digital state registers and one or more digital logic modules config...  
WO/2012/111078A1
According to the present invention, the size of an applied 2N-branch non-contact Huffman tree is determined depending on where in a range the total number of types (X) of character information groups exists. The size of the 2N-branch non...  
WO/2012/106108A1
System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-d...  
WO/2012/084835A1
The invention provides a method for adding specific hardware on both receive and transmit sides that will hide to the software most of the effort related to buffer and pointers management. At initialization, a set of pointers and buffers...  
WO/2012/076391A1
A dedicated vector gather buffer (VGB) that stores multiple cache lines read from a memory hierarchy in one or more Logical Units (LUs) each having multiple buffer entries and performs parallel operations on vector registers. Once loaded...  
WO/2012/072862A1
An approach is provided for predicting and pre-fetching location information. A pre-fetching manager determines a predicted location associated with a device. Next, the pre-fetching manager retrieves location information based, at least ...  
WO/2012/038829A3
Systems and methods are provided for a first-in-first-out buffer. A buffer includes a first sub-buffer configured to store data received from a buffer input, and a second sub-buffer. The second sub-buffer is configured to store data rece...  
WO/2012/011726A3
A method and apparatus are provided for providing a DRM service in a user terminal apparatus providing an adaptive streaming service. Content protection information is received that includes information about multiple DRM systems applied...  
WO/2012/011726A2
A method and apparatus are provided for providing a DRM service in a user terminal apparatus providing an adaptive streaming service. Content protection information is received that includes information about multiple DRM systems applied...  
WO/2012/008669A1
Disclosed are a malicious code real-time inspecting device in a DRM environment and a recording medium for recording a program to execute a method thereof. A DRM module performs decryption and encryption during file reading/writing opera...  
WO/2011/154642A2
This processor (80) for processing digital data comprises at least one butterfly operator (82) for the execution of a fast Fourier transform computation, this butterfly operator exhibiting a pipelined architecture for the clocked recepti...  
WO/2011/112201A1
A method for encoding bits to be stored within a crossbar memory architecture performed by a physical computing system includes designating, with the physical computing system (100), a subset of crosspoints (306) within a crossbar matrix...  
WO/2011/085934A1
The present invention relates to a data buffer memory (104) and method for storing data in a data communications network, and to a data buffer system (100) comprising such a data buffer memory. The data buffer memory comprising a data se...  
WO/2011/075076A1
A method is disclosed to convert digital data using a memory card operatively engaged with an apparatus such as a digital camera having control buttons but that does not have a keyboard or keypad. The memory card comprises a central proc...  
WO/2011/071273A2
An SRAM based address generator is provided, which can perform a TCAM function that returns an address of data when the data is input. The address generator includes n bit position tables receiving n input sub-words each of which is comp...  
WO/2011/071273A3
An SRAM based address generator is provided, which can perform a TCAM function that returns an address of data when the data is input. The address generator includes n bit position tables receiving n input sub-words each of which is comp...  
WO/2011/058659A1
A FIFO buffer (1) comprises a packet storage buffer (10), a bank switch (17), a packet write control circuit (15), and a packet write start bank holding FIFO queue (19). The packet storage buffer (10) is capable of writing and reading da...  
WO/2011/046559A1
Systems and methods for information technology system change planning are described. In an information technology system change planning method in accordance with an embodiment, a change request is received on a network server (310). Dom...  
WO/2011/026212A1
A data broker method, apparatus and system is provided. The data brokerage system comprising: a profile server for executing a profile services application a native application format; a data broker engine connected to the profile server...  
WO/2011/015672A1
The invention relates to a system and to a method for visualizing decors, particularly wood decors. The system is characterized by at least one image projector (1, 2, 3) and a spatial projection surface (4) comprising different partial s...  
WO/2011/009591A1
An interfacing circuit comprising a First In First Out (FIFO) memory for exchanging data between a "data producer device" and a "data consumer device". The FIFO memory is controlled by first write control signals (WR, CLK_WR) and second ...  
WO/2011/010184A1
A signal processing system (100) comprising buffer control logic (142) arranged to allocate a plurality of buffers (144) for the storage of information fetched from at least one memory element (160). Upon receipt of fetched information t...  
WO/2010/127438A1
A system and method for transforming a software application comprising binary code and optionally associated data, from an original form to a more secure form. The method includes performing a combination of binary transmutations to the ...  
WO/2010/124356A1
A method and device are provided for converting or transforming a morph shape definition specified in a SWF file into a vector graphics shape definition including one or more vector graphics path definitions that can then be used by a ve...  
WO/2010/124357A1
A method and device are provided for converting or transforming a shape definition specified in a SWF file into a vector graphics shape definition. The vector graphics shape definition includes one or more vector graphics path definition...  
WO/2010/107650A1
A floating point unit includes a floating point adder to perform a floating point addition operation between first and second floating point numbers each having an exponent and a mantissa. The floating point unit also includes an alignme...  
WO/2010/083108A2
A system and method include a SerDes transmitter comprising a digital block operating in a digital voltage domain. The digital block can be configured to receive a first group of bits of data in parallel and store history bits from anoth...  
WO/2010/083108A3
A system and method include a SerDes transmitter comprising a digital block operating in a digital voltage domain. The digital block can be configured to receive a first group of bits of data in parallel and store history bits from anoth...  
WO/2010/077885A2
A method and apparatus for extending cache coherency to hold buffered data to support transactional execution is herein described. A transactional store operation referencing an address associated with a data item is performed in a buffe...  
WO/2010/076582A3
A theft protection method and promotion system for audio media for providing a secure and irreversible way to protect audio containing media content, while supplying an enhanced promotional potential. The inventive device includes a prop...  
WO/2010/078061A2
Certain embodiments of the present disclosure relate to methods for peak-to-average power ratio (PAPR) reduction of a transmission signal in a single carrier frequency division multiple access (SC-FDMA) system. The proposed methods and s...  
WO/2010/077885A3
A method and apparatus for extending cache coherency to hold buffered data to support transactional execution is herein described. A transactional store operation referencing an address associated with a data item is performed in a buffe...  
WO/2009/154838A2
A processor (16) and cache (40) is coupled to a system memory (13) via a system interconnect (12). A first buffer circuit (44) coupled to the cache receives one or more data words and stores the one or more data words in each of one or m...  
WO/2009/154838A3
A processor (16) and cache (40) is coupled to a system memory (13) via a system interconnect (12). A first buffer circuit (44) coupled to the cache receives one or more data words and stores the one or more data words in each of one or m...  
WO/2009/142671A1
A zero prediction method and apparatus for use in a reduced instruction set computer. The zero predictor (115) in use is connected by a controller (110) to an arithmetic unit (120). Different embodiments of the invention for use in addit...  
WO/2009/137910A1
A modular transcoder software system for transcoding a multimedia message includes a collection of software modules and objects for the dynamic construction of a series of complex, related or unrelated operations in the form of a transco...  
WO/2009/129824A1
The invention relates to a method and an engineering system, by means of which relationships can be automatically identified between CAD objects (12, 13, 14, 15) of different CAD models (4, 5). In order to allow this, the proposed method...  
WO/2009/128925A2
A method and apparatus to gain additional functionality of a microprocessor by adding an extended instruction set mode. In this mode, the result of executing an instruction may be changed without changing the instruction itself. In the e...  

Matches 51 - 100 out of 9,226