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Matches 51 - 100 out of 9,267

Document Document Title
WO/2014/113727A1
Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices with significantly reduced or eliminated Simultaneous Sw...  
WO/2014/097356A1
The purpose of the present invention is to reduce the processing time required for compression. A compression program executes a process on a computer, whereby, when data that appears multiple times in a file exists, data in a storage ar...  
WO/2014/097359A1
The purpose of the present invention is to generate compressed data that can be partially expanded while using a dynamically generated compression dictionary in a compression process. This compression program executes a process on a comp...  
WO/2014/097353A1
In one aspect of the present invention, a comparison process in data units that differ to data units constituting data to be compressed is suppressed with respect to data to be encoded. A compression program executes a process on a compu...  
WO/2014/070942A1
Communication of signals between mobile devices and automotive Controller Area Network (CAN) buses. An abstraction and communication device includes a connector, a mapping platform, and a transceiver. The connector is adapted to interfac...  
WO/2014/046930A1
Presented herein are techniques for detection and characterization of buffer occupancy of a buffer in a network device. Packets are received at a network device. The packets are stored in a buffer of the network device as they are proces...  
WO/2014/046742A1
An apparatus includes a plurality of channels (250), where each of the channels includes an asynchronous buffer (210), a latency determination block (211 ), a tap selection circuit (220), and a variable delay (202). A latency locator (21...  
WO/2014/027328A1
Data is written from a first domain (117) to a FIFO memory buffer (105) in a second domain(119). The first domain (117) uses a first clock signal, the second domain (119) uses a second clock signal and the memory buffer (105) uses the fi...  
WO/2014/006465A8
A method facilitates viewing of DICOM medical images by providing a 16-bit DICOM image on a computer readable storage medium, text-converted metadata of the DICOM image and an html-compatible conversion of the DICOM pixel data on a compu...  
WO/2014/006465A1
A method facilitates viewing of DICOM medical images by providing a 16-bit DICOM image on a computer readable storage medium, text-converted metadata of the DICOM image and an html-compatible conversion of the DICOM pixel data on a compu...  
WO/2014/001766A1
An arrangement for transferring a data signal (data_a) from a first clock domain (2) to a second clock domain (4) in a digital system. The arrangement has a signal input (6, 7) for receiving an input signal (data_a) from the first clock ...  
WO/2014/001764A1
A system (1) for transferring a data signal (sig_fast) from a first clock domain (4) to a second clock domain (8). The first clock domain (4) has a first clock (ck_fast) with a frequency greater than the frequency of a second clock (ck_s...  
WO/2014/001765A1
An arrangement for transferring a data signal from a first clock domain (bus_slow) to a second clock domain (bus_fast) in a digital system. The first clock domain (bus_slow) has a first clock (ck slow) with a frequency less than a freque...  
WO/2013/190690A1
A data predicted value generating unit (210) generates a predicted value (data predicted value) for source data (101) to be encoded on the basis of a history of the source data (101), which is floating point data. A data predicted value ...  
WO/2013/150107A1
The invention relates to a method for transferring data from a matrix of detector elements (D) to a memory of a data processing system by means of at least one slip ring. In said method, the data are combined in a plurality of blocks (B)...  
WO/2013/145599A1
For multiplexer classification for column compression of tabular data, Similar type data segments are classified into classes for grouping the data segments into compression streams associated with each one of the classes. The compressio...  
WO/2013/109683A1
Dual-voltage domain memory buffers, and related systems and methods are disclosed. To reduce area needed for voltage level shifters for voltage level shifting, latch banks are provided in a voltage domain of memory buffer read circuitry,...  
WO/2013/097393A1
Disclosed is a hardware abstract data structure, including a general interface (GI), a coherent interface (CI), a control and configure logic (CCL), an intelligent logic (IL) and a memory pool (MP). The GI is configured to implement the ...  
WO/2013/095337A1
A system and method for creating a guaranteed MSI latency by coupling a coprocessor, which may be a dedicated agent, to the existing front side bus ("FSB") in a processor (e.g., Intel® Atomâ„¢ processor) to handle deterministic interrup...  
WO/2013/091010A1
A method of outputting a media data sample at a media output device, comprising: receiving from a media capture device a media data sample and a timestamp associated with the received media data sample; associating the received media dat...  
WO/2013/083191A1
A queuing apparatus (1) having a queuing engine (2) comprising: a predetermined number, K, of queues, Q, wherein each queue Q has a number, N, of sub-queues, SQ, associated to a corresponding number, N, of input lanes of said queuing eng...  
WO/2013/049764A2
An apparatus includes a register file including a logical circuit. The register file is configured to perform one or more logical operations in conjunction with the logical circuit. The logical operation is performed in response to the r...  
WO/2013/040708A1
In embodiments, the present invention provides method and system for determining if an existing pass log may be reused. The method may include associating an existing pass log with an encoding profile. The method may further include comp...  
WO/2013/033334A1
Systems and methods for adaptive bitrate streaming of alternative streams of video encoded at resolution and sample aspect ratio combinations and maximum bitrates in accordance with embodiments of the invention are disclosed. In one embo...  
WO/2013/026155A1
Systems and methods are provided for structuring information, including analyzing an original digital information file (DIF) to determine an information quantity (IQ) and an information value (IV). An initial manipulation process is appl...  
WO/2013/025637A1
According to an embodiment, an apparatus includes a data storage device. Data to be stored in the data storage device is level shifted from a first voltage domain to a second voltage domain prior to being stored within the data storage d...  
WO/2012/169032A1
The invention is a buffer apparatus provided with multiple input ports (3), multiple buffers (5) from which information input from the multiple input ports (3) is written, and at least one output port (7). The invention is provided with:...  
WO/2012/164813A1
Upon reading data from the main memory, an input unit (110) repeatedly starts and stops inputting the data to a compression execution unit (120) that executes lossless compression. A start address holding section (112) stores the start a...  
WO/2012/160108A1
Embodiments of the present invention provide an apparatus for synchronizing a data handover between a first clock domain and a second clock domain. The apparatus includes a calculator, a first-in-first-out storage, a synchronization puls...  
WO/2012/149742A1
Embodiments of the present invention relate to a signal order-preserving method and device. When data of a request signal from a corresponding first upstream device is written in a first FIFO storage, in the same clock cycle, invalid dat...  
WO/2012/127590A1
The purpose of the present invention is to perform endian conversion without affecting the internal processing performance of a system, and to perform endian conversion having a complex data structure. A CPU (101) is assumed to perform d...  
WO/2012/124100A1
The objective of the present invention is to achieve both the effect of reducing the amount of data stored in a storage device and the effect of shortening the processing time for the storage. A write control unit (14) executes in parall...  
WO/2012/116759A1
The invention provides microprocessor extensions for cooperating with a sequential arithmetic-logic unit (ALU) to execute a multiply-and-accumulate operation (MAc). The ALU performs a continuous sequence of accumulation instructions sync...  
WO/2012/117291A2
Various embodiments are provided for fully digital chaotic differential equation- based systems and methods. In one embodiment, among others, a digital circuit includes digital state registers and one or more digital logic modules config...  
WO/2012/111078A1
According to the present invention, the size of an applied 2N-branch non-contact Huffman tree is determined depending on where in a range the total number of types (X) of character information groups exists. The size of the 2N-branch non...  
WO/2012/106108A1
System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-d...  
WO/2012/084835A1
The invention provides a method for adding specific hardware on both receive and transmit sides that will hide to the software most of the effort related to buffer and pointers management. At initialization, a set of pointers and buffers...  
WO/2012/076391A1
A dedicated vector gather buffer (VGB) that stores multiple cache lines read from a memory hierarchy in one or more Logical Units (LUs) each having multiple buffer entries and performs parallel operations on vector registers. Once loaded...  
WO/2012/072862A1
An approach is provided for predicting and pre-fetching location information. A pre-fetching manager determines a predicted location associated with a device. Next, the pre-fetching manager retrieves location information based, at least ...  
WO/2012/038829A3
Systems and methods are provided for a first-in-first-out buffer. A buffer includes a first sub-buffer configured to store data received from a buffer input, and a second sub-buffer. The second sub-buffer is configured to store data rece...  
WO/2012/011726A3
A method and apparatus are provided for providing a DRM service in a user terminal apparatus providing an adaptive streaming service. Content protection information is received that includes information about multiple DRM systems applied...  
WO/2012/011726A2
A method and apparatus are provided for providing a DRM service in a user terminal apparatus providing an adaptive streaming service. Content protection information is received that includes information about multiple DRM systems applied...  
WO/2012/008669A1
Disclosed are a malicious code real-time inspecting device in a DRM environment and a recording medium for recording a program to execute a method thereof. A DRM module performs decryption and encryption during file reading/writing opera...  
WO/2011/154642A2
This processor (80) for processing digital data comprises at least one butterfly operator (82) for the execution of a fast Fourier transform computation, this butterfly operator exhibiting a pipelined architecture for the clocked recepti...  
WO/2011/112201A1
A method for encoding bits to be stored within a crossbar memory architecture performed by a physical computing system includes designating, with the physical computing system (100), a subset of crosspoints (306) within a crossbar matrix...  
WO/2011/085934A1
The present invention relates to a data buffer memory (104) and method for storing data in a data communications network, and to a data buffer system (100) comprising such a data buffer memory. The data buffer memory comprising a data se...  
WO/2011/075076A1
A method is disclosed to convert digital data using a memory card operatively engaged with an apparatus such as a digital camera having control buttons but that does not have a keyboard or keypad. The memory card comprises a central proc...  
WO/2011/071273A2
An SRAM based address generator is provided, which can perform a TCAM function that returns an address of data when the data is input. The address generator includes n bit position tables receiving n input sub-words each of which is comp...  
WO/2011/071273A3
An SRAM based address generator is provided, which can perform a TCAM function that returns an address of data when the data is input. The address generator includes n bit position tables receiving n input sub-words each of which is comp...  
WO/2011/058659A1
A FIFO buffer (1) comprises a packet storage buffer (10), a bank switch (17), a packet write control circuit (15), and a packet write start bank holding FIFO queue (19). The packet storage buffer (10) is capable of writing and reading da...  

Matches 51 - 100 out of 9,267