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Patent Searching and Data


Matches 201 - 250 out of 6,162

Document Document Title
WO/2005/039122
The invention relates to a method and equipment for controlling the congestion management and transmission-link-capacity scheduling in packet-switched telecommunications, in such a way that 1) it is possible to define what share of the c...  
WO/2005/029342
A method of reconciling a first data structure with a second data structure that is a subsequently modified version of the first data structure. Initially, each node in the first data structure for which a change has been made to a corre...  
WO/2005/024624
A circuit is proposed which has a memory to which input data can be written at different write addresses with a first clock rate and from which output data can be read at different read addresses with a second clock rate. The memory can ...  
WO/2005/024542
The invention relates to a digital signal processing device comprising: input storage means (3; 5); a computational device (4) that is connected to said means, defines a data path (9) and contains at least one arithmetic unit (6) in addi...  
WO/2005/020062
There is described a dynamic memory buffer (30, 210) for buffering between one or more software applications (40) executing on computing means and one or more data generating and/or receiving devices (20) in communication through the buf...  
WO/2005/013639
The buffer management system (100) is arranged to control in a data communication system an end to end delay (&Dgr ) of a data unit (150) from input to output. Blocks (104, 106) of data units (150, 152) are written in a buffer (102) with...  
WO/2005/008472
A method for buffering variable length data at a decoupler (110) includes receiving, at a decoupler (110), a request to queue variable length data from a producer (108), with the decoupler comprising a management header (205) and buffer ...  
WO/2005/006177
Briefly, a re-timing buffer system that may insert or remove dummy data during frequency translation.  
WO/2005/006195
A system (10) for selectively affecting data flow to and/or from a memory device (16). The system (10) includes a first mechanism (24, 26) for intercepting data bound for the memory device (16) or originating from the memory device (16)....  
WO/2005/003955
FIFO memory devices are configured to support a pair of hybrid operating modes that enable the FIFO memory device to be depth-expandable with other FIFO memory devices in a collective standard mode of operation. The pair of hybrid operat...  
WO/2005/003956
The present invention relates to a memory device comprising a memory (EM) having at least two predetermined register memory sections addressable by respective address ranges AS1-ASz) and at least one access port (P1-PZ) for providing acc...  
WO/2004/114166
Embodiments of the invention include a system for an integrated circuit development. Elements of the development system include hardware and software objects. These objects can be instanced, ordered, parameterized, and connected in a sof...  
WO/2004/109523
An apparatus (100) for enhancing the speed of a synchronous bus includes a two register based FIFO with software control bits and a second clock signal. According to the invention, the second clock signal rd&lowbar clk (103) is supplied ...  
WO/2004/107198
Described is a system and method for applying transforms to multi-part files (202). A request is received to access a stream within a multi-part file. Upon receipt of the request, a list of transforms associated with the stream is identi...  
WO/2004/102555
A method is described for setting a disc speed in a disc drive apparatus (3)which is in data transfer communication (7) with a host system (2), wherein data transfer between carrier and drive apparatus takes place with a carrier/drive tr...  
WO/2004/095460
The amount of jitter incurred when reading data written into a FIFO (12) can be reduced by clocking the FIFO with Read Clock pulses at a frequency x fn where x is a whole integer and fn is the frequency at which the memory is clocked to ...  
WO/2004/095460
The amount of jitter incurred when reading data written into a FIFO (12) can be reduced by clocking the FIFO with Read Clock pulses at a frequency x fn where x is a whole integer and fn is the frequency at which the memory is clocked to ...  
WO/2004/092945
A processing circuit executes a data producing process and a data consuming process. The data producing process produces a stream of data, the data consuming process consumes the stream of data concurrently with production of the stream....  
WO/2004/088486
A lookup table device adapted to convert a digital input signal into a predetermined digital output signal corresponding to the digital input signal. This device includes a separator information storage unit 10 in which separator informa...  
WO/2004/061644
An access control method achieves enhanced security and accuracy compared with other systems through recognition of one or more distorted biometrics. The method includes outputting a distorted biometric print from a surface acoustic wave...  
WO/2004/059471
A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first tr...  
WO/2004/053707
A method for transparently presenting different size operands to be processed is provided. The method initiates with providing a first operand having a first bit-width (250). Then, a bit width of a second operand associated with a proces...  
WO/2004/053680
A buffer management system (100) partitions a total memory space (200) into a programmable number of substantially uniform-size buffers (220-223). An application communicates the desired number of buffers to the buffer management system ...  
WO/2004/051492
A storage device for compressing the same input value by using an input processing section, a data storage device, a FIFO memory, and an output processing section. The input processing section checks, for the input value, data stored in ...  
WO/2004/044731
A method and device is provided for performing rotate operations on operands having a size of 2N bits, alternatively, for performing rotate operations on two operands each having a size of N bits to the left, whereby N is an integer. The...  
WO/2004/042591
A processing system comprises a detection unit which detects repetitions of periods of access address patterns output from at least one of a plurality of processing units. The interface switches selectable connections between the data in...  
WO/2004/042552
A system and method for declarative markup that allows temporal manipulation of media assets. The media assets can be audio media, video media, animations, audio-visual media, images or events. Using the, present invention a media sequen...  
WO/2004/029793
A method and system for performing many different types if algorithms utilizes a single mathematical engine (30) such that the mathematical engine is capable of utilizing the same multipliers for all of the algorithms. The mathematical e...  
WO/2004/027596
System for decompressing a program word that is subsequently delivered to a processor for execution. Program word fields are compressed based on regularities between operations and operands. The resulting microcode, is stored in program ...  
WO/2004/021113
A method and apparatus for achieving a non-disruptive code load that includes staging the new version of executable code, stacking the hardware events during code copy and code switch over, copying the code into the runtime area, restart...  
WO/2004/019202
A data retiming arrangement applies data to be retimed to a delay line. The data is applied concurrently with a data clock applied to a clock multiplexer and to a data counter, and a second clock applied to the clock multiplexer. The cou...  
WO/2004/001574
Methods and apparatuses for scheduling commands are described. According to various embodiments of the invention ,delay information (108, 112), is issued with an associated command (101, 103). The delay information (201, 206) directs the...  
WO/2003/107172
A FIFO-register (10) according to the invention comprises a sequence of register cells (10.1,...,10.m), which register cells have a data section (40) and a status section (30). Data (Din) provided at an input (20) is shifted via the data...  
WO/2003/103766
A system for writing data efficiently between a fast clock domain and a slow clock domain. In one embodiment, a processor that performs firmware routines is clocked by a fast clock that is turned on when a prescribed event occurs to oper...  
WO/2003/104968
The invention is based on the idea to maintain two counters for an input or output port of a FIFO. A device for writing data elements from a coprocessor into a FIFO memory is provided. Said device is embedded in a multiprocessing environ...  
WO/2003/101024
A method and apparatus for generating and using symbol messages, which may include trademarks, registered trademarks, service marks, and other well-known symbols. Additionally, a method is provided for generating a symbol or logo alphabe...  
WO/2003/100985
A method of packing a variable number of bits from an input bit stream into an output bit stream, comprising the steps of: defining a maximum number n of bits which are to be packed into the output bit stream within a clock cycle, provid...  
WO/2003/101024
A method and apparatus for generating and using symbol messages, which may include trademarks, registered trademarks, service marks, and other well-known symbols. Additionally, a method is provided for generating a symbol or logo alphabe...  
WO/2003/098446
Appropriate contents are distributed in accordance with the performance specification of a client device without preparing contents in a plurality of formats. When receiving a request for data list from a client, a server establishes, as...  
WO/2003/090064
Bit-rate scalable compression for storing A/V information in a pause buffer of a digital video recorder, providing a viewer of a live program to take a delayed decision about whether or not to record the program while still viewing the '...  
WO/2003/090063
This invention relates to a method and system for changing an output rate of information for a buffer (3) with a constant first output rate (R1) which receives output data from a data source (2a), where the method step comprises; halting...  
WO/2003/083642
The data processing system and method performs a mathematical operation on multi bit binary integer numbers using floating point arithmetic. The binary integer numbers are divided into corresponding segments and processed to determine at...  
WO/2003/077504
Disclosed is an interface (10, 40) between a master device (30) and a slave device (20). The interface includes a bit serial bidirectional signal line (10A) for conveying commands and associated data from the master device to the slave d...  
WO/2003/073296
A queuing system uses a common buffer for receiving input data from multiple-inputs, by allocating memory-elements in the common buffer to each input-stream, as the streams provide their input data. To allow for an independently controll...  
WO/2003/073290
The present invention allows for an increase in programming parallelism in a non-volatile memory system without incurring additional data transfer latency. Data is transferred from a controller(101) to a first memory chip (131-0) and a p...  
WO/2003/060692
Disclosed is a shifting device for shifting the first place of a data word consisting of a plurality of places to a second place so as to obtain a shifted data word. The first place is coded by means of a first coding parameter while the...  
WO/2003/058425
A system and method for determining the resources available or used in a remote device is disclosed. The system can be used to determine whether the remote device (106) is using expected resources as originally configured or to determine...  
WO/2003/048924
A Galois field linear transformer (28) includes a matrix responsive to a number of input bits in one or more bit streams and having a plurality of outputs providing the Galois field linear transformation of those bits; the matrix includi...  
WO/2003/047113
A hybrid serial&sol parallel bus interface method for a user equipment (UE) has a data block demultiplexing device (40). The data block demultiplexing device (40) has an input configured to receive a data block and demultiplexes the data...  
WO/2003/046757
Systems and methods for processing documents are disclosed. Documents received at a data server are transcoded using locally stored or generated code books. Code books for transcoded documents received at a wireless mobile communication ...  

Matches 201 - 250 out of 6,162