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Patent Searching and Data


Matches 201 - 250 out of 9,221

Document Document Title
WO/2006/086379A3
A RAID controller is disclosed. The controller controls at least one redundant array of physical disks (702), receives I/O requests from the array from host computers, and responsively generates disk commands for each of the disks (706)....  
WO/2006/085273A1
A data register (300) for use in a computer comprises a clock terminal (310) configured to receive a clock signal. A plurality of registers (320) are configured to selectively store data. A data input circuit (330) is coupled to the regi...  
WO2005122689A3
The present invention is directed to a method and system for securing a device (e.g. a security token). The method comprising the steps of: providing physical actuation mechanism (e.g. a switch) to the device; disabling some function(s) ...  
WO/2006/069438A1
A method of accommodating legacy devices in which application memory is not able to operate fast enough to reliably receive data from a relay or other external device is disclosed. An application queue memory space is provided, either as...  
WO/2006/071817A3
For attached disk drive operations such a file copy and move, as well as more elaborate processes such as searching, virus-scanning and volume merge, a novel intelligent storage engine concept is disclosed. In one embodiment, a storage e...  
WO/2006/063395A1
A method for feature reduction in a training set for a learning machine such as a Support Vector Machine (SVM). In one embodiment the method includes a step (35) of receiving input training data vectors xi of a training set. The input tr...  
WO/2006/064962A1
Methods and apparatus provide for transferring data to and from one or more processors of a multi-processor system over a first bus at a first frequency; transferring data to and from one or more interface circuits over a second bus at a...  
WO/2006/062142A1
It is possible to increase the compression ratio of the encoding method using a dictionary such as LZ77, LZ78, LZW for sample strings of the audio signal and video signal. Each sample is aligned at the MSB side (73), divided from the MSB...  
WO/2006/060648A3
An interrupt notification block stored in host memory (132) is disclosed that contains an image of the interrupts condition contents that may be stored in a host attention register (120) in a host interface port (104). The interrupt noti...  
WO/2006/055282A2
A multiprocessor system (206) having a plurality of processors (304-306), each processor capable of processing at least one queue (404A-404N) of at least one service application, and at least one task (402A-402N) comprising at least one ...  
WO2005091131A3
The invention relates to a computer system for electronic data processing, comprising a first data processing unit, a second data processing unit and a data transmission/memory device which can transmit sets of data from the data process...  
WO/2006/053321A3
Systems and methods for controlling clock rates of circuits are provided. The systems and methods, collectively referred to as clock rate control, generate a clock rate control parameter from data of one or more fuses. The clock rate con...  
WO/2006/052933A3
Circuits, methods, and apparatus that adaptively control 1T and 2T timing for a memory controller interface. An embodiment of the present invention provides a first memory interface as well as an additional memory interface, each having ...  
WO/2006/043274A3
Web content based on markup language technology is delivered to a client device running a browser or similar application through a markup language file manipulator. Files requested by a client device are processed through the markup lang...  
WO/2006/043274A2
Web content based on markup language technology is delivered to a client device running a browser or similar application through a markup language file manipulator. Files requested by a client device are processed through the markup lang...  
WO/2006/041165A1
There are provided a method for encoding signals by separating them by using a common multiplier so as to improve the compression efficiency of an audio signal and a method for obtaining a multiplier common to a numeric set including an ...  
WO/2006/037677A1
The invention relates to a method for reading out sensor data from an intermediate memory (110), written by at least one sensor (10) in the intermediate memory at a data rate (Tpas). According to the invention, a sampling rate (Tsg) is s...  
WO/2006/024781A1
The invention concerns a method for managing a buffer memory used for a computer programme using a MMU memory management unit. The invention is characterized in that it comprises a step which consists in detecting an access exceeding the...  
WO/2006/023877A3
A first file is received in a first format. The first format is determined. A converter is selected based on the first format. Using the converter, the first file is translated to at least one second file. The second file has a second fo...  
WO/2006/007801A1
The present invention provides a First-in-first-out memory to improve the empty-full indicator generating logic unit of the existing FIFO such that the First-in-first-out memory can generate a state adjusting signal which is output direc...  
WO2005066827A3
A number of symbols are received in a first integrated circuit (IC) device, where these symbols have been transmitted by a second IC device and are received over a serial point to point link. These symbols include a non-data sequence tha...  
WO/2006/004165A1
A mask which is used for divided recording that completes an image with a plurality of scanning operations by using a plurality of different colors of ink, and which can prevent the occurrence of grains in the middle of recording and red...  
WO/2005/122689A2
The present invention is directed to a method and system for securing a device (e.g. a security token). The method comprising the steps of: providing physical actuation mechanism (e.g. a switch) to the device; disabling some function(s) ...  
WO2004114166A3
Embodiments of the invention include a system for an integrated circuit development. Elements of the development system include hardware and software objects. These objects can be instanced, ordered, parameterized, and connected in a sof...  
WO/2005/116815A1
Methods and apparatus provide for efficient message passing communication between subsystems. In one aspect of the present invention FIFOs (202, 203, 204, 212, 216) are disposed between the subsystems (102, 104, 110) to buffer the messag...  
WO/2005/114433A3
An integrated circuit capable of supporting a plurality of host processor families includes a host processor belonging to a first processor family (Fig. 1, 148); a reconfigurable processor core (Fig. 1, 150) coupled to the host processor...  
WO/2005/112269A1
Audio information is encoded, sample by sample, by creating a table of encoded audio sample values in which redundant ones of the encoded audio sample values share common table entries. The encoding method may include comparing a current...  
WO/2005/111813A3
A storage server (120) uses a semantic processor (100) to parse and respond to client requests. A direct execution parser (140) in the semantic processor parses an input stream, comprising client storage server requests, according to a d...  
WO2003103766A3
A system for writing data efficiently between a fast clock domain and a slow clock domain. In one embodiment, a processor that performs firmware routines is clocked by a fast clock that is turned on when a prescribed event occurs to oper...  
WO/2005/088889A1
A circuit is described comprising a first (10) and a second circuit module (20) and a synchronization module (30). The first and the second module are mutually a¬≠synchronous, and are coupled by the synchronization module. The synchroniz...  
WO/2005/085990A1
Systems and techniques are disclosed relating to shifting a plurality of input data bits to the left or right by a number of bit positions as a function of a binary value of a plurality of shift control bits. A first shifter element may ...  
WO/2005/078572A1
A FIFO memory device (300) comprises a storage device (321) which is a non-volatile FIFO comprising a plurality of non-volatile storage elements or latches. The FIFO memory device (300) also comprises an input stage (315) which is a vola...  
WO/2005/076123A1
A differential clock-pulse compensation between the clock-pulse system (23) of a digital line-connected data interface and the asynchronous clock-pulse system (22) of a digital wireless data interface is carried out, whereby a variable (...  
WO2005003955A3
FIFO memory devices are configured to support a pair of hybrid operating modes that enable the FIFO memory device to be depth-expandable with other FIFO memory devices in a collective standard mode of operation. The pair of hybrid operat...  
WO/2005/069121A1
An asynchronously operated FIFO pipe-line (10a-d) comprises a plurality of handshake chains functionally in parallel. Successive data items are each passed by selecting a chain dependent on a value of the data item. The FIFO pipelines (1...  
WO/2005/066827A2
A number of symbols are received in a first integrated circuit (IC) device, where these symbols have been transmitted by a second IC device and are received over a serial point to point link. These symbols include a non-data sequence tha...  
WO/2005/057861A1
A transfer device (20) includes: means for generating a bit string (13) in which a bit string (14q) is arranged in a predetermined order by performing only logic operation without subjecting the bit string (14q) received from an I/O devi...  
WO2004059471A3
A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first tr...  
WO2005024542A3
The invention relates to a digital signal processing device comprising: input storage means (3; 5); a computational device (4) that is connected to said means, defines a data path (9) and contains at least one arithmetic unit (6) in addi...  
WO/2005/039122A1
The invention relates to a method and equipment for controlling the congestion management and transmission-link-capacity scheduling in packet-switched telecommunications, in such a way that 1) it is possible to define what share of the c...  
WO/2005/039123A1
The invention relates to a method and equipment for performing aggregate-portion-specific flow shaping in packet-switched telecommunications, in such a way that the traffic flows (V1-VL) arriving in the system can be arbitrarily bundled ...  
WO2002071248A3
According to the invention, memories are associated with a reconfigurable component (VPU) at the inputs and outputs thereof, so that the internal data processing and particularly the reconfiguration cycles can be decoupled from the exter...  
WO2005013639A3
The buffer management system (100) is arranged to control in a data communication system an end to end delay (Delta) of a data unit (150) from input to output. Blocks (104, 106) of data units (150, 152) are written in a buffer (102) with...  
WO/2005/029342A1
A method of reconciling a first data structure with a second data structure that is a subsequently modified version of the first data structure. Initially, each node in the first data structure for which a change has been made to a corre...  
WO2004109523A3
An apparatus (100) for enhancing the speed of a synchronous bus includes a two register based FIFO with software control bits and a second clock signal. According to the invention, the second clock signal rd_clk (103) is supplied by the ...  
WO/2005/024624A1
A circuit is proposed which has a memory to which input data can be written at different write addresses with a first clock rate and from which output data can be read at different read addresses with a second clock rate. The memory can ...  
WO/2005/024542A2
The invention relates to a digital signal processing device comprising: input storage means (3; 5); a computational device (4) that is connected to said means, defines a data path (9) and contains at least one arithmetic unit (6) in addi...  
WO2005006195A3
A system (10) for selectively affecting data flow to and/or from a memory device (16). The system (10) includes a first mechanism (24, 26) for intercepting data bound for the memory device (16) or originating from the memory device (16)....  
WO2004034401A3
Described are dynamic memory systems that perform overlapping refresh and data-access (read or write) transactions that minimize the impact of the refresh transaction on memory performance. The memory systems support independent and simu...  
WO/2005/020062A1
There is described a dynamic memory buffer (30, 210) for buffering between one or more software applications (40) executing on computing means and one or more data generating and/or receiving devices (20) in communication through the buf...  

Matches 201 - 250 out of 9,221