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Patent Searching and Data


Matches 301 - 350 out of 9,144

Document Document Title
WO/2003/060692A2
Disclosed is a shifting device for shifting the first place of a data word consisting of a plurality of places to a second place so as to obtain a shifted data word. The first place is coded by means of a first coding parameter while the...  
WO/2003/058425A1
A system and method for determining the resources available or used in a remote device is disclosed. The system can be used to determine whether the remote device (106) is using expected resources as originally configured or to determine...  
WO/2003/048924A1
A Galois field linear transformer (28) includes a matrix responsive to a number of input bits in one or more bit streams and having a plurality of outputs providing the Galois field linear transformation of those bits; the matrix includi...  
WO/2003/047113A1
A hybrid serial&sol parallel bus interface method for a user equipment (UE) has a data block demultiplexing device (40). The data block demultiplexing device (40) has an input configured to receive a data block and demultiplexes the data...  
WO/2003/046757A2
Systems and methods for processing documents are disclosed. Documents received at a data server are transcoded using locally stored or generated code books. Code books for transcoded documents received at a wireless mobile communication ...  
WO/2003/044652A2
A buffer, having a first buffer input, a second buffer input, and a buffer output. The buffer is configured to store a plurality of data entries. The buffer includes: a first memory, the first memory having an input and an output. The in...  
WO/2003/042811A1
The invention relates to a method and a device for reading/writing data elements from/into a shared FIFO buffer, wherein the signalling that a data element or a storage space for a data element is available in a FIFO buffer, i.e. perform...  
WO/2003/042810A1
A V-operation not performed atomically for each data element or storage space that becomes available in a FIFO or a P-operation is not performed atomically for each request for a data element or a storage space in the FIFO but rather one...  
WO2002078227A3
In parallel networks that include a transmission media and at least one I/O processor connected to the transmission media by a core, a buffering device is provided that compensates for different latencies from all physical lanes in data ...  
WO/2003/039061A2
A method and arrangement of passing data from a source clock domain to a non-synchronous receive clock domain are provided. A first processing circuit, located in the source clock domain, links write-address information with the data, an...  
WO2002031664A3
A system, method and article of manufacture are provided for data transfer across different clock domains. A request for transferring data from a sending (transmitting) process in a first domain to a receiving process in a second domain ...  
WO/2003/036475A1
Described herein is a technology facilitating the operation of non-native program modules within a native computing platform. This technology provides a mechanism for aligning-as necessary-parameters of data structures so that program mo...  
WO2001082053A3
A FIFO design interfaces a sender subsystem and a receiver subsystem working at different speeds. Global control signals relating to whether the FIFO is nearly full or nearly empty are synchronized to the sender subsystem clock and the r...  
WO/2003/032157A1
A compiler capable of facilitating calculation description in a source program and simplifying the source program description so as to reduce generation of bugs in calculation according to the block floating method by software. When a so...  
WO/2003/032147A2
So-called LCH packets are defined in the Hiperlan Type 2 System for wire-free transmission of video and audio data streams. These LCH packets have a length of 54 data bytes. Furthermore, the Hiperlan/2 Standard provides for so-called ARQ...  
WO/2003/029953A2
The invention relates to a method which is characterised in that the data is stored or transferred together with an information message on the basis of which it can be determined in which order, at which time, and/or during which time sp...  
WO2002071249A9
The invention relates to procedures and methods for administering and transferring data within multi-dimensional systems consisting of transmitters and receivers. The division of a data stream into several independent branches and the su...  
WO/2003/023600A2
An apparatus and method for extracting and loading data to/from a buffer are described. The method includes the selection of data from a data buffer in response to execution of a data access instruction. The data buffer includes a plural...  
WO2003007517A8
This invention relates to the field of packet communications. More particularly, this invention is a method and system for using a jitter absorption buffer to absorb propagation delay variation in packet arrival time. The invention uses ...  
WO/2003/019350A1
A hierarchical memory access control distinguishes between blocks of data that are known to be sequentially accessed, and the contents of each block, which may or may not be sequentially accessed. If the contents of a block are provided ...  
WO/2003/019351A2
First-in first-out (FIFO) memory devices include a plurality of memory devices that are configured to support any combination of dual data rate (DDR) or single data rate (SDR) write modes that operate in-sync with a write clock signal (W...  
WO/2003/017541A1
A variable size FIFO memory (13) is provided by the use of head (17) and tail (16) FIFO memories operating at a very high data rate and then an off chip buffer memory (18), for example, of a dynamic RAM type, which temporarily stores dat...  
WO2002097604A3
A system for providing a floating point sum comprises an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first fl...  
WO/2003/012648A1
A data formatter (100) includes a shift register (112) and a pointer manager (120). The shift register (112) receives data from a providing RAM (108) and shifts that data in response to reading data from the providing RAM (108) and writi...  
WO/2003/007517A1
This invention relates to the field of packet communications. More particularly, this invention is a method and system for using a jitter absorption buffer to absorb propagation delay variation in packet arrival time. The invention uses ...  
WO/2003/007614A2
The invention regards a method for compressing a hierarchical tree describing a multimedia signal, said tree comprising nodes and leaves, which can be associated to contents of at least two distinct types.According to the invention, said...  
WO/2003/001360A2
A first-in, first-out (FIFO) memory system (10) includes first and second FIFOs (A and B). First and second multiplexers (12, 14) each have two input terminals for receiving data. An output terminal of the first multiplexer (12) is coupl...  
WO/2002/101938A2
According to the invention, in order to carry out an equidistant data transfer between clock pulse domains having different clock pulse rates, a combination of a counter (1) and a finite state machine (2) is used. Said counter (1) contin...  
WO/2002/099554A2
The invention relates to a power controlled electronic circuit comprising a controller which is used to process a processor task and a power determination device which determines the power available for the controller. A control device o...  
WO/2002/099621A1
A first in, first out (FIFO) circular buffer enables high speed streaming data transfer between integrated circuit devices by performing more than one data element transfer unidirectionally by having a plurality of ports to address a mem...  
WO/2002/097604A2
A system for providing a floating point sum comprises an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first fl...  
WO/2002/097607A1
A floating point unit generates results in which status information generated for an operation is encoded within the resulting operand, instead of requiring a separate floating point status register for the status information. In one emb...  
WO/2002/097620A2
The present invention provides safe and secure application distribution and execution by providing systems and methods that test an application to ensure that it satisfies predetermined criteria associated with the environment in which i...  
WO/2002/097606A1
A system for providing a floating point product comprises an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the firs...  
WO2002063776A3
The invention concerns a method for compressing a structured document comprising nested information elements, the document being associated with at least a tree-like structure schema (1) defining a structure of the document and comprisin...  
WO/2002/093358A1
Distributed compression of a data file can comprise a master server module for breaking the data file into data blocks and transmitting the data blocks to worker server modules. A first worker server module can compress a first data bloc...  
WO/2002/093392A1
A data processor (1) comprises a central processing unit (2), a memory (5) accessible by the central processing unit, input/output circuits (12, 13), and a FIFO control circuit (6) for operating the memory as a FIFO buffer for the input/...  
WO/2002/091188A1
An apparatus for gathering queue performance data includes an event conditioning logic unit (220) that receives a queue enter signal (211), a queue exit signal (213), and a queue not empty signal (215) from a queue (210). This apparatus ...  
WO/2002/088928A2
The invention relates to an improved method and to a corresponding device for adapting the data rate of a data stream while using a first in, first out (FIFO) memory (1) into which data packets of the data stream with a first data rate a...  
WO2002071196A8
The invention relates to a data processing unit (VPU) comprising logic cells (PAEs) clocked in operational fields in different configuration states and a clocking input means for setting the clocking of the logic cell. According to the i...  
WO2002003206A3
An architecture and techniques of the present invention combine multiple queues into a single multientity queue that functions in conjunction with a free queue embodied within the multientity queue. This multienity queue enables a device...  
WO/2002/082348A2
Method and system for real time monitoring of activities within a health care tracking environment generates a substantially complete and accurate electronic patient care record, and makes information on evaluation of patient care, inclu...  
WO/2002/079971A1
Disclosed is a programmable buffer circuit (16) for interfacing a CPU (12) to a plurality of channel interfaces (814). The buffer circuit includes a dual port memory (18) having a first port coupled to a CPU data bus and a second port co...  
WO2002027464A3
A novel FIFO data structure in the form of a multi-dimensional FIFO. For a rectangular multi-dimensional FIFO, data items are received at an input of an N-row-by-M-column FIFO array of cells and transferred to an output, via a predetermi...  
WO2002050655A3
A device for controlling a stream of data packets, comprising: a buffer (2) means (4) adapted to monitor a fill level of said buffer (2), means (5) to detect a fill level condition of said buffer (2), in which incoming data has to be dro...  
WO2001037076A3
A system for detecting underflow and overflow errors arising within a ring buffer. When the system receives a data word to be transferred through the ring buffer, the system generates a flow indicator value to be stored with the data wor...  
WO/2002/077829A2
A communication system includes a core for providing speed reduction in communications between a transmission media and a processor having an upper link layer in a parallel-serial architecture. The core includes a lower logic layer, seri...  
WO/2002/078227A2
In parallel networks that include a transmission media and at least one I/O processor connected to the transmission media by a core, a buffering device is provided that compensates for different latencies from all physical lanes in data ...  
WO/2002/071249A2
The invention relates to procedures and methods for administering and transferring data within multi-dimensional systems consisting of transmitters and receivers. The division of a data stream into several independent branches and the su...  
WO/2002/071196A2
The invention relates to a data processing unit (VPU) comprising logic cells (PAEs) clocked in operational fields in different configuration states and a clocking input means for setting the clocking of the logic cell. According to the i...  

Matches 301 - 350 out of 9,144