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Patent Searching and Data


Matches 301 - 350 out of 9,263

Document Document Title
WO/2004/029793A1
A method and system for performing many different types if algorithms utilizes a single mathematical engine (30) such that the mathematical engine is capable of utilizing the same multipliers for all of the algorithms. The mathematical e...  
WO2004021113A3
A method and apparatus for achieving a non-disruptive code load that includes staging the new version of executable code, stacking the hardware events during code copy and code switch over, copying the code into the runtime area, restart...  
WO/2004/027596A1
System for decompressing a program word that is subsequently delivered to a processor for execution. Program word fields are compressed based on regularities between operations and operands. The resulting microcode, is stored in program ...  
WO2003046757A3
Systems and methods for processing documents are disclosed. Documents received at a data server are transcoded using locally stored or generated code books. Code books for transcoded documents received at a wireless mobile communication ...  
WO2003067469A3
A document transformation system (1) comprises a layout server (2) which dynamically generates output documents for delivery to a user device. The layout server (2) selects a layout template (5) according to user device and delivery chan...  
WO/2004/021113A2
A method and apparatus for achieving a non-disruptive code load that includes staging the new version of executable code, stacking the hardware events during code copy and code switch over, copying the code into the runtime area, restart...  
WO/2004/019202A2
A data retiming arrangement applies data to be retimed to a delay line. The data is applied concurrently with a data clock applied to a clock multiplexer and to a data counter, and a second clock applied to the clock multiplexer. The cou...  
WO2002017494A3
A gray-code counter system (AP1) for a RAM-based FIFO comprises a read pointer (10), a write pointer (20), and a detector (30). The read pointer includes a gray-code decoder (11), a binary incrementer (12), a gray-code encoder (13), and ...  
WO2002099554A3
The invention relates to a power controlled electronic circuit comprising a controller which is used to process a processor task and a power determination device which determines the power available for the controller. A control device o...  
WO2003019351A3
First-in first-out (FIFO) memory devices include a plurality of memory devices that are configured to support any combination of dual data rate (DDR) or single data rate (SDR) write modes that operate in-sync with a write clock signal (W...  
WO2003060692A3
Disclosed is a shifting device for shifting the first place of a data word consisting of a plurality of places to a second place so as to obtain a shifted data word. The first place is coded by means of a first coding parameter while the...  
WO2003032147A3
So-called LCH packets are defined in the Hiperlan Type 2 System for wire-free transmission of video and audio data streams. These LCH packets have a length of 54 data bytes. Furthermore, the Hiperlan/2 Standard provides for so-called ARQ...  
WO2003073296A3
A queuing system uses a common buffer for receiving input data from multiple-inputs, by allocating memory-elements in the common buffer to each input-stream, as the streams provide their input data. To allow for an independently controll...  
WO2002071248A8
According to the invention, memories are associated with a reconfigurable component (VPU) at the inputs and outputs thereof, so that the internal data processing and particularly the reconfiguration cycles can be decoupled from the exter...  
WO/2004/001574A1
Methods and apparatuses for scheduling commands are described. According to various embodiments of the invention ,delay information (108, 112), is issued with an associated command (101, 103). The delay information (201, 206) directs the...  
WO2003083642A3
The data processing system and method performs a mathematical operation on multi bit binary integer numbers using floating point arithmetic. The binary integer numbers are divided into corresponding segments and processed to determine at...  
WO/2003/107172A2
A FIFO-register (10) according to the invention comprises a sequence of register cells (10.1,...,10.m), which register cells have a data section (40) and a status section (30). Data (Din) provided at an input (20) is shifted via the data...  
WO/2003/104968A2
The invention is based on the idea to maintain two counters for an input or output port of a FIFO. A device for writing data elements from a coprocessor into a FIFO memory is provided. Said device is embedded in a multiprocessing environ...  
WO2003077504A3
Disclosed is an interface (10, 40) between a master device (30) and a slave device (20). The interface includes a bit serial bidirectional signal line (10A) for conveying commands and associated data from the master device to the slave d...  
WO/2003/103766A2
A system for writing data efficiently between a fast clock domain and a slow clock domain. In one embodiment, a processor that performs firmware routines is clocked by a fast clock that is turned on when a prescribed event occurs to oper...  
WO/2003/100985A1
A method of packing a variable number of bits from an input bit stream into an output bit stream, comprising the steps of: defining a maximum number n of bits which are to be packed into the output bit stream within a clock cycle, provid...  
WO/2003/101024A3
A method and apparatus for generating and using symbol messages, which may include trademarks, registered trademarks, service marks, and other well-known symbols. Additionally, a method is provided for generating a symbol or logo alphabe...  
WO/2003/101024A2
A method and apparatus for generating and using symbol messages, which may include trademarks, registered trademarks, service marks, and other well-known symbols. Additionally, a method is provided for generating a symbol or logo alphabe...  
WO2002071196A3
The invention relates to a data processing unit (VPU) comprising logic cells (PAEs) clocked in operational fields in different configuration states and a clocking input means for setting the clocking of the logic cell. According to the i...  
WO2002088928A3
The invention relates to an improved method and to a corresponding device for adapting the data rate of a data stream while using a first in, first out (FIFO) memory (1) into which data packets of the data stream with a first data rate a...  
WO/2003/098446A1
Appropriate contents are distributed in accordance with the performance specification of a client device without preparing contents in a plurality of formats. When receiving a request for data list from a client, a server establishes, as...  
WO/2003/090063A2
This invention relates to a method and system for changing an output rate of information for a buffer (3) with a constant first output rate (R1) which receives output data from a data source (2a), where the method step comprises; halting...  
WO2002071249A8
The invention relates to procedures and methods for administering and transferring data within multi-dimensional systems consisting of transmitters and receivers. The division of a data stream into several independent branches and the su...  
WO/2003/090064A1
Bit-rate scalable compression for storing A/V information in a pause buffer of a digital video recorder, providing a viewer of a live program to take a delayed decision about whether or not to record the program while still viewing the '...  
WO2003039061A3
A method and arrangement of passing data from a source clock domain to a non-synchronous receive clock domain are provided. A first processing circuit, located in the source clock domain, links write-address information with the data, an...  
WO2002082348A3
Method and system for real time monitoring of activities within a health care tracking environment generates a substantially complete and accurate electronic patient care record, and makes information on evaluation of patient care, inclu...  
WO2003007614A3
The invention regards a method for compressing a hierarchical tree describing a multimedia signal, said tree comprising nodes and leaves, which can be associated to contents of at least two distinct types.According to the invention, said...  
WO2001095089A3
A FIFO design interfaces a sender subsystem and a receiver subsystem operating on different time domains. The sender subsystem and the receiver subsystem may be synchronous or asynchronous. The FIFO circuit includes a put interface confi...  
WO2003001360A3
A first-in, first-out (FIFO) memory system (10) includes first and second FIFOs (A and B). First and second multiplexers (12, 14) each have two input terminals for receiving data. An output terminal of the first multiplexer (12) is coupl...  
WO2002023476A3
A signal processing apparatus for processing signals like video, audio or graphics contains signal processor units that produce and consume a stream of data items relating to samples along at least one dimension of an at least one dimens...  
WO/2003/083642A2
The data processing system and method performs a mathematical operation on multi bit binary integer numbers using floating point arithmetic. The binary integer numbers are divided into corresponding segments and processed to determine at...  
WO2002101938A3
According to the invention, in order to carry out an equidistant data transfer between clock pulse domains having different clock pulse rates, a combination of a counter (1) and a finite state machine (2) is used. Said counter (1) contin...  
WO/2003/077504A2
Disclosed is an interface (10, 40) between a master device (30) and a slave device (20). The interface includes a bit serial bidirectional signal line (10A) for conveying commands and associated data from the master device to the slave d...  
WO/2003/073296A2
A queuing system uses a common buffer for receiving input data from multiple-inputs, by allocating memory-elements in the common buffer to each input-stream, as the streams provide their input data. To allow for an independently controll...  
WO/2003/073290A1
The present invention allows for an increase in programming parallelism in a non-volatile memory system without incurring additional data transfer latency. Data is transferred from a controller(101) to a first memory chip (131-0) and a p...  
WO2002021285A3
A circuit arrangement, apparatus and method control the transfer of data into an intermediate buffer (28) associated with a split transaction interconnect or bus (16a) by conditioning such transfer on both the amount of free space in the...  
WO/2003/067469A2
A document transformation system (1) comprises a layout server (2) which dynamically generates output documents for delivery to a user device. The layout server (2) selects a layout template (5) according to user device and delivery chan...  
WO2002050656A3
Techniques for indicating partial fullness levels of a FIFO comprising a plurality of stages using a partial fullness detector, such as a m-out-of-n detector. According to an embodiment, the m-out-of-n detector is coupled to "n" stages o...  
WO2002077829A3
A communication system includes a core for providing speed reduction in communications between a transmission media and a processor having an upper link layer in a parallel-serial architecture. The core includes a lower logic layer, seri...  
WO/2003/060692A2
Disclosed is a shifting device for shifting the first place of a data word consisting of a plurality of places to a second place so as to obtain a shifted data word. The first place is coded by means of a first coding parameter while the...  
WO/2003/058425A1
A system and method for determining the resources available or used in a remote device is disclosed. The system can be used to determine whether the remote device (106) is using expected resources as originally configured or to determine...  
WO/2003/048924A1
A Galois field linear transformer (28) includes a matrix responsive to a number of input bits in one or more bit streams and having a plurality of outputs providing the Galois field linear transformation of those bits; the matrix includi...  
WO/2003/046757A2
Systems and methods for processing documents are disclosed. Documents received at a data server are transcoded using locally stored or generated code books. Code books for transcoded documents received at a wireless mobile communication ...  
WO/2003/047113A1
A hybrid serial&sol parallel bus interface method for a user equipment (UE) has a data block demultiplexing device (40). The data block demultiplexing device (40) has an input configured to receive a data block and demultiplexes the data...  
WO/2003/044652A2
A buffer, having a first buffer input, a second buffer input, and a buffer output. The buffer is configured to store a plurality of data entries. The buffer includes: a first memory, the first memory having an input and an output. The in...  

Matches 301 - 350 out of 9,263