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Patent Searching and Data


Matches 301 - 350 out of 6,156

Document Document Title
WO/2002/008917
A queuing architecture and method for scheduling disk drive access requests in a video server. The queuing architecture employs at least two access request queues (221; 222, 223) for each disk drive (120) within a disk drive (120) within...  
WO/2002/003206
An architecture and techniques of the present invention combine multiple queues into a single multientity queue that functions in conjunction with a free queue embodied within the multientity queue. This multienity queue enables a device...  
WO/2002/003612
A technique is described for providing service to multiple ports sharing common scheduling resources. According to one implementation, the scheduling technique of the present invention may be used to dynamically balance the frequency of ...  
WO/2002/003629
A improved connection shaping technique is disclosed, whereby at least one high-priority 'preemptive' service flow is initiated at a customer entity in order to limit or restrict the effective usable bandwidth on a particular line or con...  
WO/2002/003745
A technique is disclosed for scheduling data parcels from at least one client process to be output for transmission over a first communication line having an associated first bit rate. The at least one client process may include a plural...  
WO/2001/095123
The present invention relates to data representation and more paricularly to a system and method for creating a source document and presenting the source document to a user in a target format. The system selects the target DTD of the tar...  
WO/2001/095088
A system and method for creating a source document and presenting the source document to a user in a target format are described. A construction user interface area (437) is presented to enable a user to create the source document in a s...  
WO/2001/095089
A FIFO design interfaces a sender subsystem and a receiver subsystem operating on different time domains. The sender subsystem and the receiver subsystem may be synchronous or asynchronous. The FIFO circuit includes a put interface confi...  
WO/2001/093051
A data processing system and a data processing method control the feed of a clock in accordance with various processing instructions issued from an instruction issuer, and request a data transfer without finishing the data processing ins...  
WO/2001/086449
A system and method for compensating for differences between a recovered receive clock and an internal transmit clock in an elastic buffer and thereby preventing corruption of data. In one embodiment, the system comprises a circularly ac...  
WO/2001/082053
A FIFO design interfaces a sender subsystem and a receiver subsystem working at different speeds. Global control signals relating to whether the FIFO is nearly full or nearly empty are synchronized to the sender subsystem clock and the r...  
WO/2001/082081
An integrated circuit includes an address register, clocked by the clock signal corresponding to the TAP, used to address a control/status register within the integrated circuit. The address register receives a signal indicating that an ...  
WO/2001/079987
A synchronization circuit (P2P) for interfacing a first digital circuit functioning with a first clock (CLK1) and a second digital circuit functioning with a second clock (CLK2) that may be different from the first clock (CLK1) in terms ...  
WO/2001/071482
A first-in first-out buffer (FIFO) with multiple outputs. The FIFO has an input for writing data into the FIFO. The FIFO has multiple outputs for reading the data out of the FIFO. Each output is independent from the other outputs, and ca...  
WO/2001/065774
A multi-port communications system (100) is described, which includes hardware based subsystems for performing both physical medium dependent operations and transport convergence operations on a data transmission. A software based subsys...  
WO/2001/058168
A method of compressing an image frame composed of an array of pixels in the form of digital signals comprises a two stage codebook search. In the first stage the pixelated image frame and the pixelated codebook patches are transformed t...  
WO/2001/055834
A system (100) includes a first device (104) that can store and transfer data. The first device (104) is capable of transferring data at a first rate, although it may transfer data at other rates. An intermediate storage location (108) i...  
WO/2001/053943
A linked-list-based concurrent shared object implementation has been developed that provides non-blocking and linearizable access to the concurrent shared object. In an application of the underlying techniques to a deque, the linked-list...  
WO/2001/053942
An array-based concurrent shared object implementation has been developed that provides non-blocking and linearizable access to the concurrent shared object. In an application of the underlying techniques to a deque, the array-based algo...  
WO/2001/046988
The present invention comprises a method and apparatus of routing a 1 of N signal to reduce the effective signal coupling between the signal wires. The present invention comprises a wire pack (129) with a plurality of wires for routing a...  
WO/2001/046988
The present invention comprises a method and apparatus of routing a 1 of N signal to reduce the effective signal coupling between the signal wires. The present invention comprises a wire pack (129) with a plurality of wires for routing a...  
WO/2001/043287
The present invention is a method and apparatus (106) for an N-NARY logic circuit that uses N-NARY signals (A0-A3, B0-B3). The present invention includes a shared logic tree circuit (107) that evaluates one or more N-NARY input signals a...  
WO/2001/037076
A system for detecting underflow and overflow errors arising within a ring buffer. When the system receives a data word to be transferred through the ring buffer, the system generates a flow indicator value to be stored with the data wor...  
WO/2001/033716
Non-power-of-two grey-code counters (AP1, AP4, AP5, AP6), including modulos-10, 12, 14, and 22 are disclosed, along with a sequencing method they employ. Each counter includes a register (REG, 402, 502, 602) for storing an N-bit, e.g., 4...  
WO/2001/029650
A multiple time domain serial-to-parallel converter includes a combiner operable to receive a stream of serial data within a first time domain and to accumulate a portion of the serial data into a set of parallel data. A first hold regis...  
WO/2001/016757
A method is described for streaming data in Java comprising the steps of: storing audio/video data in a first addressable memory space (501); playing back the audio/video data stored in the first addressable memory space (501) when the f...  
WO/2001/009710
The invention relates to a method for writing and reading a buffer memory. Said buffer memory has an input for write data and an output for read data. The output of a first addressing device addresses a memory cell of the buffer memory t...  
WO/2001/009712
Floating-point processors (200) capable of performing multiply-add (Madd) operations and incorporating improved intermediate result handling capabilities. The floating-point processor (200) includes a multiplier unit (210, 212) coupled t...  
WO/2001/006347
The invention concerns a stack of operands (10) for optimising the location of a storage unit and a continuous monitoring of the type of operand by the installation of a storage unit (20) recording data for each operand, said data contai...  
WO/2001/004724
A partitioned shift right logic circuit (300) that is programmable and contains rounding support (310a, 310b, 320a, 330a, and 330b). The circuit of the present invention accepts 32-bit value (360) and a shift amount (350) and then perfor...  
WO/2000/079378
A first-in first-out (FIFO) storage device for storing data including continuous identical values, which is reduced in a required circuit scale and increased in a reading operation speed, and which comprises a memory region (13) provided...  
WO/2000/077786
When data are transferred from a host CPU (14) to a sound processor (24) which reproduces music sounds on a real-time basis, the burden on the host CPU (14) is greatly reduced. Upon transfer of music sound data from the host CPU (14) as ...  
WO/2000/073872
A processor for performing a block floating point Fast Fourier Transform having improved signal to quantization noise ratio performance. In the radix-2 Decimation In Time algorithm, overflow between stages is prevented by a scale down by...  
WO/2000/068774
A computer system (AP1) includes a RAM-based FIFO (20) for buffering communications between a host processor (10) and a remote serial-communications device (16). The FIFO provides for quadlet, doublet, and singlet transfer widths dependi...  
WO/2000/068794
The aim of the invention is to facilitate a secure writing of a pointer (P) that points to the respective actual data set in a cyclic memory or a circular memory such as an EEPROM. To this end, the new data set (D'#3) is written into the...  
WO/2000/062154
A cyclic buffer is implemented using logical blocks corresponding to the physical blocks of the buffer. The logical blocks are mapped to the physical blocks of the cyclic buffer, and are used to create an index to the buffer. Each entry ...  
WO/2000/062153
The present invention relates to a buffer device of the first-in-first-out type. The buffer device comprises a data inlet In, a data outlet Out and a storage buffer MEMFIFO1. The buffer device also comprises an integrated circuit IC, whi...  
WO/2000/060749
An interleave/deinterleave processing in which input data is arranged and stored in a storage area having continuous addresses of a RAM (103), the stored data is read with double precision in order of address of the RAM (103) according t...  
WO/2000/057268
A system (20) converts data from input field types to output field types. The system (20) receives a plurality of input attributes and output attributes from an application program (10), dynamically generates a plurality of data field co...  
WO/2000/054163
An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data ...  
WO/2000/054141
The invention relates to a system and a method for temporary decoupling of selection, processing and elimination of data to be transmitted or received from pure transmission or reception of data telegrams of a data bus. Temporary decoupl...  
WO/2000/052567
The invention relates to a system for transmitting data records that are divided into a plurality of words between two control units (5, 20). The inventive system comprises a memory configuration having a first memory (A) and a second me...  
WO/2000/049492
Systems and methods for transferring very large data files to a remote location (17). The systems and methods fragment the very large data file into smaller ordered blocks using file conversion software (11a) loaded onto a computer proce...  
WO/2000/049485
A circuit (34) receives data asynchronously from a bus (48) on which the data is transferred on both rising and falling edges of a control signal (H-STROBE), and provides the data to an output (FIFO_DIN) synchronously with a local clock ...  
WO/2000/046949
To synchronize a regulary occurring pulse train to the average of a bunched pulse train, an oscillator generates a plurality of differently phase shifted signals at a given frequency. One of the phase shifted signals is selected as an ou...  
WO/2000/046661
The drift between a write pointer and a read pointer processing packets of data through a FIFO buffer is compensated for by adjusting the start of the read pointer relative to the write pointer. The FIFO buffer is sized to include a numb...  
WO/2000/038045
A FIFO unit for buffering serial communications includes a register and a unit for maintaining a single pointer. The single pointer functions as an IN pointer during writes and an OUT pointer during reads. The same circuitry maintains th...  
WO/2000/038112
A code compaction based on macro substitutions is presented wherein the choice of possible macro substitutions is guided by an evolutionary algorithm process. In a preferred embodiment, a random population of sets of macro substitutions ...  
WO/2000/038063
A method and system for allocating memory. The computer system on which the memory allocation system executes may support the simultaneous execution of multiple threads. Under control of a thread, the memory allocation system first ident...  
WO/2000/033166
Methods and apparatus for implementing a technique for determining a data rate of a serial bitstream using pattern recognition and for matching a clock speed of a deserializer to that data rate. In one implementation, a port (100) for co...  

Matches 301 - 350 out of 6,156