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Patent Searching and Data


Matches 351 - 400 out of 9,145

Document Document Title
WO/2002/069500A1
The present invention provides for the compression of digital and analog data for storage and transmission. Analog data in the form of an analog signal (3) is converted into a digital signal (6) by an analog-to-digital converter (5). The...  
WO/2002/063461A1
The invention discloses a method of improving the playback of streamed media on a client device by overcoming problems caused by variations in the transmission delay of packets due to network and transport protocol operation and variatio...  
WO/2002/063776A2
The invention concerns a method for compressing a structured document comprising nested information elements, the document being associated with at least a tree-like structure schema (1) defining a structure of the document and comprisin...  
WO2002019535A9
Logic circuitry performs a matching algorithm function. A memory produces a match signal that indicates which memory cells contain data that matches input address data to the memory. A first logic AND function performs a logic AND betwee...  
WO/2002/060226A1
An improved technique of interfacing a computer lighting device to a control computer is disclosed, wherein a hardware device is interposed between the control computer and the lighting device. The hardware device handles certain functio...  
WO/2002/057891A1
A plurality of data signal delay (102) and sampling (103) circuits are connected to a clock terminal and a parallel data terminal to provide time-slice bit samples of each information bit of a parallel data signal. A comparator (104) and...  
WO2001086449A3
A system and method for compensating for differences between a recovered receive clock and an internal transmit clock in an elastic buffer and thereby preventing corruption of data. In one embodiment, the system comprises a circularly ac...  
WO/2002/056478A1
Data is compressed through implementing the inserting of a regressive reference string scheme, each such reference replacing a particular data string through referring to an associated earlier data string of identical content. In particu...  
WO/2002/054227A1
In one embodiment, a modulo addressing unit for a processor is described that includes a plurality of adders to generate an uncorrected target modulo address and at least one corrected target modulo address in parallel. A comparator sele...  
WO/2002/052399A1
A method for controlling a jitter buffer and a communication apparatus implementing the method and functioning as a first node of a communication system, wherein the jitter buffer is adapted to buffer a stream of blocks of compressed spe...  
WO/2002/050655A2
A device for controlling a stream of data packets, comprising: a buffer (2) means (4) adapted to monitor a fill level of said buffer (2), means (5) to detect a fill level condition of said buffer (2), in which incoming data has to be dro...  
WO/2002/050656A2
Techniques for indicating partial fullness levels of a FIFO comprising a plurality of stages using a partial fullness detector, such as a m-out-of-n detector. According to an embodiment, the m-out-of-n detector is coupled to 'n' stages o...  
WO2000057268A9
A system (20) converts data from input field types to output field types. The system (20) receives a plurality of input attributes and output attributes from an application program (10), dynamically generates a plurality of data field co...  
WO2002003612A3
A technique is described for providing service to multiple ports sharing common scheduling resources. According to one implementation, the scheduling technique of the present invention may be used to dynamically balance the frequency of ...  
WO2002003629A3
A improved connection shaping technique is disclosed, whereby at least one high-priority "preemptive" service flow is initiated at a customer entity in order to limit or restrict the effective usable bandwidth on a particular line or con...  
WO2001053942A3
An array-based concurrent shared object implementation has been developed that provides non-blocking and linearizable access to the concurrent shared object. In an application of the underlying techniques to a deque, the array-based algo...  
WO2001082081A3
An integrated circuit includes an address register, clocked by the clock signal corresponding to the TAP, used to address a control/status register within the integrated circuit. The address register receives a signal indicating that an ...  
WO/2002/033537A1
The present invention proposes a multiplier device performing multiplication of different powers of two serially in time (not in parallel) in order to further reduce the area needed for a hardware realization. By virtue thereof, it is en...  
WO/2002/031664A2
A system, method and article of manufacture are provided for data transfer across different clock domains. A request for transferring data from a sending (transmitting) process in a first domain to a receiving process in a second domain ...  
WO2001053943A3
A linked-list-based concurrent shared object implementation has been developed that provides non-blocking and linearizable access to the concurrent shared object. In an application of the underlying techniques to a deque, the linked-list...  
WO/2002/027464A2
A novel FIFO data structure in the form of a multi-dimensional FIFO. For a rectangular multi-dimensional FIFO, data items are received at an input of an N-row-by-M-column FIFO array of cells and transferred to an output, via a predetermi...  
WO2000046661A9
The drift between a write pointer and a read pointer processing packets of data through a FIFO buffer is compensated for by adjusting the start of the read pointer relative to the write pointer. The FIFO buffer is sized to include a numb...  
WO2002003745A3
A technique is disclosed for scheduling data parcels from at least one client process to be output for transmission over a first communication line having an associated first bit rate. The at least one client process may include a plural...  
WO/2002/023476A2
A signal processing apparatus for processing signals like video, audio or graphics contains signal processor units that produce and consume a stream of data items relating to samples along at least one dimension of an at least one dimens...  
WO/2002/023326A1
Operations that involve denormalized numbers are handled by restructuring the input values for an operation as normalized numbers, and performing calculations on the normalized numbers. As a first step in the process of performing an ope...  
WO/2002/021848A1
The invention concerns a method for compressing and decompressing a structured document, associated with at least a tree diagram structure (1; 31, 39, 43) defining a document structure and comprising nested structure elements, associated...  
WO/2002/021285A2
A circuit arrangement, apparatus and method control the transfer of data into an intermediate buffer (28) associated with a split transaction interconnect or bus (16a) by conditioning such transfer on both the amount of free space in the...  
WO/2002/019093A1
An instruction set architecture (ISA) for application specific signal processor (ASSP) is tailored to digital signal processing applications. The ISA implemented with the ASSP, is adapted to DSP algorithmic structures. The ISA of the pre...  
WO/2002/019535A1
Logic circuitry performs a matching algorithm function. A memory produces a match signal that indicates which memory cells contain data that matches input address data to the memory. A first logic AND function performs a logic AND betwee...  
WO/2002/017494A2
A gray-code counter system (AP1) for a RAM-based FIFO comprises a read pointer (10), a write pointer (20), and a detector (30). The read pointer includes a gray-code decoder (11), a binary incrementer (12), a gray-code encoder (13), and ...  
WO/2002/014992A1
A system and method for synchronizing the skip pattern to two clock domains and initializinbg the clock skipping buffer (50) which enables data transfers between the two clock domains. In one embodiment, a circuit comprises a pair of ali...  
WO/2002/008917A1
A queuing architecture and method for scheduling disk drive access requests in a video server. The queuing architecture employs at least two access request queues (221; 222, 223) for each disk drive (120) within a disk drive (120) within...  
WO/2002/003206A2
An architecture and techniques of the present invention combine multiple queues into a single multientity queue that functions in conjunction with a free queue embodied within the multientity queue. This multienity queue enables a device...  
WO/2002/003612A2
A technique is described for providing service to multiple ports sharing common scheduling resources. According to one implementation, the scheduling technique of the present invention may be used to dynamically balance the frequency of ...  
WO/2002/003629A2
A improved connection shaping technique is disclosed, whereby at least one high-priority 'preemptive' service flow is initiated at a customer entity in order to limit or restrict the effective usable bandwidth on a particular line or con...  
WO/2002/003745A2
A technique is disclosed for scheduling data parcels from at least one client process to be output for transmission over a first communication line having an associated first bit rate. The at least one client process may include a plural...  
WO/2001/095123A1
The present invention relates to data representation and more paricularly to a system and method for creating a source document and presenting the source document to a user in a target format. The system selects the target DTD of the tar...  
WO/2001/095088A1
A system and method for creating a source document and presenting the source document to a user in a target format are described. A construction user interface area (437) is presented to enable a user to create the source document in a s...  
WO/2001/095089A2
A FIFO design interfaces a sender subsystem and a receiver subsystem operating on different time domains. The sender subsystem and the receiver subsystem may be synchronous or asynchronous. The FIFO circuit includes a put interface confi...  
WO/2001/093051A1
A data processing system and a data processing method control the feed of a clock in accordance with various processing instructions issued from an instruction issuer, and request a data transfer without finishing the data processing ins...  
WO/2001/086449A2
A system and method for compensating for differences between a recovered receive clock and an internal transmit clock in an elastic buffer and thereby preventing corruption of data. In one embodiment, the system comprises a circularly ac...  
WO/2001/082053A2
A FIFO design interfaces a sender subsystem and a receiver subsystem working at different speeds. Global control signals relating to whether the FIFO is nearly full or nearly empty are synchronized to the sender subsystem clock and the r...  
WO/2001/082081A2
An integrated circuit includes an address register, clocked by the clock signal corresponding to the TAP, used to address a control/status register within the integrated circuit. The address register receives a signal indicating that an ...  
WO/2001/079987A1
A synchronization circuit (P2P) for interfacing a first digital circuit functioning with a first clock (CLK1) and a second digital circuit functioning with a second clock (CLK2) that may be different from the first clock (CLK1) in terms ...  
WO2000038063A9
A method and system for allocating memory. The computer system on which the memory allocation system executes may support the simultaneous execution of multiple threads. Under control of a thread, the memory allocation system first ident...  
WO/2001/071482A1
A first-in first-out buffer (FIFO) with multiple outputs. The FIFO has an input for writing data into the FIFO. The FIFO has multiple outputs for reading the data out of the FIFO. Each output is independent from the other outputs, and ca...  
WO/2001/065774A1
A multi-port communications system (100) is described, which includes hardware based subsystems for performing both physical medium dependent operations and transport convergence operations on a data transmission. A software based subsys...  
WO2001004724A9
A partitioned shift right logic circuit (300) that is programmable and contains rounding support (310a, 310b, 320a, 330a, and 330b). The circuit of the present invention accepts 32-bit value (360) and a shift amount (350) and then perfor...  
WO2001004724A3
A partitioned shift right logic circuit (300) that is programmable and contains rounding support (310a, 310b, 320a, 330a, and 330b). The circuit of the present invention accepts 32-bit value (360) and a shift amount (350) and then perfor...  
WO/2001/058168A1
A method of compressing an image frame composed of an array of pixels in the form of digital signals comprises a two stage codebook search. In the first stage the pixelated image frame and the pixelated codebook patches are transformed t...  

Matches 351 - 400 out of 9,145