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Patent Searching and Data


Matches 351 - 400 out of 9,213

Document Document Title
WO/2003/017541A1
A variable size FIFO memory (13) is provided by the use of head (17) and tail (16) FIFO memories operating at a very high data rate and then an off chip buffer memory (18), for example, of a dynamic RAM type, which temporarily stores dat...  
WO/2003/012648A1
A data formatter (100) includes a shift register (112) and a pointer manager (120). The shift register (112) receives data from a providing RAM (108) and shifts that data in response to reading data from the providing RAM (108) and writi...  
WO/2003/007517A1
This invention relates to the field of packet communications. More particularly, this invention is a method and system for using a jitter absorption buffer to absorb propagation delay variation in packet arrival time. The invention uses ...  
WO/2003/007614A2
The invention regards a method for compressing a hierarchical tree describing a multimedia signal, said tree comprising nodes and leaves, which can be associated to contents of at least two distinct types.According to the invention, said...  
WO/2003/001360A2
A first-in, first-out (FIFO) memory system (10) includes first and second FIFOs (A and B). First and second multiplexers (12, 14) each have two input terminals for receiving data. An output terminal of the first multiplexer (12) is coupl...  
WO/2002/101938A2
According to the invention, in order to carry out an equidistant data transfer between clock pulse domains having different clock pulse rates, a combination of a counter (1) and a finite state machine (2) is used. Said counter (1) contin...  
WO/2002/099554A2
The invention relates to a power controlled electronic circuit comprising a controller which is used to process a processor task and a power determination device which determines the power available for the controller. A control device o...  
WO/2002/099621A1
A first in, first out (FIFO) circular buffer enables high speed streaming data transfer between integrated circuit devices by performing more than one data element transfer unidirectionally by having a plurality of ports to address a mem...  
WO/2002/097606A1
A system for providing a floating point product comprises an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the firs...  
WO/2002/097607A1
A floating point unit generates results in which status information generated for an operation is encoded within the resulting operand, instead of requiring a separate floating point status register for the status information. In one emb...  
WO/2002/097620A2
The present invention provides safe and secure application distribution and execution by providing systems and methods that test an application to ensure that it satisfies predetermined criteria associated with the environment in which i...  
WO/2002/097604A2
A system for providing a floating point sum comprises an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first fl...  
WO2002063776A3
The invention concerns a method for compressing a structured document comprising nested information elements, the document being associated with at least a tree-like structure schema (1) defining a structure of the document and comprisin...  
WO/2002/093392A1
A data processor (1) comprises a central processing unit (2), a memory (5) accessible by the central processing unit, input/output circuits (12, 13), and a FIFO control circuit (6) for operating the memory as a FIFO buffer for the input/...  
WO/2002/093358A1
Distributed compression of a data file can comprise a master server module for breaking the data file into data blocks and transmitting the data blocks to worker server modules. A first worker server module can compress a first data bloc...  
WO/2002/091188A1
An apparatus for gathering queue performance data includes an event conditioning logic unit (220) that receives a queue enter signal (211), a queue exit signal (213), and a queue not empty signal (215) from a queue (210). This apparatus ...  
WO/2002/088928A2
The invention relates to an improved method and to a corresponding device for adapting the data rate of a data stream while using a first in, first out (FIFO) memory (1) into which data packets of the data stream with a first data rate a...  
WO2002003206A3
An architecture and techniques of the present invention combine multiple queues into a single multientity queue that functions in conjunction with a free queue embodied within the multientity queue. This multienity queue enables a device...  
WO2002071196A8
The invention relates to a data processing unit (VPU) comprising logic cells (PAEs) clocked in operational fields in different configuration states and a clocking input means for setting the clocking of the logic cell. According to the i...  
WO/2002/082348A2
Method and system for real time monitoring of activities within a health care tracking environment generates a substantially complete and accurate electronic patient care record, and makes information on evaluation of patient care, inclu...  
WO2002027464A3
A novel FIFO data structure in the form of a multi-dimensional FIFO. For a rectangular multi-dimensional FIFO, data items are received at an input of an N-row-by-M-column FIFO array of cells and transferred to an output, via a predetermi...  
WO/2002/079971A1
Disclosed is a programmable buffer circuit (16) for interfacing a CPU (12) to a plurality of channel interfaces (814). The buffer circuit includes a dual port memory (18) having a first port coupled to a CPU data bus and a second port co...  
WO2001037076A3
A system for detecting underflow and overflow errors arising within a ring buffer. When the system receives a data word to be transferred through the ring buffer, the system generates a flow indicator value to be stored with the data wor...  
WO2002050655A3
A device for controlling a stream of data packets, comprising: a buffer (2) means (4) adapted to monitor a fill level of said buffer (2), means (5) to detect a fill level condition of said buffer (2), in which incoming data has to be dro...  
WO/2002/078227A2
In parallel networks that include a transmission media and at least one I/O processor connected to the transmission media by a core, a buffering device is provided that compensates for different latencies from all physical lanes in data ...  
WO/2002/077829A2
A communication system includes a core for providing speed reduction in communications between a transmission media and a processor having an upper link layer in a parallel-serial architecture. The core includes a lower logic layer, seri...  
WO/2002/071248A2
According to the invention, memories are associated with a reconfigurable component (VPU) at the inputs and outputs thereof, so that the internal data processing and particularly the reconfiguration cycles can be decoupled from the exter...  
WO/2002/071196A2
The invention relates to a data processing unit (VPU) comprising logic cells (PAEs) clocked in operational fields in different configuration states and a clocking input means for setting the clocking of the logic cell. According to the i...  
WO/2002/071249A2
The invention relates to procedures and methods for administering and transferring data within multi-dimensional systems consisting of transmitters and receivers. The division of a data stream into several independent branches and the su...  
WO/2002/069500A1
The present invention provides for the compression of digital and analog data for storage and transmission. Analog data in the form of an analog signal (3) is converted into a digital signal (6) by an analog-to-digital converter (5). The...  
WO/2002/063776A2
The invention concerns a method for compressing a structured document comprising nested information elements, the document being associated with at least a tree-like structure schema (1) defining a structure of the document and comprisin...  
WO/2002/063461A1
The invention discloses a method of improving the playback of streamed media on a client device by overcoming problems caused by variations in the transmission delay of packets due to network and transport protocol operation and variatio...  
WO2002019535A9
Logic circuitry performs a matching algorithm function. A memory produces a match signal that indicates which memory cells contain data that matches input address data to the memory. A first logic AND function performs a logic AND betwee...  
WO/2002/060226A1
An improved technique of interfacing a computer lighting device to a control computer is disclosed, wherein a hardware device is interposed between the control computer and the lighting device. The hardware device handles certain functio...  
WO/2002/057891A1
A plurality of data signal delay (102) and sampling (103) circuits are connected to a clock terminal and a parallel data terminal to provide time-slice bit samples of each information bit of a parallel data signal. A comparator (104) and...  
WO2001086449A3
A system and method for compensating for differences between a recovered receive clock and an internal transmit clock in an elastic buffer and thereby preventing corruption of data. In one embodiment, the system comprises a circularly ac...  
WO/2002/056478A1
Data is compressed through implementing the inserting of a regressive reference string scheme, each such reference replacing a particular data string through referring to an associated earlier data string of identical content. In particu...  
WO/2002/054227A1
In one embodiment, a modulo addressing unit for a processor is described that includes a plurality of adders to generate an uncorrected target modulo address and at least one corrected target modulo address in parallel. A comparator sele...  
WO/2002/052399A1
A method for controlling a jitter buffer and a communication apparatus implementing the method and functioning as a first node of a communication system, wherein the jitter buffer is adapted to buffer a stream of blocks of compressed spe...  
WO/2002/050655A2
A device for controlling a stream of data packets, comprising: a buffer (2) means (4) adapted to monitor a fill level of said buffer (2), means (5) to detect a fill level condition of said buffer (2), in which incoming data has to be dro...  
WO/2002/050656A2
Techniques for indicating partial fullness levels of a FIFO comprising a plurality of stages using a partial fullness detector, such as a m-out-of-n detector. According to an embodiment, the m-out-of-n detector is coupled to 'n' stages o...  
WO2000057268A9
A system (20) converts data from input field types to output field types. The system (20) receives a plurality of input attributes and output attributes from an application program (10), dynamically generates a plurality of data field co...  
WO2002003629A3
A improved connection shaping technique is disclosed, whereby at least one high-priority "preemptive" service flow is initiated at a customer entity in order to limit or restrict the effective usable bandwidth on a particular line or con...  
WO2002003612A3
A technique is described for providing service to multiple ports sharing common scheduling resources. According to one implementation, the scheduling technique of the present invention may be used to dynamically balance the frequency of ...  
WO2001053942A3
An array-based concurrent shared object implementation has been developed that provides non-blocking and linearizable access to the concurrent shared object. In an application of the underlying techniques to a deque, the array-based algo...  
WO2001082081A3
An integrated circuit includes an address register, clocked by the clock signal corresponding to the TAP, used to address a control/status register within the integrated circuit. The address register receives a signal indicating that an ...  
WO/2002/033537A1
The present invention proposes a multiplier device performing multiplication of different powers of two serially in time (not in parallel) in order to further reduce the area needed for a hardware realization. By virtue thereof, it is en...  
WO2001053943A3
A linked-list-based concurrent shared object implementation has been developed that provides non-blocking and linearizable access to the concurrent shared object. In an application of the underlying techniques to a deque, the linked-list...  
WO/2002/031664A2
A system, method and article of manufacture are provided for data transfer across different clock domains. A request for transferring data from a sending (transmitting) process in a first domain to a receiving process in a second domain ...  
WO/2002/027464A2
A novel FIFO data structure in the form of a multi-dimensional FIFO. For a rectangular multi-dimensional FIFO, data items are received at an input of an N-row-by-M-column FIFO array of cells and transferred to an output, via a predetermi...  

Matches 351 - 400 out of 9,213