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WO/1999/056457 |
The present invention provides such a data transmission system (100), which encodes and transmits video, audio and text information across a global computer network without the use of a personal computer, workstation or video capture car...
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WO/1999/054812 |
An arrangement for shifting packed data is provided, in which packed data have multiple partial data each having n-byte, n being an integer greater or equal to 1. The arrangement comprises: a shifter for shifting the packed data by a pre...
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WO/1999/055000 |
An apparatus for correcting skew between data signals and a clock signal in a system where the data and clock signals are transmitted and using low-voltage differential swing is disclosed. The apparatus comprises, in one embodiment, a de...
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WO/1999/051021 |
A device management module (11) particularly for use in a receiver/decoder for a broadcast digital television system in which received signals are passed through a receiver to the receiver/decoder and thence to a television set. The modu...
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WO/1999/050741 |
The present invention relates to overflow protection of a buffer of a first-in-first-out type, able to store a first number $i(x) of messages from the digital module. The method is characterised by creating and sending pace messages to t...
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WO/1999/041670 |
A method of dynamically changing draining priority in a first-in/first out ('FIFO') device to prevent over-run errors is described. The method includes the steps of detecting data received in the FIFO, asserting a request to drain the FI...
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WO/1999/036849 |
A system provides a write buffer with random access snooping capability. A random access write buffer includes a write buffer controller and a random access memory (RAM) containing a content addressable memory (CAM) address store and a r...
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WO/1999/035563 |
A circular queue is asynchronously accessed and managed by two separate processing elements. Each data element is placed on the queue together with a zero data element that both marks the tail of the queue and signifies that the queue is...
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WO/1999/028816 |
Buffer memory is dynamically assigned to a number of users according to demand so as to increase the efficiency of use of the memory device. Each user is assigned a plurality of, not necessarily sequential, memory means which are linked ...
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WO/1999/026130 |
A system is provided for the remote control of one computer from another in which selectable compression speeds are utilized to minimize overall screen refresh time. In one embodiment, an algorithm selection module at one computer choose...
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WO/1999/026145 |
A video graphics controller (VGC) for communicating with a frame buffer memory and a display device includes a first-in, first-out (FIFO)-configured memory, a memory controller for communicating with the frame buffer memory and controlli...
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WO/1999/022302 |
A 'virtual FIFO' system for use in buffering data between transacting buses (12, 18) that transfer data at different rates includes a memory device (31) and a controller (35) that partitions the memory device into multiple regions (32-1,...
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WO/1999/019798 |
A method using a RAM (10) and a short shift register (20) to emulate a long shift register to store a stream of incoming bits. A pointer points to one of the RAM registers. To store an incoming bit, the contents of the RAM register point...
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WO/1999/019785 |
The present invention provides a method and apparatus for synchronizing signal transfers between two clock domains, where the clock domains have a gear ratio relationship. A gear ratio means thatthe clocks are related by a ratio, such th...
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WO/1999/013397 |
A FIFO memory device is shown which uses embedded logic and DRAM on the same chip. A memory controller controls the transfer of data from input and to output ports to match the access speed of the DRAM to the input and output requirement...
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WO/1999/012090 |
The inventive integrated circuit has an interface circuit between the anolog circuit part (FC, or 'full-custom') and the digital circuit part (SC, or 'semi-custom') for each signal to be exchanged. Said interface circuits are assembled i...
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WO/1999/009467 |
A datastream-processing buffer memory organization has a datastream input, storage for transiently storing the datastream, accesses the buffer memory, and means for memory housekeeping. In particular, the management means is executed in ...
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WO/1998/055916 |
A method of processing an image comprising the steps of decomposing the image into detail images at successive resolution levels. The detail images at successive resolution levels contain image information at respective spatial scales. F...
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WO/1998/050850 |
The present invention relates to a device (1) for recording and/or reproducing information signals. The device has an input (2) for receiving an information signal to be recorded, a memory (9), a recording unit (3) which is suitable for ...
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WO/1998/049616 |
An instruction (also called a 'bit reversal instruction') for reversing the order of bits in an input signal is implemented by reusing one or more components in a datapath normally found in a processor. Specifically, a bit reversal instr...
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WO/1998/039772 |
A multi-channel recursive interface having independent channels that can be used in, for example, multi-level memory systems (310) is disclosed. Separate read and write command channels (100, 102) and read and write completion channels (...
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WO/1998/036357 |
Apparatus and methods for allocating shared memory utilizing linked lists (LLs) use a management RAM which controls the flow of data to/from a shared memory (RAM), and stores information regarding a number of LLs and a free link list (FL...
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WO/1998/036534 |
A split-queue architecture and method of queuing entries to the queue has a three part queue. The first part of the queue is a write side in which entries to the queue are received. The second part of the queue is a read side from which ...
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WO/1998/036587 |
A method and arrangement for queuing data in a prioritized manner have a queue with a single queue write side in which data entries are input to the queue. The queue also has a plurality of queue read sides, with each read side having a ...
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WO/1998/036539 |
Management data is supplied to a management agent by a network switch by generating management packets having at least a portion of a received data packet, and management information specifying receive status and network switch response ...
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WO/1998/036535 |
An integrated multiport switch (IMS) in which one combinational logic and register arrangement is provided for executing similar media access control (MAC) functions for a plurality of switch ports. The current access state at each of a ...
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WO/1998/036358 |
A method and arrangement for maintaining a time order of entries in a memory determines a row in which the entry will be stored, the memory being logically divided into rows and columns. The columns are arranged sequentially in each row ...
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WO/1998/036536 |
A method and arrangement for reclaiming buffers used to store frames, following the transmission of a frame, checks to determine whether the transmission of a frame is the last copy of that frame to be transmitted. If it is the last copy...
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WO/1998/036528 |
A method and arrangement for transmitting multiple copies of a frame from a network switch in a packet switched network stores a single copy of the frame received at the switch into external memory. The frame is stored at a location in m...
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WO/1998/036531 |
A method and arrangement for initiating forwarding of data from a device having multiple receive and transmit ports as a function of the data received at the device include a plurality of ports for receiving and transmitting data. A port...
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WO/1998/036530 |
An arrangement and a method of maintaining a count of the number of copies of a frame that have been transmitted from a network switch uses a cache memory to store the number of copies of a frame to be transmitted from the network switch...
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WO/1998/036538 |
An integrated multiport switch having an interface connected between the MAC of each port and a MIB report bus, whereby MIB reports for the plurality of switch ports are transmitted individually to a switch MIB engine, fed by the MIB rep...
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WO/1998/033281 |
Compression-encoding sections (311(1), 311(2), and 311(3)) generate compressed data by individually compression-encoding input signals VS, AS, and SS. An SCSI interface (32) outputs the compressed data to a DSM (50). Output buffers (312(...
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WO/1998/026348 |
N separate identical finite state machines service N corresponding channels. In one embodiment, each channel operating at a clock frequency F is serviced by the same combinatorial logic block which runs at an N*F clock frequency. The cha...
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WO/1998/021647 |
A mechanism to effectively retrieve residual data received from a serial data source is provided. As the shift register receives serial data from the serial data source, the activities and content of the shift register is monitored. Stat...
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WO/1998/015891 |
Apparatus (60; 220; 600; 800; 1000) and method (70; 300; 500; 700; 900) are provided for converting, at high speed, without queuing of data, and with absolute accuracy, parallel bytes of digital data having a given number of binary bits ...
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WO/1998/012623 |
A single port First-In-First-Out (FIFO) data storage device that include an over-write protection feature and diagnostic capabilities. The FIFO contemplated by the invention is fabricated using a field programmable gate array; yet is as ...
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WO/1998/011547 |
A recording and reproducing system for recording a first information flow on an information carrier and simultaneously processing a further information flow via the information carrier is disclosed. The system comprises a reading/writing...
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WO/1998/006028 |
The adaptive compression technique improves the Lempel-Ziv (LZ) technique because it reduces the required storage space (18) and transmission time with transferring data (22). Pre-filled compression dictionaries (48) are utilized to reso...
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WO/1998/002803 |
A load/store buffer is provided which allows both load memory operations and store memory operations to be stored within it. Because each storage location may contain either a load or a store memory operation, the number of available sto...
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WO/1997/043764 |
An addressable memory device for storing blocks of varying length, utilises a write pointer (18) to indicate the address of the next location to which data are to be written and an erase pointer (16) to indicate the address of the next l...
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WO/1997/041514 |
A qualified burst cache facilitates burst mode data transfer between a first clock domain and a second clock domain by simplifying cache control structures. A cache is marked as qualified when full or there is no more data to be written ...
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WO/1997/038434 |
A recompression server (20) that automatically decompresses selected pre-compressed data streams and recompresses the decompressed data to a greater degree than the original pre-compressed data. In one embodiment, the recompression serve...
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WO/1997/037298 |
The invention provides for a first-in-first-out (FIFO) memory system having a first fall-through FIFO (102; 302) having an input and an output, a pointer-based FIFO having an input and an output, wherein the input of the pointer-based FI...
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WO/1997/033222 |
An apparatus for performing a shift operation on a packed data element (901) having multiple values. The apparatus having multiple muxes (910-913), each of the multiple muxes having a first input, a second input, a select input and an ou...
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WO/1997/017809 |
The bit rate of an MPEG-2 or other digital coder can be varied without causing buffer underflow or overflow in a downstream decoder by controlling coder buffer occupancy and by employing an oversized coder buffer.
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WO/1997/013326 |
An apparatus and a method for controlling a mode of operation of a data converter is based on a length of an input word signal to the data converter. The apparatus includes a bit counter that counts the number of bits in the word receive...
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WO/1997/008620 |
A data processing system transports data via successive stages of a pipeline. Whenever possible the stages are in the transparent mode so that data made available can travel through the pipeline with a minimum delay. The arrival of data ...
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WO/1997/008608 |
An apparatus for including in a processor a set of instructions that support operations on packed data required by typical multimedia applications. In one embodiment, the invention includes a processor having a storage area (150), a deco...
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WO/1997/008610 |
A processor having a first and second storage having a first and second packed data, respectively. Each packed data includes a first, second, third, and fourth data element. A multiply-add circuit is coupled to the first and second stora...
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