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WO/2024/069604A1 |
The present disclosure provides a system and method for implementing a physical layer architecture of base station in a heterogeneous platform, which involves time critical, computationally intensive, and huge data processing modules or ...
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WO/2024/063844A1 |
Techniques are disclosed relating to dedicated power function circuitry for a floating-point power instruction. In some embodiments, execution circuitry is configured to execute a floating- point power instruction to evaluate the power f...
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WO/2024/049791A1 |
Disclosed herein is a co-designed compiler and CGRA architecture that achieves both high programmability and extreme energy efficiency. The architecture includes a rich set of control-flow operators that support arbitrary control flow an...
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WO/2024/044150A1 |
Techniques for parallel processing based on a parallel processing architecture with bin packing are disclosed. An array of compute elements is accessed. Each compute element is known to a compiler and is coupled to its neighboring comput...
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WO/2023/071489A9 |
The present application relates to the technical field of data processing. Disclosed are a sensor data processing method, an electronic device, and a readable storage medium, which are intended to correct an ODR of a sensor. The specific...
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WO/2024/017337A1 |
Disclosed in the present application are a FIFO storage control circuit and method, a chip, and an electronic device. The circuit comprises: a single-port random access memory, a switching control circuit and a switching circuit, wherein...
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WO/2024/010714A1 |
A drug delivery device includes a microcontroller, a pressure sensor, and/or a fluid pathway including a reservoir, a pump downstream of the reservoir, and/or a fluid line downstream of the pump. The reservoir may be configured to receiv...
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WO/2024/006900A1 |
A disclosed method for making efficient picks of micro-operations for execution includes selecting a first set of micro-operations that are ready for execution during a certain clock cycle. The method also includes selecting a second set...
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WO/2023/237121A1 |
The present application provides a data processing method and apparatus and a related device. The method comprises: a computing device determining a first reference value according to a plurality of pieces of first data to be compressed;...
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WO/2023/224182A1 |
A method of performing a homomorphic permutation via a terminal includes: generating, via a ciphertext generation portion, a first ciphertext, which is modified from a basic ciphertext by adding noise to the basic ciphertext; transmittin...
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WO/2023/220069A1 |
A learning system deploys a dynamic data conversion module (DDCM) that is customized to perform one or more extract, transform, and load (ETL) operations on the local client data that is used to train at least a portion of a master machi...
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WO/2023/204534A1 |
Disclosed is a method of processing an encrypted message. The method of processing an encrypted message includes: performing calculation on a homomorphic encrypted message on an approximate message including an error, and when a proporti...
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WO/2023/185035A1 |
Disclosed in the present application is a direct memory access architecture. The direct memory access architecture comprises a direct memory access control component, a read data moving component, a write data moving component and a data...
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WO/2023/170309A1 |
An electronic device is provided for securing and desynchronizing register transfers as a mitigation strategy to side channel attacks that employ power analysis profiling, whereby leakage information produced as a result of register swit...
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WO/2023/170815A1 |
A read-side read pointer synchronization unit (109) synchronizes a read pointer (208) with a write clock (WCLK) and takes in the result, said read pointer (208) having been generated on the side of a memory read circuit (201) which synch...
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WO/2023/147649A1 |
Systems and methods for converting distributed raw user data into processable data for data analysis, such as machine learning (ML) training or the like. In one embodiment, the method comprises generating, at a server, from a data schema...
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WO/2023/146721A1 |
One example provides a device comprising a FIFO data buffer comprising a load shift register, a request line encoder, a state machine, and one or more clocks to provide a clock signal. The load shift register comprises a plurality of reg...
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WO/2023/133438A1 |
A method for calculating a square root B having N bits of a number X having 2N bits includes iterating on bits bi of square root B starting from the most significant bit until the least significant bit of square root B. For each iteratio...
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WO/2023/129231A1 |
Embodiments of the present disclosure include a multipurpose multiply-accumulator (MAC) array circuit comprising one or more input memories for receiving operands and a plurality of multiply-accumulator circuits each selectively coupled ...
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WO/2023/129469A1 |
Methods, systems, and apparatuses to encode data for storage in genetic materials. For example, a computing system may segment user data into a plurality of data blocks and generate seed data characterizing a plurality of fountain code s...
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WO/2023/121884A1 |
Methods and apparatus employ an asynchronous first-in-first-out buffer (FIFO), that includes a plurality of entries. Control logic determines a timing separation between a write header valid signal and corresponding write data valid sign...
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WO/2023/121086A1 |
The present invention relates to the field of digital neural network computing technology and, more specifically, to a convolutional neural network computing device which: comprises a distributed memory structure storing artificial neura...
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WO/2023/103337A1 |
Disclosed is a synchronous FIFO comprising a data storage circuit, a first logic circuit, a second logic circuit and an indicator circuit. The data storage circuit comprises N first registers, N first multiplexers and N first deciders, N...
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WO/2023/066454A1 |
The present disclosure relates to a method performed by a producer (105) for inputting data items in a ring buffer (100). The producer (105) performs an atomic operation comprising obtaining a sampled value of an input counter and increm...
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WO/2023/068489A1 |
An operation circuit according to an embodiment may comprise a combiner for combining a first integer number and a second integer number among multiple integer numbers. The operation circuit may comprise a multiplier for obtaining a prod...
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WO/2023/056779A1 |
A computing-in-memory eDRAM accelerator for a convolutional neural network, which is characterized in that same comprises four P2ARAM blocks; each P2ARAM block comprises a 5T1C ping-pong eDRAM bit cell array consisting of 64x16 5T1C ping...
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WO/2023/053070A1 |
A network device transfers packets from a packet memory to one or more network interfaces for transmission by the one or more network interfaces. The transferring of packets includes transferring the packets via one or more respective tr...
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WO/2023/035427A1 |
An information generation method and apparatus based on a FIFO memory, and a device and a medium. In the method, the apparatus, the device and the medium, a write credit score and a read credit score of the current FIFO memory are determ...
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WO/2023/029937A1 |
A data processing method, which is applied in the field of computers. The method comprises the following steps: acquiring a first global read pointer for a circular storage queue, the circular storage queue comprising multiple storage ar...
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WO/2023/030555A1 |
A method and apparatus for determining a data storage bit width, and a method for storing index data. The method comprises: obtaining data to be stored, wherein there are at least four pieces of data, and performing block segmentation on...
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WO/2023/019594A1 |
Embodiments of the present application provide a data transmission circuit, a chip and a terminal, which relate to the technical field of integrated circuits. According to a first identification signal and a second identification signal,...
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WO/2023/022906A1 |
A reconfigurable compute fabric can include multiple nodes, and each node can include multiple tiles with respective processing and storage elements. A first tile in a first node can include a processor with a processor output and a firs...
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WO/2023/009466A1 |
Methods and apparatus for synchronizing data transfers across clock domains for using heads-up indications. An integrated circuit includes a first-in first-out buffer (FIFO); a memory controller configured to operate in a first clock dom...
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WO/2023/004520A1 |
The invention relates to an item of public furniture secured to a slab foundation by a pair of legs, which, in its initial form, is a bench similar to those found in public parks, but which can be folded out and converted into a picnic t...
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WO/2023/008984A1 |
Disclosed are a method and device for computing function approximation in floating point representation. According to one mode of the present invention, provided are a device, and a computer-executed method for computing function approxi...
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WO/2023/003246A1 |
Disclosed are a function approximation device and method using a multi-level look-up table, and the present embodiment provides a function approximation device and method, which approximate function values for and functions by using a mu...
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WO/2022/259411A1 |
A data flow control device (100a) comprises an input/output interface conversion unit (130) that is disposed between function units (101-1, 101-2) which perform data processing, and in a case where the input/output interfaces of the func...
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WO/2022/256391A1 |
A system for synchronizing a local audio processing clock rate of a digital signal processor (DSP) to an audio clock rate of a network to which the DSP is connected. The system includes an adjustable clock synthesizer that is configured ...
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WO/2022/231634A1 |
Various techniques are provided to implement programmable linear-feedback shift register (LFSR) circuits. In one example, the LFSR circuit includes state storage elements. Each state storage element is configured to store a state signal....
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WO/2022/231518A1 |
Methods for providing a computer system to retain information and/or analyze information including at least one processor, and a memory storing at least one program for execution. The at least one program includes instructions for receiv...
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WO/2022/225997A1 |
A method may include selecting an RNA or a set of RNAs; defining a minimum and a maximum target RNAi transcript hybridization length of the RNA or set of RNAs; and executing a computer algorithm, wherein the computer algorithm determines...
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WO/2022/197091A1 |
A parallel processing device according to an embodiment receives first to N-th inputs ({X1, Y1}, {X2, Y2}, ... {XN, YN}), and outputs first to N-th outputs (M1, M2, ... MN). The first to N-th outputs (M1, M2, ... MN) include a plurality ...
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WO/2022/188807A1 |
A data transmission system, comprising an integrated processor, a first hardware device and a first memory. The integrated processor comprises a processor and a queue element, which are connected by means of an internal bus, the queue el...
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WO/2022/160036A1 |
A method for connecting a plurality of remotely located users over a shared environment. The method includes the steps of loading, by a first user, a first data sample to a shared sequencer, which is converted to a base64 string. The bas...
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WO/2022/150058A1 |
In one embodiment, multiplier circuitry multiplies operands of a first format. One or more storage register circuits store digital bits corresponding to an operand and another operand of the first format. A decomposing circuit decomposes...
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WO/2022/142157A1 |
Disclosed are a double-buffering encoding system and a control method therefor, and a medium and a device. The double-buffering encoding system comprises: a production module, a consumption module and two buffering modules, wherein the p...
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WO/2022/133718A1 |
A number of domain specific accelerators (DSA1-DSAn) are integrated into a conventional processing system (100) to operate on the same chip by adding additional instructions to a conventional instruction set architecture (ISA), and furth...
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WO/2022/126621A1 |
A reconfigurable processing element array for zero-buffer pipelining, and a zero-buffer pipelining method. In a reconfigurable processing element array (PEA) for zero-buffer pipelining, data transmission between processing elements (PE),...
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WO/2022/105252A1 |
The present disclosure relates to a computing core, a computing chip, and a data processing device. The computing core comprises an input module configured to receive data blocks, a computing module configured to perform a hash operation...
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WO/2022/104452A1 |
A machine vision functionality deployment system for transcoding a raw machine vision data signal in an existing machine vision system for capturing sensed information from a substrate. Provided is a digital data interface bus to: receiv...
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