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Matches 1 - 50 out of 9,296

Document Document Title
WO/2019/075504A1
Methods and systems for performing clock domain crossing. The method may include receiving a start signal from an ingress domain delay device at a first egress domain delay device. The start signal may be received at a first rising edge ...  
WO/2019/054495A1
The purpose of the present invention is to provide a memory circuit device that enables the circuit to be downscaled. The memory circuit device is provided with: multiple memory cells 11, each comprising a variable resistance memory comp...  
WO/2019/009993A1
Methods, systems, and apparatus, including an apparatus for transferring data using multiple buffers, including multiple memories and one or more processing units configured to determine buffer memory addresses for a sequence of data ele...  
WO/2019/005424A1
Methods and systems for dynamically controlling buffer size in a computing device in a computing device ("PCD") are disclosed. A monitor module determines a first use case for defining a first activity level for a plurality of components...  
WO/2018/232490A1
A multilevel queue based blockchain transaction traffic shaping method is disclosed. The method includes receiving a transaction request at the blockchain from a client; inserting the transaction into the first-level queue, and using the...  
WO/2018/200274A1
At least some aspects of the present disclosure direct to systems and methods of extracting medical entry information from medical documentation. A method comprises the steps of: identifying patient information needed for a predefined me...  
WO/2018/193707A1
[Problem] The purpose of the present invention is to provide an information processing device and the like with which it is possible to prevent an increase in circuit size. [Solution] This information processing device 1 is provided with...  
WO/2018/144413A1
Superconducting devices with enforced directionality and related methods are provided. In one example, a device including a first Josephson junction transmission line (JTL) for propagating a first set of quantum signals in a first direct...  
WO/2018/144347A1
An integrated circuit may have configurable storage blocks. A configurable storage block may include a memory array, and arithmetic and control circuitry. The arithmetic and control circuitry may be used to determine whether to operate t...  
WO/2018/129930A1
A fast Fourier transform (FFT) processing method and device, and a computer storage medium. The method comprises: writing discrete digital signals in a discrete digital signal sequence into an upper memory and a lower memory according to...  
WO/2018/057349A1
A control system controls First-In First-Out (FIFO) settings (30) of a receiving system (14) (14). The control system includes a FIFO settings controller (28) that receives a first signal indicative of a first frequency of data (16) rece...  
WO/2018/042402A1
The invention relates to a software defined device interface system 10, a software defined device interface, gateway and a method of defining an interface for a device which uses a specific communication protocol for communication purpos...  
WO/2018/031468A1
Some disclosed embodiments include a platform for secure data management and, in particular, for secure data management of smart city data. A method includes converting at least a portion of a first plurality of data streams from a plura...  
WO/2018/027133A1
A system and method for obtaining a reissue of an electronic document lacking required data. The method includes creating a template for the electronic document, wherein the template is a structured dataset including at least one transac...  
WO/2017/222576A1
Systems, apparatuses, and methods for implementing asynchronous feedback training sequences are described. A transmitter transmits a training sequence indication to a receiver via a communication channel including a plurality of data lin...  
WO/2017/210798A1
A computer-implemented method for performing data storage. The method comprises the steps of: receiving data to be stored from a data source; segmenting the data into immutable core objects each being written into a collection and being ...  
WO/2017/208182A1
A first memory device stores (i) a head part of a FIFO queue structured as a linked list (LL) of LL elements arranged in an order in which the LL elements were added to the FIFO queue and (ii) a tail part of the FIFO queue. A second memo...  
WO/2017/207889A1
The invention relates to a method for processing data by means of a device (DV2) for parallel data processing comprising a unit (U1) configured to receive, on parallel inputs, a set (W) of binary words (wi). The method comprises a step c...  
WO/2017/196693A1
An architecture and associated techniques of an apparatus for hardware accelerated machine learning are disclosed. The architecture features multiple memory banks storing tensor data. The tensor data may be concurrently fetched by a numb...  
WO/2017/196694A3
Neural network specific hardware acceleration optimizations are disclosed, including an optimized multicast network and an optimized DRAM transfer unit to perform in constant or linear time. The multicast network is a set of switch nodes...  
WO/2017/171983A1
Techniques described herein perform high fidelity combination of data, for example combining time series data in response to a query. In an embodiment, a first input data stream of a first type (e.g., continuous), a second input data str...  
WO/2017/172050A1
A system with improved power performance for task executed in parallel. A plurality of processing cores each to execute tasks. An inter-core messaging unit to conveys messages between the cores. A power management agent transitions a fir...  
WO/2017/151012A1
The invention relates to the field of processing machine readable information and can be used in the exercise of commercial operations and electronic and online commerce, and also in the creation of targeted and contextual audio advertis...  
WO/2017/124186A1
A system for interactive virtual lighting of a virtual sample representative of a real-life manufactured object, based on data relative to the real-life manufactured object. A lighting calibration module generates user lighting condition...  
WO/2017/101759A1
Methods and apparatus for managing data content among in-network caches of a communication network are provided. In some embodiments, multiple registers are maintained for indexing cached data content. Different data content is indexed i...  
WO/2017/091254A1
Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mo...  
WO/2017/068405A1
Systems and methods for detecting data in a received multiple-input-multiple-output signal are provided. N signals are received from N antennas, with M being greater than or equal to three. The N signals form a vector y and are associate...  
WO/2017/039393A1
An apparatus and a method for processing data are provided. The method for processing data by a terminal, the method comprises: identifying a plurality of inspection types for a packet; determining at least one inspection type from the p...  
WO/2017/040586A1
Methods and systems of controlling frequency regulation system controllers in a utility grid frequency regulation program are shown and described. One method includes providing historical frequency regulation data and energy storage devi...  
WO/2017/027169A1
Apparatus and methods are disclosed for reordering data received in a non-contiguous order into a contiguous order. In one example of the disclosed technology, an apparatus includes a number of input buffers comprising at least a first, ...  
WO/2017/009599A1
An integrated circuit includes multiple blocks of circuitry (4, 6, 8) communicating signals via an interface 10 controlled by a clock signal. A clock mesh (20, 22) is used on at least one side of the interface driven by one or more clock...  
WO/2016/162872A1
A method of transforming data including receiving data in a first language specific form, converting the data in the first language specific form to a language agnostic form, storing the data in the language agnostic form, converting the...  
WO/2016/145508A1
Systems and methods for the generation of timelines for emails found on a computer. The files relating to emails on a computer are first located on the machine. These files are then analyzed and each email is extracted into a separate fi...  
WO/2016/071667A1
A processing apparatus (200) includes floating point arithmetic circuitry (214, 216) coupled to monitoring circuitry (226). The monitoring circuitry stores exponent limit data indicating at least one of a maximum exponent value and a min...  
WO/2016/058355A1
Disclosed is a data caching method, comprising: according to an input port number of a cell, storing the cell in a corresponding first-in first-out queue; determining that a cell to be dequeued can be dequeued in the current Kth cycle, s...  
WO/2016/045288A1
Disclosed are an asynchronous FIFO controller and a method for preventing data overflow of an asynchronous FIFO buffer. The method may comprise: an asynchronous FIFO controller acquires the data volume to be acquired by a second FIFO buf...  
WO/2016/049350A1
Systems and methods are provided for determining identifier information associated with media content stored in a storage device; wherein the storage device comprises a plurality of clusters and stores a media file including media conten...  
WO/2016/025487A1
Methods for monitoring subject compliance with a prescribed treatment regimen are disclosed. In an embodiment, the method comprises measuring a drug and a metabolite level in fluid of a subject and transforming the ratio of the measured ...  
WO/2016/016726A3
A vector processor is disclosed including a variety of variable-length instructions. Computer-implemented methods are disclosed for efficiently carrying out a variety of operations in a time-conscious, memory-efficient, and power-efficie...  
WO/2016/004629A1
The present invention relates to the technical field of data processing. Provided are an expected data compressibility calculation method and device. In the solution, the expected compressibility is calculated using related indicators ch...  
WO/2015/199947A1
Method and apparatus for implementing an optimized credit return mechanism for packet sends. A Programmed Input/Output (PIO) send memory is partitioned into a plurality of send contexts, each comprising a memory buffer including a plural...  
WO/2015/176475A1
A first input first output (FIFO) data buffer, the FIFO data buffer comprising: an input port, an output port, a control unit (100), a first buffer unit (101), and a second buffer unit (102); the control unit (100) is used to obtain the ...  
WO/2015/172017A1
Methods, systems, and apparatus, including medium-encoded computer program products, for analyzing data include: receiving data including a person's responses regarding judgments of semantic similarities between items selected from a gro...  
WO/2015/157049A2
Repeat-Until-Success (RUS) circuits are compiled in a Clifford+T basis by selecting a suitable cyclotomic integer approximation of a target rotation so that the rotation is approximated within a predetermined precision. The cyclotomic in...  
WO/2015/151444A1
[Problem] To suppress increases in the size of a fully indexable dictionary while making it possible for a target bit stream to be subjected to two types of selection operation employing the fully indexable dictionary. [Solution] An info...  
WO/2015/134103A1
According to at least one example embodiment, a multi-chip system includes multiple chip devices configured to communicate to each other and share resources, such as I/O devices. According to at least one example embodiment, a method of ...  
WO/2015/134611A2
Computing systems and computer-implemented methods for specifying distributed computation (Fig. 1). The systems and methods utilize computer-readable code causing a computer to engage in reversible, self-organizing hierarchical space-lik...  
WO/2015/134611A3
Computing systems and computer-implemented methods for specifying distributed computation (Fig. 1). The systems and methods utilize computer-readable code causing a computer to engage in reversible, self-organizing hierarchical space-lik...  
WO/2015/103676A1
An interface device (200) to interface a first device (400) to a second device (500). The interface device includes a first part (200) and a second part (220). The interface device (200) further includes a third part (230) to which a mem...  
WO/2015/102579A1
According to various aspects and embodiments, a device is provided. The device includes a memory, a Controller Area Network (CAN) controller coupled to a CAN bus, at least one processor coupled to the memory and the CAN controller. The a...  

Matches 1 - 50 out of 9,296