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WO/2023/144577A1 |
A hybrid time-shared iterative multiply-accumulate circuit comprises a product storage circuit, a multiply circuit operable to receive a first input value, receive a second input value, produce a product of the first input value and the ...
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WO/2023/141933A1 |
Disclosed are apparatuses, systems, and techniques to perform and facilitate fast and efficient modular computational operations, such as modular division and modular inversion, using shared platforms, including hardware accelerator engi...
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WO/2023/137696A1 |
Disclosed in the present application are a logical operation storage unit, a storage array and a logical operation memory. The logical operation storage unit comprises a logical operation control circuit, a result storage circuit, a WBL ...
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WO/2023/134130A1 |
Disclosed in the present application are a Galois field multiplier and an erasure coding and decoding system. The Galois field multiplier comprises a plurality of basic operation units connected in series and a plurality of cyclic proces...
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WO/2023/134507A1 |
A stochastic calculation method, a circuit, a chip and a device, belonging to the technical field of circuits. A stochastic calculation circuit comprises: a control circuit, which is used to input a control parameter into a pulse input c...
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WO/2023/134905A1 |
Techniques for determining an inner product between a non-binarized first array and a second array using a binary logic unit (201) are provided. The first array is decomposed into a plurality of binarized arrays by determining a respecti...
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WO/2023/131432A1 |
The invention relates to a device for identifying at least one synchronicity range (SB) of two time series of random numbers, a first time series ((Ak)) and a second time series ((Bk)). The device comprises - a first non-deterministic ra...
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WO/2023/133438A1 |
A method for calculating a square root B having N bits of a number X having 2N bits includes iterating on bits bi of square root B starting from the most significant bit until the least significant bit of square root B. For each iteratio...
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WO/2023/124235A1 |
A multi-input floating point number processing method executed by a computer device, the method comprising: obtaining a plurality of floating point numbers to be processed corresponding to a target task, and respectively extracting an ex...
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WO/2023/124561A1 |
A circuit, a multiplier and a circuit optimization method, related to the field of electronic devices and used for realizing the balance between the power consumption and the precision of the multiplier. The circuit comprises a digital a...
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WO/2023/125815A1 |
Embodiments of the present application provide a data processing method and apparatus and an edge computing device. The method comprises: quantizing first input data of a neural network to obtain second input data; determining first outp...
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WO/2023/129347A1 |
Techniques for training a neural network having a plurality of computational layers with associated weights and activations for computational layers in fixed-point formats include determining an optimal fractional length for weights and ...
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WO/2023/129261A1 |
The present disclosure relates to a carry chain logic system that leverages carry in and carry out signals from logic blocks to implement logic functions on programmable hardware (e.g., FPGA hardware). In particular, implementations of t...
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WO/2023/129231A1 |
Embodiments of the present disclosure include a multipurpose multiply-accumulator (MAC) array circuit comprising one or more input memories for receiving operands and a plurality of multiply-accumulator circuits each selectively coupled ...
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WO/2023/129491A1 |
Techniques for task processing based on compute element processing using control word templates are disclosed. One or more control word templates are generated for use in a two-dimensional array of compute elements. Each compute element ...
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WO/2023/124372A1 |
The present disclosure provides a floating-point number processing apparatus and method, an electronic device, a storage medium, and a chip. The floating-point number processing method comprises: acquiring a plurality of floating-point n...
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WO/2023/123617A1 |
A method for quickly calculating a three-dimensional polarization dimension, comprising: determining that an incident light field is a coherency matrix of a partially coherent schell-model beam, and decomposing the coherency matrix into ...
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WO/2023/129469A1 |
Methods, systems, and apparatuses to encode data for storage in genetic materials. For example, a computing system may segment user data into a plurality of data blocks and generate seed data characterizing a plurality of fountain code s...
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WO/2023/124371A1 |
Provided in the present disclosure are a data processing apparatus and method, and a chip, a computer device and a storage medium. The data processing apparatus comprises: a data conversion circuit, which is used for receiving data to be...
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WO/2023/129546A1 |
The technology disclosed provides a system that comprises a processor with computing units on an integrated circuit substrate. The processor is configured to map a program across multiple hardware stages with each hardware stage executin...
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WO/2023/121729A1 |
A field programmable gate array, FPGA, including a configurable interconnect fabric connecting a plurality of logic blocks, the configurable interconnect fabric and the logic blocks being configured to implement a data masking circuit co...
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WO/2023/118965A1 |
This disclosure is directed to generating a set of data elements for more secure encryption or more resilient decryption associated with generating a target set of conditional data elements. The target set of conditional data elements ma...
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WO/2023/117081A1 |
The invention is notably directed to a method of in-memory processing, the aim of which is to perform matrix-vector calculations. The method relies on a device having a crossbar array structure (15). The latter includes N input lines (15...
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WO/2023/120403A1 |
Provided is a unit that is for calculation by CGRA, that effectively uses a memory space, and that makes it possible to obtain a sparse matrix product by using less local memory. The calculation unit comprises a 3-input pipeline floating...
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WO/2023/121666A1 |
A divide circuit, according to certain embodiments disclosed herein, includes a prescaler and an iterator. The prescaler is configured to prescale a dividend by a prescaling factor to generate a prescaled dividend and to prescale a divis...
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WO/2023/108281A1 |
Cryptographic processor chips, systems and associated methods are disclosed. In one embodiment, a cryptographic processor is disclosed. The cryptographic processor includes a first cryptographic processing module to perform a first logic...
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WO/2023/113906A1 |
Methods, systems and computer program products are provided for improving performance (e.g., reducing power consumption) of a hardware accelerator (e.g., neural processor) comprising hybrid or analog multiply and accumulate (MAC) process...
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WO/2023/111625A1 |
The present disclosure relates to a multimodal system 100 for activity-based carbon footprint prediction contains a plurality of hospitals 102, a data repository unit 104, an information processing unit 106, an analyzing unit 108, a reco...
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WO/2023/109749A1 |
Examples pertaining to optimization of delivery of extended reality (XR) traffic over a wireless link in mobile communications are described. An application implemented in a user equipment (UE) communicates with a network to transmit and...
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WO/2023/111748A1 |
Methods, systems, and computer program products for automated few-shot learning techniques for artificial intelligence-based query answering systems are provided herein. A computer-implemented method includes obtaining multiple sets of q...
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WO/2023/114235A2 |
Multiply-accumulate processors within a tensor processing unit simultaneously execute, in each of a sequence of multiply-accumulate cycles, respective multiply operations using a shared input data operand and respective weighting operand...
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WO/2023/113445A1 |
The present invention relates to a floating point arithmetic technology, and is characterized by: on the basis of the result of comparing exponent parts of at least two operands being input, storing bit information of a mantissa part of ...
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WO/2023/111781A1 |
A computer-implemented method for detecting reference data standardization gaps in data sets is disclosed. The method comprises identifying at least one reference data candidate in a data set, using an index for values of the identified ...
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WO/2023/108422A1 |
An efficient zero knowledge proof accelerator. A hardware carrier having high computing power and high efficiency can be provided for zero knowledge proof calculation; and a fine-grained pipeline architecture is applied to a multi-scalar...
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WO/2023/109520A1 |
Provided are a random number generation method and apparatus based on a blockchain. The method is applied to a blockchain node, and comprises: receiving a transaction carrying a random number generation request, wherein the random number...
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WO/2023/103689A1 |
A method and device for generating a random number in a blockchain, a blockchain node, a storage medium and a computer program product, which relate to the technical field of blockchain. The method comprises: generating a first random fa...
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WO/2023/099714A1 |
The present invention relates to a method for generating, by a random number generator of a cryptographic system, an independent bit sequence from a binary candidate random stream, said random generator comprising a source of randomness ...
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WO/2023/098601A1 |
Systems and methods are provided for automated classification of data using fingerprints. The method includes: generating, by a computing device based on predetermined rules, a fingerprint of a data column in a data set to be classified,...
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WO/2023/100379A1 |
A service provider (C) accepts gm, the digital signature and a zero-knowledge proof statement (Π) of the digital signature from a job-seeker (A). The gm is encrypted data obtained by encrypting attribute information (m) by exponentiatio...
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WO/2023/100285A1 |
This addition circuit comprises: a plurality of addition input resistances (1-1) to (1-N) that each receive at one end a signal to be added; a plurality of transmission lines (2-1) to (2-N) that are connected at one end to the other ends...
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WO/2023/096689A1 |
A field programmable gate array (FPGA) including a configurable interconnect fabric connecting a plurality of logic blocks configured to implement a reciprocal function data path including: a mantissa computation stage including a mantis...
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WO/2023/096708A1 |
An apparatus is provided to access a weight vector of a layer in a sequence of layers in the DNN. The weight vector includes a first sequence of weights having different values. A bitmap is generated based on the weight vector. The bitma...
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WO/2023/092669A1 |
Disclosed in the present invention are a multi-precision accelerator based on a systolic array and a data processing method therefor. The method comprises: obtaining data precision of preset input data, wherein the data precision is used...
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WO/2023/093128A1 |
An operation processing method and system, a main processor, and a coprocessor. The method comprises: a main processor first obtains an operation instruction to be processed, and determines whether the operation instruction is a coproces...
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WO/2023/095979A1 |
Disclosed are an apparatus and a method for judging infringing products. The apparatus for judging infringing products may comprise: a communication unit configured to communicate with a mobile terminal that images a target product; and ...
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WO/2023/095419A1 |
The present invention realizes four arithmetic operations of integer-wise TFHE. A cipher text is a fully homomorphic cipher text for which a prescribed arithmetic operation can be performed on integers without decoding, and which include...
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WO/2023/090502A1 |
The present invention relates to a method and an apparatus for calculating a variance matrix product on the basis of frame quantization, and provides a method and an apparatus for calculating a variance matrix product in a plurality of o...
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WO/2023/089930A1 |
[Problem] To provide an information processing method which further minimizes quantum bit exponential measurement frequency. [Solution] One aspect of the present invention provides an information processing method. The information proces...
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WO/2023/091258A1 |
There is disclosed a system and method of performing an artificial intelligence (AI) inference, including: programming an AI accelerator circuit to solve an AI problem with a plurality of layer-specific register file (RF) size allocation...
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WO/2023/091174A1 |
A method of automatic troubleshooting, includes determining that a first parameter was degraded; identifying at least one first process corresponding to the first parameter; determining whether the at least one first process was operatin...
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