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Matches 451 - 500 out of 855,240

Document Document Title
WO/2018/044510A1
Apparatuses and methods are disclosed that include two transistor-one capacitor memory and for accessing such memory. An example apparatus includes a capacitor coupled to first and second selection components. The apparatus further inclu...  
WO/2018/040576A1
A video editing method, device, terminal, and computer storage medium. The editing method comprises: determining a location to be edited corresponding to an audio to be edited (S101); acquiring an adjusted audio corresponding to the loca...  
WO/2018/041885A1
The invention relates to a device for controlling the refresh cycles of data stored in a non-volatile memory. The device comprises a temperature sensor capable of measuring the temperature of at least one non-volatile memory and of deliv...  
WO/2018/044755A1
Fuse state sensing circuits, devices and methods. In some embodiments, a fuse state sensing circuit can include an enable block configured to enable a flow of a fuse current resulting from a supply voltage to a fuse element upon receipt ...  
WO/2018/044487A8
Apparatuses and methods are disclosed that include ferroelectric memory and for accessing ferroelectric memory. An example method includes increasing a voltage of a first cell plate of a capacitor to change the voltage of a second cell p...  
WO/2018/043593A1
Provided is a photosensitive composition for hologram recording, with which it is possible to further improve diffraction properties. The composition includes at least: two or more types of phopolymerizable monomers; a photopolymerizatio...  
WO/2018/042285A1
To provide a novel semiconductor device or display device. The semiconductor device includes a decoder circuit, an amplifier circuit, and an arithmetic circuit. The amplifier circuit includes a first amplifier and a second amplifier. One...  
WO/2018/044486A1
Apparatuses and methods are disclosed that include ferroelectric memory and for operating ferroelectric memory. An example apparatus includes a capacitor having a first plate, a second plate, and a ferroelectric dielectric material. The ...  
WO/2018/044562A2
One embodiment includes a superconducting gate memory circuit. The circuit includes a Josephson D-gate circuit configured to set a digital state as one of a first data state and a second data state in response to a write enable single fl...  
WO/2018/043680A1
Provided is a sputtering target which enables decrease in the heat treatment temperature for ordering an Fe-Pt magnetic phase, and which is suppressed in generation of particles during the sputtering. A non-magnetic material-dispersed sp...  
WO/2018/044487A1
Apparatuses and methods are disclosed that include ferroelectric memory and for accessing ferroelectric memory. An example method includes increasing a voltage of a first cell plate of a capacitor to change the voltage of a second cell p...  
WO/2018/044485A1
Apparatuses and methods are disclosed that include ferroelectric memory cells. An example ferroelectric memory cell includes two transistors and two capacitors. Another example ferroelectric memory cell includes three transistors and two...  
WO/2018/044562A3
One embodiment includes a superconducting gate memory circuit. The circuit includes a Josephson D-gate circuit configured to set a digital state as one of a first data state and a second data state in response to a write enable single fl...  
WO/2018/044368A1
Apparatuses, systems, methods, and computer program products are disclosed for state-dependent read compensation. A set of non-volatile storage cells 200 comprises a plurality of word lines 260, 262, 264, 266, 506, 508, 510. A controller...  
WO/2018/044329A1
Systems, methods, and non-transitory computer-readable media can acquire a first selection to identify a subset of media content items out of a set of media content items. A second selection to identify a mood out of a set of moods can b...  
WO/2018/044391A1
First data is read out of a core storage array of a memory component over a first time interval constrained by data output bandwidth of the core storage array. After read out from the core storage array, the first data is output from the...  
WO/2018/044479A1
A sense amplifier construction comprises a first n-type transistor and a second n-type transistor above the first n-type transistor. A third p-type transistor is included and a fourth p-type transistor is above the third p-type transisto...  
WO/2018/042175A1
Systems and methods for superimposing the human elements of video generated by computing devices, wherein a first user device (20) and second user device (20) capture and transmit video (212, 214) to a central server (30) which analyzes ...  
WO/2018/043903A1
Disclosed are a transmitter which requires only a low cost and a small area and can eliminate switching noise, and a data transmission method therefor. The transmitter comprises: an encoder for converting two-level input data (1 and 0) i...  
WO/2018/044815A1
A ferroelectric memory and a method for operating a ferroelectric memory are disclosed. The ferroelectric memory includes a ferroelectric memory cell having a ferroelectric capacitor characterized by a maximum remanent charge, Qmax. A wr...  
WO/2018/040711A1
A shift register and a driving method thereof, a gate driving circuit and a display device. The shift register comprises: an input unit (11), configured to provide an input signal to a first node (N1); a pull-up unit (12), configured to ...  
WO/2018/043425A1
A semiconductor device having a plurality of memory cells (MC1, MC2), the semiconductor device being such that each of the plurality of memory cells (MC1, MC2) respectively has: a memory transistor (10M) having an oxide semiconductor lay...  
WO/2018/044384A1
A Data Storage Device (DSD) enclosure includes a chassis and at least one backplane mounted in the chassis. According to one aspect, each backplane includes a row of DSD slots and a switch slot located in a middle portion of the row of D...  
WO/2018/041557A1
A differential gain-stage circuit (10) comprises a positive and a negative input terminal (25, 26), a first capacitor (11) with a first and a second electrode (12, 13), a second capacitor (14) with a first and a second electrode (15, 16)...  
WO/2018/044503A1
The disclosure generally relates to a memory power reduction scheme that can flexibly transition memory blocks among different power states to reduce power consumption (especially with respect to leakage power) in a manner that balances ...  
WO/2018/044458A1
Some embodiments include a memory array having a series of bitlines. Each of the bitlines has a first comparative bitline component and a second comparative bitline component. The bitlines define columns of the memory array. Memory cells...  
WO/2018/040969A1
The present invention relates to the technical field of flash memory, and provides a method and device for improving reliability of a NAND flash memory. The method comprises the following steps: upon receiving an interrupt signal, a NAND...  
WO/2018/042814A1
The present invention makes it possible to obtain a highly accurate signal quality assessment value capable of having a high correlation with the error rate for a reproduction signal from a high-density recording medium. For this purpose...  
WO/2018/045214A1
In some example implementations, there may be provided methods for beamforming calibration of active electronically steered arrays (AESA). In some implementations, one or more adders may generate a phase offset by adding phase calibratio...  
WO/2018/044567A1
Apparatuses and methods for temperature and process corner sensitive control of power gated domains are described. An example apparatus includes an internal circuit; a power supply line; and a power gating control circuit which responds,...  
WO/2018/038802A2
Adaptive power regulation methods and systems are disclosed. In one aspect, one or more process sensors for memory elements are provided, which report information relating to inherent speed characteristics of sub-elements within the memo...  
WO/2018/038783A1
Systems and methods for performing a partial block erase operation on a portion of a memory array are described. The memory array may include a plurality of vertical NAND strings in which a first set of the plurality of vertical NAND str...  
WO/2018/038802A3
Adaptive power regulation methods and systems are disclosed. In one aspect, one or more process sensors for memory elements are provided, which report information relating to inherent speed characteristics of sub-elements within the memo...  
WO/2018/037155A1
An apparatus configured to, in respect of a video provided to a user and wherein a plurality of comments are displayed such that they scroll across the video, based on the comments and one or more comment filtering rules, provide for com...  
WO/2018/037777A1
This magnetoresistive element 10 is obtained by laminating a lower electrode 31, a first base layer 21A formed of a non-magnetic material, a storage layer 22 having perpendicular magnetic anisotropy, an intermediate layer 23, a magnetiza...  
WO/2018/039059A1
A computer-implemented method is described for automatically digitally transforming and editing video files to produce a finished video presentation. The method includes the steps of recording or receiving from a user a master video, rec...  
WO/2018/038849A1
A magnetic random access memory (MRAM) array including several bit cells is described. Each of the bit cells includes a perpendicular magnetic tunnel junction (pMTJ) -a magnetic tunnel junction with perpendicular anisotropy- including a ...  
WO/2018/038835A1
Apparatuses and methods related to adjusting a delay of a command signal path are disclosed. An example apparatus includes: a timing circuit that includes a divider circuit that receives a first clock signal having a first frequency and ...  
WO/2018/037828A1
Provided is a semiconductor device comprising an internal nonvolatile memory element and an input terminal (A) for receiving an external test control signal input and a input signal for writing/erasing voltage, wherein the semiconductor ...  
WO/2018/039156A1
In described examples, error correction code (ECC) hardware includes write generation (Gen) ECC logic (115b) and a check ECC block (120b) coupled to an ECC output of a memory circuit (130) with read Gen ECC logic (120b1) coupled to an XO...  
WO/2018/038784A1
Techniques are provided for preventing program disturb when programming a memory device. Hot electron injection program disturb is prevented or reduced. Voltage boosting of the NAND channel of a program inhibited NAND string may be contr...  
WO/2018/039215A1
Methods, systems, and apparatuses for full bias sensing in a memory array are described. Various embodiments of an access operation of a cell in a array may be timed to allow residual charge of a middle electrode between the cell and a s...  
WO/2018/038850A1
Systems and apparatuses for memory devices utilizing a continuous self-refresh timer are provided. An example apparatus includes a self-refresh timer configured to generate a signal periodically. A period of the signal may be based on a ...  
WO/2018/034752A2
A voltage regulator package includes a voltage regulator module that outputs a voltage signal of a particular voltage level through an output terminal is provided. The voltage regulator module may be switched on according to a periodic s...  
WO/2018/034825A1
In one embodiment of the present invention, one row is selected and two columns are selected for a read or programming operation, such that twice as many flash memory cells can be read from or programmed in a single operation compared to...  
WO/2018/035288A1
A semiconductor device may include a substrate, active circuitry on the substrate and including differential transistor pairs, and threshold voltage test circuitry on the substrate. The threshold voltage test circuitry may include a pair...  
WO/2018/034371A1
According to an embodiment, disclosed is a computer program stored in a computer-readable recording medium in order to execute a motion image processing method comprising the steps of: by using a computer including a storage medium, an o...  
WO/2018/034752A3
A voltage regulator package includes a voltage regulator module that outputs a voltage signal of a particular voltage level through an output terminal is provided. The voltage regulator module may be switched on according to a periodic s...  
WO/2018/032327A1
A current sampling and holding circuit and a signal acquisition system. The current sampling and holding circuit comprises: a cancellation circuit (21) connected in series between a VDD end and an amperometric sensor (11), and outputting...  
WO/2018/032315A1
An anti-vibration heat dissipation bracket for a hard disk drive, comprising a cuboid mounting bracket (1). The bottom of the mounting bracket (1) is provided with an elastic cushioning member (10), and the inner wall of the mounting bra...  

Matches 451 - 500 out of 855,240