Login| Sign Up| Help| Contact|

Patent Searching and Data


Matches 451 - 500 out of 861,271

Document Document Title
WO/2020/073300A1
Examples described herein can be used to calibrate resistances provided by pull-up and pull-down circuits in an output driver circuit. A first reference voltage can be determined and applied to set a resistance level of a pull-up circuit...  
WO/2020/075957A1
An artificial neural network computation acceleration apparatus for distributed processing, according to the present invention, can comprise: an external main memory for storing input data and synapse weights for input neurons; an intern...  
WO/2020/076560A1
A variety of applications can include apparatus and/or methods to preemptively detect defect prone memory blocks in a memory device and handle these memory blocks before they fail and trigger a data loss event. Metrics based on memory op...  
WO/2020/074996A1
Zero-shifting techniques in analog crosspoint arrays are provided. In one aspect, an analog array-based vector-matrix multiplication includes: a weight array connected to a reference array, each including a crossbar array (802, 804) havi...  
WO/2020/076586A1
Methods, systems, and devices for operating memory cell(s) using adapting the current on a channel are described. A current on a channel may be adapted during a transition period between signaling a first logic value over the channel and...  
WO/2020/074718A1
The invention relates to a method for producing a ceramic material having permeability gradients that can be set locally, to the use of said ceramic material in a coating-method material processing method, and to the use of said coating-...  
WO/2020/075658A1
With recognition applications such as for recognizing handwritten text, it is often not possible to find a complete match. Such cases necessitate permitting a certain extent of mismatch, determining words to be seen as "matching to a cer...  
WO/2020/073995A1
Disclosed is a magnetic random access memory, comprising: a substrate (10); multiple driver sets sequentially arranged in the direction away from the substrate (10) and on the surface of the substrate (10), wherein each driver set compri...  
WO/2020/076718A1
A buffer chip includes a first set of input/output (I/O) pins a second set of I/O pins, and is configurable to operate in one of a first mode or a second mode. The first set of I/O pins and the second set of I/O pins are configured to co...  
WO/2020/070655A1
Exemplary embodiments of the present disclosure are directed towards a system for creating a personalized story, comprising: a first end-user device 102 and a second end-user device 104 configured to establish two way wireless-communicat...  
WO/2020/072389A1
Apparatuses and methods for input receiver circuits and receiver masks for electronic memory are disclosed. Embodiments of the disclosure include memory receiver masks having shapes other than rectangular shapes. For example, a receiver ...  
WO/2020/071046A1
This playback device comprises: a calculation unit for obtaining a first differential signal a and a second differential signal b orthogonal in phase to the first differential signal a; and a phase correction unit to which the first diff...  
WO/2019/190684A9
Methods and apparatus for a host to communicate with memory modules via an interposer are presented. An apparatus includes the interposer and a plurality of memory module sockets attached to the interposer. The interposer includes at lea...  
WO/2019/147522A3
A synapse circuit of a non-volatile neural network. The synapse includes: an input signal line (265); a reference signal line (265); an output line (266), and a cell (2032) for generating the output signal (203). The cell (2032) includes...  
WO/2020/072885A1
Apparatus, systems, and methods for resistive switching are generally described.  
WO/2020/072242A1
Methods, systems, and devices for dynamically configuring transmission lines of a bus between two electronic devices (e.g., a controller and memory device) are described. A first device may determine a quantity of bits (e.g., data bits, ...  
WO/2020/072738A1
Various client devices include displays and one or more image capture devices configured to capture video data. Different users of an online system may authorize client devices to exchange information captured by their respective image c...  
WO/2020/070801A1
The purpose of the present invention is to, when displaying thumbnails of wide-angle panoramic images, improve the visibility by displaying thumbnail images, in which distortion, inclination, and the like have been reduced, in a scrollab...  
WO/2020/070830A1
According to the present invention, a memory cell (MC1) of a 2-port static random-access memory (SRAM) is provided with transistors (TP1, TP2, TN1-TN6). Gate wirings (21-25) are disposed so as to extend in the X-direction and arranged in...  
WO/2020/072056A1
The system and method for phase noise reduction and/or vibration reduction in assemblies using piezoelectric passive resonant shunt damping or active vibration cancellation/compensation techniques. In some cases a circuit card or similar...  
WO/2020/063119A1
Disclosed are a gate drive unit circuit, a gate drive circuit and a method for driving the gate drive unit circuit. The gate drive unit circuit comprises an input sub-circuit (1) and an output sub-circuit (2). The input sub-circuit (1) i...  
WO/2020/062230A1
Provided are a thin-film transistor (T1), a gate driver on array circuit (1), and a display apparatus (100) having the gate driver on array circuit (1), wherein the gate driver on array circuit (1) comprises several thin-film transistors...  
WO/2020/068323A1
An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memor...  
WO/2020/068588A1
A method and architecture for mitigating memory imprinting in electronic system volatile memory. At system power-up, a bus mode register control determines whether to operate the current power cycle in normal mode or inversion mode, with...  
WO/2020/066660A1
This information processing device sets an upper limit number of characters according to the time length of a video, receives input of characters representing a voice to be added to the video, and performs an alarm notification operation...  
WO/2020/066389A1
This recording device is provided with: a generation unit for generating a hierarchy of groups into which respective sets of data are classified from information regarding multiple sets of data to be recorded; and a control unit for perf...  
WO/2020/068239A1
An apparatus is provided which comprises: a first power supply rail to provide a first power supply; second and third power supply rails to provide second and third power supplies, respectively, wherein a voltage level of the first power...  
WO/2020/068435A1
A ceramic waveguide includes: a doped metal oxide ceramic core layer; and at least one cladding layer comprising the metal oxide surrounding the core layer, such that the core layer includes an erbium dopant and at least one rare earth m...  
WO/2020/068591A1
A method and architecture for mitigating configuration memory imprinting in programmable logic devices. At power-up, a configuration memory inversion control determines whether to operate the current power cycle in normal mode or inversi...  
WO/2020/068307A1
Compute-in memory circuits and techniques are described. In one example, a memory device includes an array of memory cells, the array including multiple sub-arrays. Each of the sub-arrays receives a different voltage. The memory device a...  
WO/2020/068236A1
Techniques and mechanisms for a memory device to perform in-memory computing based on a logic state which is detected with a voltage-controlled oscillator (VCO). In an embodiment, a VCO circuit of the memory device receives from a memory...  
WO/2020/069234A1
Medication-receivers for safely and securely receiving the temporary delivery of medications are discussed. Such medication-receivers may be removably attached to exterior doors or structures such as, but not limited to, residences and/o...  
WO/2020/066826A1
This sputtering target has (100-x)MgO-xCuO(0
WO/2020/068354A1
The present disclosure includes apparatuses and methods related to data transfer in memory. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports and a second number of memory dev...  
WO/2020/062501A1
A GOA circuit structure. The GOA circuit structure comprises a pull-up control unit (2), a pull-up unit (3), a downloading unit (4), a pull-down unit (5), a pull-down holding unit (6) and an additional thin film transistor (T23). By mean...  
WO/2020/066114A1
The present invention provides a sputtering target which contains Ru and boron. A sputtering target which contains Ru as a main component, while containing a composite oxide that contains boron and has a higher melting point than B2O3.  
WO/2020/068322A1
Embodiments include apparatuses, methods, and systems associated with save-restore circuitry including metal-ferroelectric-metal (MFM) devices. The save-restore circuitry may be coupled to a bit node and/or bit bar node of a pair of cros...  
WO/2020/068365A1
The present disclosure includes apparatuses and methods related to direct data transfer in memory. An example apparatus can include a first number of memory devices coupled to a host via a respective first number of ports and a second nu...  
WO/2020/068580A1
A computer system displays a representation of a field of view of one or more cameras that is updated with changes in the field of view. In response to a request to add an annotation, the representation of the field of view of the camera...  
WO/2020/063152A1
A music playing control method and apparatus, and a household appliance, a server and a medium for enabling household appliances to play corresponding music, the music playing control method comprising: a household appliance determining ...  
WO/2020/068240A1
An apparatus is provided which comprises: a first circuitry to sample a first input signal to generate a first sampled signal, and to sample a second input signal to generate a second sampled signal, wherein the first input signal compri...  
WO/2020/063413A1
A chip (1) and a chip test system,the chip (1) includes a decoding module (11) and a test mode control module (12), and decodes an input signal to determine whether the input signal is a pre-activation signal or not. If the input signal ...  
WO/2020/063827A1
An electronic device includes a plurality of semiconductor dies (A-D) stacked vertically over each other and a power supply system (402, 600). The semiconductor dies (A-D) are stacked over the power supply system (402, 600). The power su...  
WO/2020/061892A1
A semiconductor device includes a string of transistors stacked along a vertical direction above a substrate of the semiconductor device. The string can include a first substring, a channel connector disposed above the first substring, a...  
WO/2020/062027A1
A scanning drive unit (10), a scanning drive circuit (100), an array substrate (AY), and a display device. A pull-up control unit (11) in the scanning drive unit (10) receives a starting voltage (STV) to control a pull-up node (PU) to be...  
WO/2020/061617A1
An optical data storage material comprising graphene oxide (GO) configured to be photo-chemically reduced on selected areas for optical data storage, nanoparticles configured to photo-chemically reduce the GO on the selected areas by opt...  
WO/2020/068042A1
A 3D cross-bar array of non-volatile resistive memory devices includes an array of pillar electrodes, an array of word lines, a plurality of memristor cells, and a plurality of insulation walls. The array of pillar electrodes is arranged...  
WO/2020/062797A1
A data storage method and a memory. The method comprises: establishing an ECC table, and recording a first ECC value of a data source page and a second ECC value of a data target page (S101); updating the ECC table (S102); loading the EC...  
WO/2020/063720A1
An electronic device and a semiconductor package structure are provided. The electronic device includes a plurality of semiconductor dies stacked vertically over each other and a power supply system. The plurality of semiconductor dies a...  
WO/2020/058050A1
There is provided a cryptographic key determination device (13) for determining one or more cryptographic keys in a cryptographic device (1), the cryptographic device (1) being configured to execute one or more test programs, the cryptog...  

Matches 451 - 500 out of 861,271