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Patent Searching and Data


Matches 451 - 500 out of 857,375

Document Document Title
WO/2018/223837A1
Disclosed are a music playing method and a related product. The method comprises: acquiring user habit data for music playing; determining a playing moment according to the user habit data; acquiring a user mood parameter and/or an envir...  
WO/2018/224726A1
A method including capturing, by a low latency monitoring device (432), content visualized in video rendering mode, capturing at least one parameter modified (474) in the video rendering mode, determining at least one correction update m...  
WO/2018/223834A1
A shift register unit and a driving method thereof, a gate driving circuit, and a display device in the technical field of displays. The shift register unit comprises a control subcircuit (20) and a noise reduction subcircuit (30). When ...  
WO/2018/226692A1
A method and system for tracking movements of objects in a sports activity are provided. The method includes matching video captured by at least one camera with sensory data captured by each of a plurality of tags, wherein each of the at...  
WO/2018/225725A1
Provided is a glass for an information recording medium substrate, said glass being an an amorphous glass which has, in terms of mol%, an SiO2 content of 55-68%, a B2O3 content of 0-5%, an Al2O3 content of 1-14%, an MgO content of 8-23%,...  
WO/2018/224811A1
The present techniques generally relate to methods, systems and devices for operation of memory device. In one aspect, bit positions of a portion of a memory array may be placed in a first value state. Values to be written to the bit pos...  
WO/2018/224911A1
The present invention provides a semiconductor device having a large storage capacity per unit area. Specifically provided is a semiconductor device having memory cells, the memory cells being provided with: a first conductor; a first in...  
WO/2018/226586A1
A method includes generating a bias signal from a first device, and applying the bias signal to a second device, the first device having (a) a superconducting trace and (b) a superconducting quantum interference device (SQUID), in which ...  
WO/2018/225386A1
An optical device according to an embodiment of the present disclosure is a device that performs at least one of writing and deleting of information on a reversible recording medium. The optical device is provided with: a plurality of la...  
WO/2018/224929A1
A magnetic tunnel junction (MTJ) storage element includes a reference layer, a tunnel barrier and a free layer on an opposite side of the tunnel barrier layer from the reference layer. The reference layer has a fixed magnetization direct...  
WO/2018/220356A1
The present techniques generally relate to fabrication of correlated electron materials (CEMs) devices used, for example, to read from a resistive memory element or to write to a resistive memory element. In embodiments, by limiting curr...  
WO/2018/219886A1
The proposed invention relates to a method for situation-dependent storage of data of a system, in which data of the system is detected, is amalgamated in at least one data block (9, 9a) and is stored in a volatile memory, and in which, ...  
WO/2018/220220A1
The present invention relates to an electroless nickel alloy plating bath comprising nickel ions; further reducible metal ions selected from the group consisting of molybdenum ions, rhenium ions, tungsten ions, and mixtures thereof; at l...  
WO/2018/222582A1
A magnetoresistive dynamic random access memory (MDRAM) cell is described. A hybrid memory cell includes a first transistor having a first source/drain electrode coupled to a charge storage node and a gate of a second transistor. A first...  
WO/2018/218531A1
An EEPROM programming system and an EEPROM programming method. The EEPROM programming system (1) comprises an upper computer (11), an EEPROM programmer (12) and a chip programming seat (13). The upper computer (11) is used for receiving ...  
WO/2018/221293A1
Provided is a configuration that converts MMT format data to MPEG-2TSV format data and records the result to a medium, and allows copy control that complies with original copy control information. MMT format data for which copy control i...  
WO/2018/218659A1
Provided are a method and device for a page being read to play back background sound, comprising: when a page being read receives a trigger instruction for playing back background sound, calling a corresponding background sound access in...  
WO/2018/218886A1
A shift register, a gate driving circuit and a display device. The shift register comprises: a first shift register unit, a second shift register unit, a pull-down control subcircuit (20) and a pull-down subcircuit (30); the first shift ...  
WO/2018/222586A1
Aspects for reducing or avoiding mechanical stress in static random access memory (SRAM) strap cells are disclosed herein. An exemplary SRAM strap cell includes a P-type doped well (Pwell) tap electrically coupled to a first supply rail ...  
WO/2018/218731A1
A potential transfer circuit (103, 300), a driving method therefor, and a display panel thereof. The potential transfer circuit (103, 300) comprises: a core circuit (310) configured to provide an image signal; a control unit (320) config...  
WO/2018/220846A1
The present invention provides a semiconductor module capable of improving a bandwidth between a logic chip and a RAM. According to the present invention, a semiconductor module 1 is provided with: a logic chip; a pair of RAM units 30 ea...  
WO/2018/221292A1
Provided is a configuration that allows reproduction permission age information corresponding to recorded content of a medium to be recorded, and allows reproduction control that is based on age to be performed at the time of reproductio...  
WO/2018/222853A1
Nucleic acid memory strands encoding digital data using a sequence of homopolymer tracts of repeated nucleotides provides a cheaper and faster alternative to conventional digital DNA storage techniques. The use of homopolymer tracts allo...  
WO/2018/220471A1
Provided is a low-power-consumption storage device. The storage device has first through third transistors, first wiring, second wiring, memory cells, and a capacitive element. The first through third transistors are serially connected. ...  
WO/2018/220849A1
Provided is a semiconductor module which enables a memory bandwidth to be widened, and which enables data transfer efficiency to be improved by reducing power consumption. A semiconductor module 1 comprises: an interposer 10; and a proce...  
WO/2018/221655A1
This recording control device (10) is configured so as to to control the recording of data in a recording unit (14, 24, 34, 44, 54), and is provided with: a data acquisition unit (17); a data storage unit (S110, S140, S190, S670); and a ...  
WO/2018/218689A1
The present utility model is applicable to the field of audio recording. Provided is a simulation apparatus and a recording device, comprising a first simulation portion which comprises a first facial structure and a first ear structure,...  
WO/2018/221044A1
A semiconductor device of the present disclosure is provided with: a plurality of first selection lines that are provided in a region, which is outside a region of a plurality of opening areas and is in a first area, on a first selection...  
WO/2018/222686A1
Disclosed are systems, methods, and computer-readable storage media to provide voice driven dynamic menus. One aspect disclosed is a method including receiving, by an electronic device, video data and audio data, displaying, by the elect...  
WO/2018/216499A1
The present technology relates to a data processing device, a data processing method, a program, and data processing system for enabling meaningful audio to be recorded for intermittently-captured images. The data processing device is pr...  
WO/2018/216542A1
The present invention implements a gate driver (scanning signal line driving circuit) having higher reliability than conventional ones. A shift register constituting the gate driver operates on the basis of gate clock signals of three or...  
WO/2018/215715A1
The invention relates to a memory device comprising one or more banks (126), each bank comprising a plurality of memory rows, the memory device comprising moreover: logic for detecting triggering of the Row Hammer (123) and configured to...  
WO/2018/217632A1
A bipartite memristive network and method of teaching such a network is described herein. In one example case, the memristive network can include a number of nanofibers, wherein each nanofiber comprises a metallic core and a memristive s...  
WO/2018/217582A3
Apparatuses and methods for detecting refresh starvation at a memory. An example apparatus may include a plurality of memory cells, and a control circuit configured to monitor refresh request commands and to perform an action that preven...  
WO/2018/217744A1
A memory device includes a memory array including a plurality of memory cells; and a controller coupled to the memory array, the controller configured to iteratively: determine a first error rate corresponding to a current processing lev...  
WO/2018/217813A3
Apparatus and method are described for trimming parameters of analog circuits. The apparatus includes trim result registers for storing trim results for adjusting parameters of analog circuits, respectively; a memory device configured to...  
WO/2018/215804A1
A tunable CMOS circuit comprising a CMOS element and a tunable load. The CMOS element is configured to receive an analogue input signal. The tunable load is connected to the CMOS element and configured to set a switch point of the CMOS e...  
WO/2018/214613A1
Disclosed are a shift register circuit and a drive method therefor, and a gate drive circuit and a display panel. The shift register circuit comprises: an input circuit (1), a first control circuit (2), a second control circuit (3), a th...  
WO/2018/217737A2
A memory system includes a memory array including a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: determine background records associated with a programming step, wherein the backg...  
WO/2018/217425A1
A method and apparatus of integrating memory stacks includes providing a first memory die of a first memory technology and a second memory die of a second memory technology. A first logic die is in communication with the first memory die...  
WO/2018/217737A3
A memory system includes a memory array including a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: determine background records associated with a programming step, wherein the backg...  
WO/2018/217899A1
An example system (600) includes a non-volatile memory (606) including a binary section (615), a first page table (610) and a second page table (612). The system (600) also has a volatile memory (616) and a processor (604) coupled to the...  
WO/2018/217740A1
A memory system includes a memory array including a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: determine a target profile including distribution targets, wherein each of the dis...  
WO/2018/217311A1
Method and Apparatuses for transmitting and receiving commands for a semiconductor device are described. An example apparatus includes: a memory device including a plurality of banks, each bank including a plurality of memory cells; and ...  
WO/2018/216424A1
Provided is a configuration that allows rapid confirmation of whether medium-recorded MMT format audio data is MPEG4 AAC LC audio data or MPEG4 ALS audio data. A clip information file in which audio identification information is recorded...  
WO/2018/216365A1
A semiconductor device according to the present disclosure comprises: a plurality of first selection lines provided in a first region, and extending in a first direction and aligned in a second direction; a plurality of second selection ...  
WO/2018/217467A1
An integrated circuit comprising a physical array of logic tiles, wherein each logic tile includes a perimeter and a plurality of external I/O disposed in a layout on the perimeter of the logic tile wherein the layout of the external I/O...  
WO/2018/217813A2
Apparatus and method are described for trimming parameters of analog circuits. The apparatus includes trim result registers for storing trim results for adjusting parameters of analog circuits, respectively; a memory device configured to...  
WO/2018/211378A1
The present invention provides a novel semiconductor device. Alternatively, the present invention provides a storage device that is capable of holding more multivalue information. One among the source and the drain of a write transistor ...  
WO/2018/213073A3
The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an internal bus configured to transfer data between the plurality of banks and an...  

Matches 451 - 500 out of 857,375