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Patent Searching and Data


Matches 451 - 500 out of 854,492

Document Document Title
WO/2017/205029A1
Systems and methods for providing variable trick-play mode playback of media content in accordance with embodiments of the invention are disclosed. A playback device stores images of the media content associated with presentation times a...  
WO/2017/204977A1
One embodiment describes a reciprocal quantum logic (RQL) sense amplifier system. The system includes an input stage configured to amplify a sense current received at an input. The system also includes a detection stage configured to tri...  
WO/2017/204876A1
A system and method of writing data to a memory block includes receiving user data in a memory controller to be written to the memory block. The user data is first written to a buffer. A screening pattern is written to at least one scree...  
WO/2017/202617A1
A system (100) and method for zooming of a video recording are provided. The system is configured to detect, track and select object(s) in a first view (110) of the video recording. The system further is configured to perform at least on...  
WO/2017/204957A1
An apparatus is provided which comprises: a select line; a select transistor coupled to a resistive memory element and to the select line; a word-line coupled to a gate terminal of the select transistor; and a current mirror operable to ...  
WO/2017/204679A1
Claimed is a method for automatically creating video content taking into account the preferences of a user. The invention relates to systems for automatically editing digital films from material filmed by a user, which enable the user to...  
WO/2017/204224A1
The present invention provides: a glass for use in magnetic recording media, which enables reduction of heat cracking arising from a temperature distribution in a glass substrate during a process for heating the glass substrate over 600...  
WO/2017/204871A1
Techniques are provided for reducing program disturb and short term data retention loss. Program disturb becomes worse for the drain-side memory cells at higher temperatures, while data retention generally does not become worse at higher...  
WO/2017/204158A1
Provided is a sputtering target material which has an improved strength without using pure Ta, can be prevented from forming cracks or particles during sputtering, and can be prevented from having a non-uniform composition in a sputtered...  
WO/2017/204143A1
The present invention provides: a glass for data storage medium substrates, which is easy to recognize in a production process and which enables shards of the glass caused by cracking or chipping to be easily found; a glass substrate for...  
WO/2017/204980A1
Methods of operating a memory include developing first and second voltage levels in first and second semiconductor materials, respectively, forming channel regions for first and second groupings of memory cells, respectively, of a string...  
WO/2017/204001A1
The present invention pertains to a disc-like recording medium, a recording device, a recording method, a reproduction device, and a reproduction method that enable recording of data at high density and enable robust reproduction of data...  
WO/2017/202619A1
A user interface, UI, (100) for zooming of a video recording by a device comprising a screen, the UI being configured to: register a marking by a user on the screen of an object in the video recording on the screen, associate the marking...  
WO/2017/199677A1
A semiconductor circuit includes first (IV1, IV3) and second (IV2, IV4) circuits, first (31) and second (32) transistors, a first storage element (35), and a driver (22, 23, 52, 53). The first (IV1, IV3) and second (IV2, IV4) circuits, r...  
WO/2017/199743A1
The present invention enables recording, in an MPEG-2 TS format, and playback of a high frame rate image based on an MMT format. MPEG-2 TS format data in which a main stream and a substream based on the MMT format are stored in setting p...  
WO/2017/200710A1
A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory cells includes a column bit line, a first column control gate line for even row c...  
WO/2017/199430A1
A disk transfer device (1) is provided with: a plurality of disk drives (30); a housing unit (20) that holds a plurality of disks (50) in a stacked state such that the disks are not in contact with each other; and a transfer unit (10), w...  
WO/2017/198737A1
An apparatus (1) for processing a multichannel audio signal (100) is provided, comprising a plurality of channel signals (x1, x2). The apparatus performs a time scale modulation of the multichannel audio signal (100) and comprises a phas...  
WO/2017/201339A1
A system and methods for manufacturing devices such as flexures using process coupons are described. The method includes performing a test on at least one feature of a coupon, the coupon is included on an assembly sheet used in manufactu...  
WO/2017/200888A1
The present invention relates to a flash memory cell with only four terminals and decoder circuitry for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the pr...  
WO/2017/200657A1
Systems and methods relate to memory operations in a memory array. A compare operation is performed using a sense amplifier. True and complement versions of a search bit are compared with true and complement versions of a data bit stored...  
WO/2017/197917A1
A shift register and an operation method therefor. The shift register comprises: an input module (31), connected to an input terminal (INPUT) and a pull-up node (PU) of the shift register; a reset module (32), connected to a reset signal...  
WO/2017/196369A1
An integrated circuit device can include a plurality of SRAM cells, each including a pair of latching devices having controllable current paths connected to first and second latching nodes, and control terminals cross-coupled between the...  
WO/2017/196424A1
A memory system includes blocks (or other groupings) of memory cells including data memory cells and dummy memory cells. In order to mitigate program disturb or other issues, the memory system applies a gate voltage based on temperature ...  
WO/2017/196423A1
A system for using bad blocks in a memory system is proposed. The system includes accessing an identification of a plurality of bad blocks and corresponding error codes which, for example, were generated during a manufacturing test and s...  
WO/2017/197108A1
A semiconductor device may include a plurality of memory cells, and at least one peripheral circuit coupled to the plurality of memory cells and comprising a superlattice. The superlattice may include a plurality of stacked groups of lay...  
WO/2017/193775A1
A shift register unit, a gate drive circuit and a drive method therefor, and a display device. The shift register unit comprises a first control unit (10), a second control unit (20), a first pull-up unit (30), a second pull-up unit (40)...  
WO/2017/197030A1
A suspension having a DSA structure on a gimbaled flexure includes a loadbeam and a flexure attached to the loadbeam. The flexure includes a metal layer with a pair of spring arms, a tongue including a slider mounting surface, and a pair...  
WO/2017/195865A1
This magnetic recording medium comprises an elongated substrate, and a strengthening layer and a carbon thin film that are provided on one surface of the substrate.  
WO/2017/194335A3
A programming device (110) arranged to obtain and store a random bit string in a memory device (100), the memory device (100) comprising multiple one-time programmable memory cells (122), a memory cell having a programmed state and a not...  
WO/2017/195866A1
A first embodiment of this magnetic recording medium comprises an elongated substrate that has a first surface and a second surface, a first strengthening layer that is provided on the first surface, a second strengthening layer that is ...  
WO/2017/197235A2
A quantum memory system includes a doped polycrystalline ceramic optical device, a magnetic field generation unit, and one or more pump lasers. The doped polycrystalline ceramic optical device is positioned within a magnetic field of the...  
WO/2017/195874A1
Provided are the following: a memory device that has a compact circuit structure and can flexibly support the number of dimensions of reference data when retrieving data similar to search data; and a memory system. Provided is the memory...  
WO/2017/197235A3
A quantum memory system includes a doped polycrystalline ceramic optical device, a magnetic field generation unit, and one or more pump lasers. The doped polycrystalline ceramic optical device is positioned within a magnetic field of the...  
WO/2017/194335A2
A programming device (110) arranged to obtain and store a random bit string in a memory device (100), the memory device (100) comprising multiple one-time programmable memory cells (122), a memory cell having a programmed state and a not...  
WO/2017/193644A1
A shift register unit and method thereof. The shift register unit includes an output port (Output) for outputting a driving signal. The shift register unit further includes a first output node control sub-circuit (11) for controlling an ...  
WO/2017/196918A1
A method of forming an array of cross point memory cells comprises using two, and only two, masking steps to collectively pattern within the array spaced lower first lines, spaced upper second lines which cross the first lines, and indiv...  
WO/2017/195541A1
The present invention pertains to a composition for forming a volume hologram recording layer, the composition including: a matrix resin or a precursor thereof; a radical polymerizable monomer; a radical polymerization initiator; and a p...  
WO/2017/195206A1
There is provided a method comprising: accessing a rich video document (RVD) comprising a multi-layer hierarchical data structure mapping hierarchical associations of rendered content items arranged such that a node at a relatively highe...  
WO/2017/192759A1
A memory component includes a first memory bank. The first memory bank has a plurality of sub-arrays having sub-rows of memory elements. The memory component includes a write driver, coupled to the first memory bank, to perform a write o...  
WO/2017/192159A2
In an example, a method may include increasing a voltage applied to an unprogrammed first memory cell in a string of series-connected memory cells from a first voltage to a second voltage while a voltage applied to second memory cells in...  
WO/2017/192159A3
In an example, a method may include increasing a voltage applied to an unprogrammed first memory cell in a string of series-connected memory cells from a first voltage to a second voltage while a voltage applied to second memory cells in...  
WO/2017/192209A1
An integrated circuit (IC) is disclosed herein for accelerating memory access with an output latch. In an example aspect, the output latch includes a data storage unit, first circuitry, and second circuitry. The data storage unit include...  
WO/2017/192626A1
A memory subsystem includes a data bus to couple a memory controller to one or more memory devices. The memory controller and one or more memory devices transfer data for memory access operations. The data transfer includes the transfer ...  
WO/2017/191243A1
A method and a device for generating a composite video are provided. The method comprises obtaining primary and secondary video segments each comprising a sequence of intra-coded I frames and predicted P frames, the primary and secondary...  
WO/2017/191706A1
The present invention reduces a necessary buffer capacity in the memory control circuit of a memory having a plurality of memory blocks. The memory control circuit is provided with an interface and a control unit. The interface receives ...  
WO/2017/192922A1
Apparatus, systems and methods for use in imparting linear tonearm tracking for a record player are provided. The systems can include a joint member having three separate movable connections to a tonearm, guiding slot and slidable pivot ...  
WO/2017/190308A1
A mobile solid state disk (1), comprising a circuit substrate (10), a power supply management module (20), a plurality of Flash storage modules (30), a master control module (40), an interface conversion module (80), a golden finger inte...  
WO/2017/189081A1
A storage system and method for using hybrid blocks with sub-block erase operations are provided. In one embodiment, a storage system is provided comprising a memory comprisiiig a block, wherein the block comprises a first sub-block and ...  
WO/2017/189074A1
Read operations are performed in a multi-plane memory device. A state machine interfaces an external controller to each plane of memory cells to allow reading from selected word lines in the planes. In one approach, different types of re...  

Matches 451 - 500 out of 854,492