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WO/2023/047657A1 |
The present invention enables emotion data, which represents user emotion for each scene of moving image content, to be effectively used. A representative emotion scene is extracted by an extraction unit on the basis of emotion metadat...
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WO/2023/049869A1 |
Nucleic acid polymers for data storage and related methods are provided. In some embodiments, the nucleic acid polymers are writable for data, and in other embodiments, the nucleic acid polymers are encoded with data when synthesized. Ge...
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WO/2023/047149A1 |
The present disclosure relates to a method for operating an array of memory cells, the method comprising storing user data in a plurality of memory cells of the array, storing parity data associated with the user data in a plurality of p...
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WO/2023/044813A1 |
Provided in the embodiments of the present disclosure are a computing circuit and an electronic device. The computing circuit comprises a storage array and an operation array. The storage array comprises a plurality of magnetic units, wh...
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WO/2023/047224A1 |
The present invention provides a semiconductor device with a novel configuration. The semiconductor device comprises a first electrode, a transistor having a back-gate, and a capacitive element having a pair of electrodes, the semiconduc...
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WO/2023/043328A1 |
There is provided a system having a server unit with a host processor and a service processor, a first bus interface and a second bus interface, a data storage unit with a plurality of drives grouped into a first and second group, a firs...
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WO/2023/043931A1 |
Methods, apparatus, systems, and articles of manufacture to improve watermark detection in acoustic environments are disclosed. An example apparatus includes at least one memory, instructions in the apparatus, and processor circuitry to ...
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WO/2023/042866A1 |
This base plate constitutes a part of a housing of a disk drive device, and is formed from a metal plate and a die-cast part. The metal plate includes a board-shaped bottom plate portion that spreads out perpendicular to an up-down exten...
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WO/2023/040158A1 |
Embodiments of the present application relate to the field of semiconductor layout design, and in particular, to a readout circuit architecture, comprising: a first NMOS layout comprising a first N-type active layer and a first gate laye...
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WO/2023/043439A1 |
An apparatus for processing data is provided comprising persistent memory circuitry, non-persistent memory circuitry and memory controller circuitry. The memory controller circuitry provides two or more memory sub-channels and each memor...
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WO/2023/040253A1 |
Embodiments of the present disclosure provide a test board, a test system and a test method. The test board comprises a register clock driver (RCD) module and a memory to be tested, and an output terminal of the RCD module is connected t...
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WO/2023/042254A1 |
A semiconductor storage device (1) comprises a memory cell array (3) in which a plurality of memory cells (MC) are connected to a bit line pair (BLT). In reading of data from the memory cell (MC), a replica bit line signal is output to a...
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WO/2023/040882A1 |
An apparatus (1000) includes a beam (1002), a chip (1004) coupled to the beam (1002), a cable (1006) coupled to the beam (1002) by a first material (1008) located at opposite edges of the cable (1006), and wire bonds (1010) extending fro...
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WO/2023/041919A1 |
A computer memory apparatus is provided having a plurality of storage locations and a plurality of address decoder elements, each having a one or more input address connections for mapping to a respective one or more data elements of an ...
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WO/2023/044503A1 |
Provided herein is a magnetic tunnel junction (MTJ) based non-volatile non-binary matrix multiplier comprising a straintronic MTJ "multiplier" and a spin-orbit torque driven MTJ "accumulator". The multiplier quantity (one element of one ...
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WO/2023/040362A1 |
Provided in the present disclosure are an anti-fuse array structure and a memory, wherein the anti-fuse array structure comprises: a plurality of anti-fuse integrated structures, which are arranged in an anti-fuse matrix in a bit line ex...
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WO/2023/042566A1 |
A semiconductor memory device (5) comprises: a storage unit (4) that has a storage memory cell (4A) that is for storage of data; a reference memory cell (1) that has a memory transistor (1A) that includes a floating gate and an oxide fil...
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WO/2023/038790A1 |
Multiple (e.g., four) memory devices on a module are connected to a common pair of differential data strobe signal conductors. The common pair of differential data strobe conductors are also coupled to a memory controller to time the tra...
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WO/2023/036604A1 |
A method for forming a nonvolatile PCM logic device may include providing a PCM film component having a first end contact distally opposed from a second end contact, positing a first proximity adjacent to a first surface of the PCM film ...
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WO/2023/036452A1 |
A belt strap retractor (10) for a safety belt system has a belt reel (14), a permanent magnet (18) and a magnetic field sensor (20). The belt reel (14) is rotatably mounted and the permanent magnet (18) is connected to the belt reel (14)...
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WO/2023/037585A1 |
A servo pattern recording device according to an embodiment of the present technique is a device for recording multiple servo patterns which are adjacent to magnetic layers of a magnetic tape in a tape width direction, and is equipped wi...
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WO/2023/038745A1 |
A compute-in-memory array is provided that implements a filter for a layer in a neural network. The filter multiplies a plurality of activation bits by a plurality of filter weight bits for each channel in a plurality of channels through...
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WO/2023/037883A1 |
In the present invention, an upper bit-line (BL_A) extends in a Y-direction in an upper memory array (1A) and a Y-decoder (3), and a lower bit-line (BL_B) extends in the Y-direction in a lower memory array (1B) and the Y-decoder. The Y-d...
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WO/2023/035411A1 |
Embodiments of the present disclosure provide a signal shielding circuit and a semiconductor memory. The signal shielding circuit comprises a receiving circuit, a delay control circuit, and a logic operation circuit. The receiving circui...
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WO/2023/038016A1 |
A sputtering target is provided which enables manufacturing a heat assisted magnetic recording medium that has high saturation magnetization and few in-plane oriented magnetic grains. This sputtering target, for producing a heat assist...
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WO/2023/035413A1 |
Embodiments of the present application provide a read and write test method and apparatus, a computer storage medium, and an electronic device. The method comprises: receiving a data instruction sent by a memory controller, and determini...
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WO/2023/035453A1 |
Provided in the embodiments of the present disclosure are a layout structure for testing a junction capacitor, and a design method therefor. The layout structure for testing a junction capacitor comprises: a well region, which is used fo...
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WO/2023/035616A1 |
The embodiments of the present disclosure relate to the field of semiconductors. Provided are a storage circuit and a memory. The storage circuit may at least comprise: a plurality of storage blocks, wherein each of the storage blocks co...
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WO/2023/037446A1 |
This memory device comprises: a first impurity layer 3 and a second impurity layer 4 provided thereon in a trench which is formed in a first semiconductor layer 1 and the side walls of which are covered with a first insulating film 2; a ...
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WO/2023/035346A1 |
Disclosed are a memory cell of a magnetic random-access memory, and a multistate data storage control method. Wherein, the memory cell comprises: a magnetic tunnel junction and two NMOS transistors; wherein, the magnetic tunnel junction ...
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WO/2023/037612A1 |
The main purpose of the present technology is to improve the reliability of magnetic recording tape by controlling the distribution of a binder in an underlayer. The present technology provides a magnetic recording medium that comprise...
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WO/2023/036507A1 |
Methods of forming a settable resistance device, settable resistance devices, and neuromorphic computing devices include isotropically etching a stack of layers, the stack of layers having an insulator layer in contact with a conductor l...
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WO/2023/039364A1 |
A cartridge module alignment and mounting system, apparatus and method for mounting of a plurality of removable modules where the modules can be densely packed within the apparatus and where physical alignment of the module is maintained...
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WO/2023/035659A1 |
A data path detection method and apparatus, a device, and a storage medium, which relate to the technical field of semiconductors and are applied to a detection process for a data path of a semiconductor integrated circuit. The data path...
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WO/2023/038907A1 |
Described herein are writable polymers for data storage and related methods. Generally, a writable polymer may contain one or more convertible residues (e.g., convertible residues comprising a modifiable fluorophore with switchable fluor...
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WO/2023/037810A1 |
Provided are: a hard nitride-containing sputtering target that can prevent the occurrence of arcing during sputtering, caused by inclusion of relatively course zirconia particles, and can suppress the generation of particles during film ...
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WO/2023/035700A1 |
A memory circuit and a memory, the memory circuit at least comprising: a plurality of memory blocks, wherein each memory block comprises a first memory sub-block (11), a second memory sub-block (12) and a third memory sub-block (13) arra...
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WO/2023/038081A1 |
The purpose of the present invention is to provide a CoFeB alloy-based target material that reduces generation of particles during sputtering. Provided is a sputtering target material comprising an alloy containing Co and/or Fe, and B an...
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WO/2023/035512A1 |
A memory and a reading, writing and erasing method thereof. The memory 10 comprises H storage surfaces 100 arranged in parallel along a first direction; each storage surface 100 extends in a second direction, and comprises M columns of s...
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WO/2023/029539A1 |
Disclosed in the present invention are a non-volatile memory, and a writing method and reading method therefor. The non-volatile memory comprises a first memory unit, a second memory unit and a reference unit. The first memory unit and t...
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WO/2023/029228A1 |
Embodiments of the present disclosure provide a layout of a driving circuit, a semiconductor structure and a semiconductor memory, the layout comprising: a P-type transistor, an N-type transistor and four test modules, the four test modu...
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WO/2023/033882A1 |
Apparatuses and techniques are described for programming a multi-tier block in which sub-blocks are arranged in respective tiers. When a program operation involves the source-side sub-block, the NAND strings are pre-charged from the sour...
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WO/2023/034680A1 |
Methods, systems, and devices for deck-level shunting in a memory device are described. A memory device may include memory arrays arranged in a stack of decks over a substrate, and a combination of deck selection circuitry and shunting c...
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WO/2023/034370A1 |
In some embodiments, a system comprises a static random access memory (SRAM) device and a controller. The SRAM device comprises a bit cell array comprising a plurality of bit cells arranged in a plurality of rows and a plurality of colum...
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WO/2023/030053A1 |
An LLC chip (1) and a cache system (50), the LLC chip (1) comprising a storage wafer (30), an interface logic unit (20) and a packaging substrate (10). The interface logic unit (20) and the storage wafer (30) are arranged in sequence on ...
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WO/2023/033908A1 |
The systems and methods described herein consider a first channel width of transistors of driver circuitry (60), where the first channel width may be set to match a second channel width of a power control transistor (82). A control circu...
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WO/2023/033338A1 |
A ferroelectric-based three-dimensional flash memory is disclosed. By determining, from among negative range values or positive range values, a program voltage applied to a target memory cell that is a target of a program operation among...
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WO/2023/034239A1 |
Provided are a read head and methods for reading a multi-layered optical data storage medium comprising a transparent substrate having layers of voxels embedded therein. The read head comprises an imaging system for capturing images of g...
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WO/2023/028890A1 |
In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structu...
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WO/2023/028758A1 |
Methods, apparatuses, and systems relates to write performance optimization for erase on demand. The methods include erasing a portion of memory from a garbage pool in response to detecting an idle period. A request to write data to the ...
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