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WO/2023/035700A1 |
A memory circuit and a memory, the memory circuit at least comprising: a plurality of memory blocks, wherein each memory block comprises a first memory sub-block (11), a second memory sub-block (12) and a third memory sub-block (13) arra...
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WO/2023/038081A1 |
The purpose of the present invention is to provide a CoFeB alloy-based target material that reduces generation of particles during sputtering. Provided is a sputtering target material comprising an alloy containing Co and/or Fe, and B an...
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WO/2023/035512A1 |
A memory and a reading, writing and erasing method thereof. The memory 10 comprises H storage surfaces 100 arranged in parallel along a first direction; each storage surface 100 extends in a second direction, and comprises M columns of s...
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WO/2023/029539A1 |
Disclosed in the present invention are a non-volatile memory, and a writing method and reading method therefor. The non-volatile memory comprises a first memory unit, a second memory unit and a reference unit. The first memory unit and t...
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WO/2023/029228A1 |
Embodiments of the present disclosure provide a layout of a driving circuit, a semiconductor structure and a semiconductor memory, the layout comprising: a P-type transistor, an N-type transistor and four test modules, the four test modu...
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WO/2023/033882A1 |
Apparatuses and techniques are described for programming a multi-tier block in which sub-blocks are arranged in respective tiers. When a program operation involves the source-side sub-block, the NAND strings are pre-charged from the sour...
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WO/2023/034680A1 |
Methods, systems, and devices for deck-level shunting in a memory device are described. A memory device may include memory arrays arranged in a stack of decks over a substrate, and a combination of deck selection circuitry and shunting c...
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WO/2023/034370A1 |
In some embodiments, a system comprises a static random access memory (SRAM) device and a controller. The SRAM device comprises a bit cell array comprising a plurality of bit cells arranged in a plurality of rows and a plurality of colum...
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WO/2023/030053A1 |
An LLC chip (1) and a cache system (50), the LLC chip (1) comprising a storage wafer (30), an interface logic unit (20) and a packaging substrate (10). The interface logic unit (20) and the storage wafer (30) are arranged in sequence on ...
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WO/2023/033908A1 |
The systems and methods described herein consider a first channel width of transistors of driver circuitry (60), where the first channel width may be set to match a second channel width of a power control transistor (82). A control circu...
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WO/2023/033338A1 |
A ferroelectric-based three-dimensional flash memory is disclosed. By determining, from among negative range values or positive range values, a program voltage applied to a target memory cell that is a target of a program operation among...
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WO/2023/034239A1 |
Provided are a read head and methods for reading a multi-layered optical data storage medium comprising a transparent substrate having layers of voxels embedded therein. The read head comprises an imaging system for capturing images of g...
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WO/2023/028890A1 |
In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structu...
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WO/2023/028758A1 |
Methods, apparatuses, and systems relates to write performance optimization for erase on demand. The methods include erasing a portion of memory from a garbage pool in response to detecting an idle period. A request to write data to the ...
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WO/2023/028820A1 |
A system includes a memory device for storing memory data. The memory device includes an array of memory cells and a plurality of word lines arranged in a plurality of rows and coupled to the array of memory cells. The system also includ...
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WO/2023/034679A1 |
Methods, systems, and devices for deck-level signal development cascodes are described. A memory device may include transistors that support both a signal development and decoding functionality. In a first operating condition (e.g., an o...
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WO/2023/031352A1 |
The invention relates to a matrix assembly comprising: - a matrix of resistive components (5), the resistance values of which represent the coefficients of a discrete Fourier matrix, wherein values representing a first set of input value...
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WO/2023/033799A1 |
Methods, systems, devices, and tangible non-transitory computer readable media for adaptive adjustment of playback. The disclosed technology can include accessing content data that includes one or more portions of content for a user. One...
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WO/2023/033879A1 |
Apparatuses and techniques are presented for detecting bit line open circuits and short circuits in a memory device in which a memory die is inverted and bonded to a control die. In one approach, the control die comprises a set of bit li...
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WO/2023/029400A1 |
Embodiments of the present disclosure relate to the field of semiconductors. Provided are a semiconductor structure, a manufacturing method therefor, and a memory. The semiconductor structure may at least comprise: multiple transistors a...
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WO/2023/029142A1 |
In certain aspects, a memory device includes a semiconductor layer, a peripheral circuit including a peripheral transistor in contact with the semiconductor layer, an array of memory cells disposed beside the semiconductor layer and the ...
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WO/2023/028846A1 |
A memory, a programming method and programming verification method for a memory, and a memory system. The programming verification method comprises: obtaining an ith verification result of an ith programming verification operation, a pro...
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WO/2023/030371A1 |
Provided in the present application are a memory link fault detection method and apparatus, and a related device. The method can comprise the following steps: a processor performing fault error correction according to memory read-write e...
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WO/2023/028836A1 |
A power-down test method for firmware of a memory system, a memory system, a computer device, a computer readable storage medium, and a power-down test system. The power-down test method comprises: triggering a power-down test at a plura...
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WO/2023/029346A1 |
Provided are a comparator and a decision feedback equalization circuit, the comparator comprising a first sampling circuit (101), which is used to generate, under the control of first control signals (D270) and clock signals (CLK), first...
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WO/2023/033987A1 |
A memory structure includes storage transistors organized as horizontal NOR memory strings where the storage transistors are thin-film ferroelectric field-effect transistors (FeFETs) having a ferroelectric gate dielectric layer formed ad...
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WO/2023/029412A1 |
The present application relates to a storage component and a preparation method therefor. The storage component comprises: a substrate and multiple storage units arranged in an array on the substrate. The storage units in adjacent rows a...
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WO/2023/034576A1 |
An SRAM controller for performing sequential accesses using internal ports that operate concurrently on different rows. Each internal port includes a row address strobe (RAS) timer that generates clock signals controlling the timing of o...
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WO/2023/028829A1 |
In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structu...
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WO/2023/034235A1 |
In some embodiments, an apparatus comprises: a static random access memory (SRAM) device. The SRAM device may have a bit cell array comprising a plurality of bit cells, the plurality of bit cells arranged in a plurality of rows and a plu...
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WO/2023/034707A1 |
This document describes apparatuses and techniques for implementing data masking with pulse amplitude modulation (PAM) encoded signals of a memory circuit. In various aspects, a data mask function (110) of a memory controller (108) may u...
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WO/2023/034326A1 |
A system includes a memory device having a plurality of memory cells and a processing device operatively coupled to the memory device. The processing device is to determine to perform a rewrite on at least a portion of the plurality of m...
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WO/2023/033881A1 |
A removable disk clamp assembly for mounting disk media on a motor-driven spindle of a magnetic read-write device includes a disk clamp and a mechanism for generating a predetermined force to press the disk media to a flange of the spind...
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WO/2023/034103A1 |
Apparatus might include an array of memory cells comprising a plurality of strings of series-connected memory cells, a data line, a first field-effect transistor between the data line and a first string of series-connected memory cells, ...
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WO/2023/011561A9 |
The present application provides a memory, comprising a plurality of one-time programmable storage elements, each one-time programmable storage element comprising a storage film (30). In one embodiment, the storage film (30) comprises an...
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WO/2023/029403A1 |
Provided in the present disclosure are a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises a substrate. A plurality of vertical transistors arranged in an aligned manner are formed on the ...
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WO/2023/028790A1 |
Embodiments of the present application provide a memory, an operating method therefor, and a memory system. The operation of the memory comprises: simultaneously performing a programming operation on at least two storage planes among a p...
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WO/2023/028848A1 |
A method for loading an L2P table to a cache of a memory controller, comprising: if it is determined, according to the currently obtained L2P table, that the address values of a plurality of target physical addresses corresponding to a p...
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WO/2023/033883A1 |
In a non-volatile memory, a block of NAND strings is divided into sub-blocks by etching the select gate layers between sub-blocks. This results in a subset of NAND strings (e.g., at the border of the sub-blocks) having select gates that ...
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WO/2023/028898A1 |
Embodiments of the present application disclose a programming method for a storage apparatus, a storage apparatus and a storage system. The storage apparatus comprises a plurality of planes. The method comprises: programming at least two...
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WO/2023/028147A1 |
Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word line...
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WO/2023/026383A1 |
This semiconductor integrated circuit device (1) is provided with a ring oscillator (5) of plural stages having delay circuits (10). In each delay circuit (10), when the signal at the input terminal (IN) makes a first transition, the sig...
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WO/2023/024562A1 |
Provided in the present disclosure are a cache content addressable memory and a memory chip encapsulation structure. The cache content addressable memory comprises a ternary content addressable memory, an encapsulation layer, and dynamic...
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WO/2023/027140A1 |
The purpose of the present invention is to provide a magnetic disk substrate and a method for manufacturing same, and a magnetic disk all of which make it possible to maintain high flatness, despite being thin, after a long-term use, be ...
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WO/2023/026537A1 |
The amount of time needed to write data is reduced. This memory device has: a magnetic memory element provided with a reference layer of which the magnetization direction is fixed and a storage layer of which the magnetization direction ...
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WO/2023/024262A1 |
Provided in the embodiments of the present application are an oscillation period measurement circuit and method, and a semiconductor memory. The oscillation period measurement circuit comprises: an oscillator module, which comprises a ta...
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WO/2023/027984A2 |
The internal row addressing of each DRAM on a module is mapped such that row hammer affects different neighboring row addresses in each DRAM. Because the external row address to internal row address mapping scheme ensures that each set o...
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WO/2023/025260A1 |
A flash memory cell (100) and a manufacturing method therefor, and a writing method and an erasing method for the flash memory cell (100). The flash memory cell (100) comprises: a substrate (101), comprising a deep well region (103) and ...
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WO/2023/025261A1 |
Provided in the present disclosure are a flash memory array, and a write method and erasure method therefor. The flash memory array according to the present disclosure comprises: a plurality of flash memory cells, which are arranged in a...
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WO/2023/027857A1 |
A memory is provided that includes multiple memory banks, each one of the memory banks being associated with a read multiplexer. A first read multiplexer couples a first plurality of bit lines to a first sense node pair, and a second rea...
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