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Patent Searching and Data


Matches 101 - 150 out of 854,506

Document Document Title
WO/2018/079931A1
A magnetoresistive memory module used as a main memory of a computing device is provided. A plurality of memory chips is mounted on a printed circuit board and a memory controller performs data scrubbing. Each memory chip comprises a plu...  
WO/2018/079833A1
The purpose of the present invention is to detect the end of writing of data to a variable-resistance memory element in which a conductive electrode is provided at one end of a memory element, the resistance of which varies, and a readin...  
WO/2018/080615A1
Disclosed herein is a memory cell including a memory element and a selector device. The memory cell may be programmed with a programming pulse having a first polarity and read with a read pulse having a second polarity. The memory cell m...  
WO/2018/076645A1
A shift register, a display device and a driving method. The shift register comprises: a driving unit (115), configured to provide a gate line signal to a corresponding pixel unit set; and a compensation circuit (110) provided in corresp...  
WO/2018/076665A1
Disclosed are a shift register, a gate drive circuit, a display panel and a drive method. The shift register (100) comprises: an input and reset circuit (100), connected to a pull-up node (PU), and a drive circuit (200) connected to the ...  
WO/2018/081403A1
A ferroelectric random access memory (FeRAM) array includes (a) a first section of FeRAM cells sharing a first plate line and a word line; and (b) a second section of FeRAM cells sharing a second plate line and the word line, wherein the...  
WO/2018/080725A1
Providing efficient handling of memory array failures in processor-based systems is disclosed. In this regard, in one aspect, a memory controller of a processor-based device is configured to detect a defect within a memory element of a p...  
WO/2018/078349A1
Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one embodiment, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. A plurality of...  
WO/2018/078368A1
The present techniques generally relate to methods, systems and devices for operation of non-volatile memory devices, whereby in an embodiment, a correlated electron switch (CES) device may be placed in any one of multiple memory states ...  
WO/2018/080589A1
An Fe-Al alloy magnetic thin film according to the present invention contains, in terms of atomic ratio, 0% to 35% (inclusive of 0%) of Co and 1.5% to 2% of Al. A [110] direction of a crystal contained in a material is perpendicular to a...  
WO/2018/076239A1
Apparatus and methods of operating such apparatus include applying a first voltage level to a source connected to a first end of a string of series-connected memory cells, applying a second voltage level to a data line connected to a sec...  
WO/2018/080644A1
Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A memory cell is sensed by discharging a sense nod...  
WO/2018/081746A1
A memory subsystem triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with ...  
WO/2018/075566A1
An infant calming/sleep-aid device that includes a moving platform and a sound generator, the sound and motion adapted to calm a fussy baby, induce sleep, and maintain sleep under normal conditions. The device makes a determination as to...  
WO/2018/075200A1
In an aspect of the disclosure, an apparatus is provided. In one aspect, the apparatus is a memory apparatus. The memory apparatus includes a memory. The memory includes first and second bitcell arrays. The memory apparatus also includes...  
WO/2018/073708A1
A data reading error is reduced. A memory cell array in a storage device includes a write word line, a read word line, a write bit line, a read bit line, a source line, and a gain cell. For example, a read transistor in the gain cell can...  
WO/2018/074162A1
This method for producing a magnetic powder comprises a process for producing second particles that contain ε-iron oxide by subjecting first particles that contain iron(II) oxide to a heat treatment.  
WO/2018/074015A1
Provided is a position control device 100 for an electromagnetic drive-type actuator, said device controlling the position of a movable part of an actuator 60 and comprising: a position target signal emission unit 10 which outputs a posi...  
WO/2018/075445A1
An electro-optical sensor chip assembly (SCA) that includes a detection device that includes an array of detector unit cells arranged in a matrix and that produce an electrical output in response to light. The SCA also includes an integr...  
WO/2018/072183A1
A method for making integrated circuit (IC) packages includes providing a leadframe strip having a plurality of leadframe units (602) and providing the leadframe strip to an operating station. The operating station is operable to perform...  
WO/2018/074093A1
[Problem] To provide a semiconductor storage element with a reduced planar area. [Solution] A semiconductor storage element comprising: a memory cell transistor, at least part of which includes a gate insulating film formed from a ferroe...  
WO/2018/072439A1
Disclosed are a test data generation method and device, and a computer storage medium. The method comprises: configuring a first group of data information and a second group of data information for test data in a register; reading corres...  
WO/2018/072325A1
A method and a device for the automatic gain control of an audio signal. The method comprises: identifying zero crossing points of the amplitude in a to-be-processed audio signal, and determining a range between adjacent zero crossing po...  
WO/2018/072683A1
A method or system for supporting dynamic construction of a user selected sub-region (e.g., viewport or region of interest) from other sub-regions of a reference media presentation is presented. The components of the reference media pres...  
WO/2018/073566A1
The present invention provides a method and system for processing data from an event, such as a neurological event. When a neurological event occurs, a spike in a neural waveform is generated. The spike can be detected and used to determ...  
WO/2018/074225A1
The purpose of the present invention is to provide a current source capable of suppressing an increase in circuit size and acquiring a highly accurate constant current that is extremely stable with respect to manufacturing variations or ...  
WO/2018/069256A1
The design of the gramophone (100) for playing music recordings on vinyl records (50) which rotate on a levitating turntable (10) with the help of magnetic forces, substitutes all established versions of analogue gramophones, where the d...  
WO/2018/069716A1
Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one embodiment, a sense circuit may enable a determination of a current impedance state of a non-volatile memory element while avoiding an uninte...  
WO/2018/069219A1
The invention relates to a system for dynamically maximizing the contrast between the foreground and background in images and/or image sequences, comprising at least one image capturing device (C1, C2); at least one analysis module (A1, ...  
WO/2018/069021A1
The method comprises at least: a step of measuring the crossing times T 1, T 2,..., T K,..., T K of a set of thresholds (11) by said signal (10) over a given time interval (T) and in which the sequence numbers of the crossed thresholds a...  
WO/2018/071046A1
Methods and systems for providing a video stream along with a slow motion video showing a particular event depicted in the video stream are described herein. The method includes generating a first video stream and generating a second vid...  
WO/2018/070244A1
The present invention stores, without excess or deficiency, management information on the MPEG-2 TS format specification, when an MMT format is converted to an MPEG-2 TS format. In a process for converting MMT format data to MPEG-2 TS fo...  
WO/2018/071107A1
Apparatuses, systems, and methods are disclosed for accessing non-volatile memory 122. A bit line 302 is coupled to storage cells for a non-volatile memory element 123. A sense amplifier 306 is coupled to a bit line 302. A sense amplifie...  
WO/2018/068638A1
Provided are a solid-state storage device and a temperature and power consumption control method therefor. The control method for the solid-state storage device comprises the following steps: in response to a present operation accessing ...  
WO/2018/069359A1
The invention relates to a capacitive matrix arrangement that comprises an active medium, which is arranged in a layer between word lines and bit lines whose crossing points have capacitor cells, selectable by actuation of the word lines...  
WO/2018/069218A1
The invention relates to a television broadcast system comprising a number of television cameras (C1, C2); at least one production unit (12) which is configured to generate a series of production images from the camera images of the numb...  
WO/2018/071101A1
Methods, systems, and devices for operating a ferroelectric memory cell or cells and, more particularly, a temperature update for a memory device are described. A memory array may be operated according to a timing cycle that includes a f...  
WO/2018/071100A1
Systems and method are directed to a Universal Flash Storage (UFS) host capable of interfacing one or more UFS devices. The UFS host includes a plurality of mobile- physical-layers (M-PHYs) for supporting one or more lanes of traffic bet...  
WO/2018/070743A1
Disclosed is a security device for preventing leakage of data information in a solid-state drive. The present invention provides a security device for preventing leakage of data information in a solid-state drive (SSD) that is used up an...  
WO/2018/067855A4
Methods and apparatus are disclosed for operating a memory cell formed from the plurality of coupled Josephson junctions. The memory cell is configured such that applying an electrical signal to the junctions can cause at least one, but ...  
WO/2018/067168A1
In some examples, a hybrid memory device includes multiple memory cells, where a given memory cell of the multiple memory cells includes a volatile memory element having a plurality of layers including electrically conductive layers and ...  
WO/2018/067904A1
Systems, methods, and software are disclosed herein having enhanced modular carrier form factors. In an implementation, a network card apparatus comprises a network card assembly. The network card assembly comprises a network interface c...  
WO/2018/068061A1
A vertical thyristor memory cell array with each of the thyristor memory cells connected to bit and word lines, the bit lines are connected to the inputs of multiplexers which are connected to sense amplifiers, is adaptable to LPDDR4 req...  
WO/2018/067254A1
Memory systems that provide separate read and write address decoding to support simultaneous memory read and write operations are disclosed. Separating read and write address decoding can avoid circuit conflicts for a simultaneous memory...  
WO/2018/065664A1
A method comprises providing an audio file comprising two or more discrete tracks;separating the two or more discrete tracks; setting a limit on an amount at least one of the two or more discrete tracks may be altered; and outputting the...  
WO/2018/066742A1
Disclosed are an apparatus and a method for providing an image. The image provision apparatus according to one embodiment of the present invention comprises: an image storage unit for storing an image obtained through a camera; and a dis...  
WO/2018/067855A1
Methods and apparatus are disclosed for operating a memory cell formed from the plurality of coupled Josephson junctions. The memory cell is configured such that applying an electrical signal to the junctions can cause at least one, but ...  
WO/2018/067262A1
A non-volatile storage system includes a plurality of memory dies and an interface circuit. Each memory die includes a wide I/O interface electrically coupled to another wide I/O interface of another memory die of the plurality of memory...  
WO/2018/067415A1
A system and a corresponding method to manage image file storage are provided, the system including a memory device to store instructions and at least one processing device to execute the instructions stored in the memory device, to dete...  
WO/2018/063287A1
Substrates, assemblies, and techniques for enabling a resistive random access memory cell are disclosed herein. For example, in some embodiments, a device may include a top electrode, a modulated interfacial region, and a bottom electrod...  

Matches 101 - 150 out of 854,506