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Matches 101 - 150 out of 852,675

Document Document Title
WO/2017/159561A1
This information recording medium (100) includes at least three information layers (10, 20, 30). The information recording medium (100) has, in one information layer (10, 20, 30), a second dielectric film (13, 23, 33) including ZrO and I...  
WO/2017/161102A1
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. One method includes determining whether to access a first memory cell of a first memory cell array or a second memory cell of a second memory...  
WO/2017/160286A1
In some examples, a method of controlling a transition between a functional mode and a test mode of a logic chip includes enabling a clock input of a disable circuit in response to an indication that the logic chip is in the functional m...  
WO/2017/157110A1
A method of controlling high-speed access to a double data rate (DDR) synchronous dynamic random access memory (SDRAM), and a device. The method comprises: dividing, according to a dynamic allocation strategy, a DDR SDRAM into variable b...  
WO/2017/159432A1
This magnetic memory is provided with: a plurality of magnetoresistance effect elements including a first ferromagnetic metal layer with a fixed magnetization direction, a second ferromagnetic metal layer configured to have a variable ma...  
WO/2017/161083A1
A method of implementing fault tolerance in computer memory includes translating a logical address to a first physical address for a first memory location in the computer memory. The computer memory includes redundant memory locations. A...  
WO/2017/159186A1
A recording device (5) comprises a reception unit, a recording unit (53), a first selection unit, and a second selection unit. The reception unit is connected to a vehicle exterior image capture device (2) and a vehicle interior image ca...  
WO/2017/156909A1
A shift register, a gate drive circuit and a display panel. In the shift register, a first node control module 11 provides a signal of an input signal end (Input) for a first node A under the control of a first clock signal end (CK1), an...  
WO/2017/156850A1
A shift register and a drive method therefor, a gate drive circuit, an array substrate and a display device. The shift register (10) comprises: a pull-up control module (1), a pull-up module (2), a pull-down control module (3), a pull-do...  
WO/2017/159560A1
This information recording medium includes at least three information layers. At least one of the information layers has a second dielectric film, a recording film, and a third dielectric film, provided in that order from the side irradi...  
WO/2017/160893A1
A switching device, comprising an anti-ferromagnet structure having an upper layer and a lower layer, the upper layer and lower layer anti-ferromagnetically coupled by an exchange coupling layer, the upper and lower layer formed of a sim...  
WO/2017/159471A1
An optical phase difference member 100 is provided with a transparent substrate 40 on which a pattern 80 of recesses and protrusions is formed, a covering layer 30 covering recesses 70 and projections 60 in the pattern 80 of recesses and...  
WO/2017/155662A1
Systems, methods, and computer programs are disclosed for allocating memory in a hybrid parallel/serial memory system. One method comprises configuring a memory address map for a multi-rank memory system with a dedicated serial access re...  
WO/2017/154403A1
A fluorine-containing ether compound which is represented by formula (1). R1-R2-CH2-R3-CH2-R4 (1) (In formula (1), R1 represents a terminal group which contains an organic group having at least one double bond or triple bond; R2 represen...  
WO/2017/152392A1
A method and apparatus for refreshing a flash memory device, achieving optimization of refresh operations for flash memories. The method comprises: a memory controller (112) reading first data from a first flash block (S402) and determin...  
WO/2017/154382A1
The purpose of the present invention is to accurately retrieve data in a storage device equipped with a variable-resistance cell. When a reference cell circuit receives an initialization signal exceeding a prescribed inversion threshold,...  
WO/2017/155749A1
There is provided a method comprising: causing received image and/or audio data associated with an audio-visual call to be played-out via a user interface; receiving, during the audio-visual call, an instruction to store received image a...  
WO/2017/155668A1
A method is provided that includes forming a vertical bit line (LBL11) disposed in a first direction above a substrate (502), forming a word line (WL10) disposed in a second direction above the substrate, the second direction perpendicul...  
WO/2017/152534A1
A method and device for acquiring an on-die termination (ODT) parameter of a double data rate (DDR) synchronous dynamic random access memory. The method comprises: arranging the m-th value of a DDR ODT and the n-th value of a column addr...  
WO/2017/155510A1
Described is an apparatus which comprises: an interconnect including a stack of metal layers having a first non-alloy metal adjacent to a metal and a first templating layer. The first non-alloy metal is formed of a material which is sele...  
WO/2017/155781A1
Apparatuses and methods are provided for logic/memory devices. An example apparatus comprises a plurality of memory components adjacent to and coupled to one another. A logic component is coupled to the plurality of memory components. At...  
WO/2017/155814A2
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be selected using a selection component that is in electronic communication with a sense amplifier and a ferr...  
WO/2017/154724A1
A recording data processing method in which, for each of an N number (N being a natural number of at least 3) of recording data pairs comprising two successive pieces of recording data when an N number of pieces of recording data are arr...  
WO/2017/155544A1
Examples herein relate to hardware accelerators for calculating node values of neural networks. An example hardware accelerator may include a crossbar array programmed to calculate node values of a neural network and a current comparator...  
WO/2017/154863A1
A regulator circuit (101) has a first stopped state, a second stopped state and an operating state, and includes: a detecting circuit portion (11) which detects the magnitude of an output voltage from the regulator circuit (101) and outp...  
WO/2017/154741A1
Through the present invention, a thin film including a FePt-based alloy usable as a magnetic recording medium can be independently formed, and the quantity of particles can be further reduced. A FePt-C-based sputtering target containing ...  
WO/2017/155508A1
Approaches for integrating spin torque transfer magnetic random access memory (STT-MRAM) memory arrays into a logic processor, and the resulting structures, are described. In an example, a logic processor including a logic region includi...  
WO/2017/153572A1
The present invention provides a computer-implemented method and an apparatus for manufacturing an analogue audio storage medium wherein digital audio data is converted into topographical data representing an analogue translation of the ...  
WO/2017/156444A1
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Offsets in the threshold voltage of switching components (e.g., transistors) connected to digit lines may be compensated by using various ope...  
WO/2017/155509A1
Described is an apparatus which input and output magnets, each configured to have six stable magnetic states including zero state, first state, second state, third state, fourth state, and fifth state, wherein the zero state is to point ...  
WO/2017/153604A1
CAM memory cell (100) comprising: a latch (103) comprising N first TFETs (102) that are connected in series between two supply potentials so that each source and drain of the first TFETs is connected either to one of the potentials or to...  
WO/2017/153864A1
The circuit scale of a semiconductor device that can perform arithmetic processing of analog data is reduced. In the semiconductor device, a memory cell is configured to generate a first current corresponding to first analog data and to ...  
WO/2017/156028A2
A memory device having a plurality sections of memory cells, such as ferroelectric memory cells (hybrid RAM (HRAM) cells) may provide for concurrent access to memory cells within independent sections of the memory device. A first memory ...  
WO/2017/155200A1
Disclosed is a method for providing music information, comprising the steps of: receiving a music signal from a user; generating a continuous melody line corresponding to the music signal, by using pitch frequencies detected from the mus...  
WO/2017/155753A1
A recording device, such as a video camera, emits audio watermarks (e.g., audible tones, inaudible tones) and records audio watermarks emitted by other recording devices. The audio watermarks provide information (e.g., data) such as an i...  
WO/2017/152553A1
A gate driving circuit and a detection method therefor, an array substrate, and a display device. The gate driving circuit comprises a plurality of cascaded gate driving units (1), access units (2), a first signal line (3), and a second ...  
WO/2017/152828A1
Proposed is a distributed pattern processor containing a three-dimensional memory (3D-M) array. The distributed pattern processor contains a plurality of memory processing units, wherein each unit contains a pattern processing circuit an...  
WO/2017/150579A1
Provided is a management device 10 that includes a plurality of tracks (MTR 101) that correspond to a plurality of terminal devices 20, that commands the terminal devices 20 to start or stop recording in accordance with a recording start...  
WO/2017/150980A1
Quantum dot circuit and a method of characterizing such a circuit Voltages that enable control of electron occupation in a series of quantum dots are determined by a method of measuring effects of gate electrode voltages on a quantum dot...  
WO/2017/151058A1
A reader structure, a method of biasing a free layer of a reader structure, and a read head are provided, the reader structure comprises a free layer having a reader edge for interacting with and being proximal to a magnetic media; a fir...  
WO/2017/151302A1
A memory array includes a first subarray of memory cells and a second set of memory cells. The first and second subarrays of memory cells share a set of global word lines. The first and second subarrays of memory cells are coupled to fir...  
WO/2017/148137A1
A shift register unit (100, 200, 300, 300A, 300B, 400, 600) includes a first node-control circuit (11, 71) for controlling a pull-up node (PU), a second node-control circuit (12, 72) for controlling a pull-down control node (PDCN), a thi...  
WO/2017/150970A1
The present invention is in the field of an atomic scale data storage device which uses vacancy manipulation, a method of providing said device, and a method of operating said device. Prior art mass data storage devices typically rely on...  
WO/2017/149412A1
The invention relates to devices intended for storing, systemising and using information in order to plan events and/or specific periods of time, and/or for educational purposes, and/or for carrying out games based on the use of cards. T...  
WO/2017/151296A1
A memory device and method comprising a metal oxide material disposed between and in electrical contact with first and second conductive electrodes, and a voltage source configured to apply a plurality of voltage pulses spaced apart in t...  
WO/2017/149874A1
A magnetoresistive element 10 is provided with: a first laminated structure 20 having a first surface 20A, and a second surface 20B on the reverse side of the first surface 20A; and a second laminated structure 30, which is formed by lam...  
WO/2017/150524A1
A film which is composed of a non-magnetic material and a magnetic metal containing Fe and Pt, and which is characterized by additionally containing Mg and having a composition represented by (Fe1-αPtα)1-βMgβ (wherein α and β are n...  
WO/2017/151567A1
A dynamic random access memory (DRAM) content aware refresh system includes a central processing unit (CPU) communicatively coupled to a memory controller having a content aware refresh unit. A main memory includes DRAM organized into a ...  
WO/2017/149282A1
There is provided a multiple data rate memory comprising a clock splitting circuit and a multiplexing address latch. The clock splitting circuit is configured to generate first and second internal clock pulses from a rising edge of an ex...  
WO/2017/151482A1
Speech understanding in the presence of background noise can be assessed using novel hearing tests. One such test is a Masking Level Difference with Digits (MLDD) test, which is a clinical tool designed to measure auditory factors that i...  

Matches 101 - 150 out of 852,675