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Patent Searching and Data


Matches 101 - 150 out of 857,375

Document Document Title
WO/2019/070081A1
[Problem] To separate a Fourier-transform hologram-reproduced image and a volume-reflection hologram-reproduced image so as to allow observation. [Solution] A hologram element comprises a hologram layer recorded by superimposing: a first...  
WO/2019/069479A1
The present invention comprises: a drive unit; a changer unit comprising a tray carrier that transports one disc tray selected from among a plurality of disc trays to the vicinity of the drive unit, and a disc selector disposed in the vi...  
WO/2019/070459A1
Methods, systems, and devices for communicating data with stacked memory dies are described. A first semiconductor die may communicate with an external computing device using a binary-symbol signal including two signal levels representin...  
WO/2019/070537A1
Apparatuses and methods including memory commands for semiconductor memories are described. An example method includes receiving a data clock signal responsive to receiving a timing command, performing an access operation responsive to r...  
WO/2019/069997A1
Provided is an information processing device (10) comprising: a storage unit (105) storing a database in which time stamp information indicative of a start time on the time axis of a video, text information obtained by converting speech ...  
WO/2019/069480A1
A disc device comprising a drive unit that records or plays back information on the disc, and a housing that supports the drive unit, wherein the drive unit is configured so as to be detachable from the housing. The drive unit comprises ...  
WO/2019/068959A1
An apparatus for audio signal processing audio objects within at least one audio scene, the apparatus comprising at least one processor configured to:define for at least one time period at least one contextual grouping comprising at leas...  
WO/2019/070428A1
A method of forming a memory device with memory cells in a memory area, and logic devices in first and second peripheral areas. The memory cells each include a floating gate, a word line gate and an erase gate, and each logic device incl...  
WO/2019/061068A1
A system component such as a nonvolatile solid state storage drive (104) or a nonvolatile memory module has an on-board wireless power receiver (112) which receives wirelessly transmitted power in a disconnected state to power refresh op...  
WO/2019/061361A1
Provided are devices and methods relating to temperature control in a solid state drive (SSD). A SSD (10, 110, 210, 310, 410, 510,610, 710) including a housing (12, 112, 212, 312, 412, 512, 612, 712) including a plurality of sides surrou...  
WO/2019/066537A1
Various embodiments of the present invention relate to a device for displaying content and an operation method therefor. An electronic device of the present invention comprises a display device, at least one processor, and a memory coupl...  
WO/2019/067052A1
A device (10) includes a combinational circuit configured to create a one or more distortion correction factors used offset inter-symbol interference from a data stream on a distorted bit. The device (10) also includes a selection circui...  
WO/2019/064679A1
An aluminum alloy substrate for magnetic disks, which is formed from an aluminum alloy that contains 0.4-3.0 mass% (hereinafter referred to as "%") of Fe, less than 0.10% of Si and less than 0.10% of Mg, with the balance being made up of...  
WO/2019/066086A1
The purpose of the present invention is to prevent adhesion between a magnetic disc and a spacer when removing the magnetic disc and the spacer from a hard disc drive device where the magnetic disc and the spacer are installed. The surfa...  
WO/2019/066729A1
Disclosed herein is a compound of formula (I): [M(L)n]m+ (Ay-)z (I) wherein M represents Ru, Fe, Co, Rh, Ir, Ni, Os, Cr, Cu or Mn; A represents an anionic group having a charge y, wherein y is 1 to 4, m is 1 to 4, n is 2 to 6, z is 1 to ...  
WO/2019/062287A1
A shift register unit, a gate drive circuit and a driving method, and a display device, which may improve the stability of the shift register unit. The shift register unit comprises a first input circuit (10), a second input circuit (20)...  
WO/2019/064808A1
The present invention is characterized by comprising: an operation part 40 that can be operated; a light-emitting part 42 that is arranged to correspond to the operation part 40 and that indicates the location of the operation part 40; a...  
WO/2019/063878A1
A method, apparatus (63) and computer program comprising: obtaining (60) a first audio signal from at least a first microphone (1) located at a first distance from an audio source (5A - 5C); obtaining (60) a local audio signal from a loc...  
WO/2019/064215A1
It is described a mathematical solving circuit (100) comprising: a crosspoint matrix (MG) including a plurality of row conductors (L±), a plurality of column conductors (Cj) and a plurality of analog resistive memories (Gij), each conne...  
WO/2019/063736A1
A method comprising determining feature values of an input audio window and determining model parameters for the input audio window based on processing of feature values using a neural network.  
WO/2019/065228A1
Provided are: a curing agent for magnetic recording media, which contains a compound represented by general formula (1); a composition for magnetic recording media, which contains this curing agent for magnetic recording media; a method ...  
WO/2019/066820A1
An apparatus is provided which comprises: a first logic device including: a spin orbit coupling material, magnetostrictive material, and at least two transistors to operate using first a clock signal; a second logic device coupled to the...  
WO/2019/068012A1
In one embodiment, an apparatus comprises a memory array and a controller. The controller is to receive a first read command specifying a read voltage offset profile identifier; identify a read voltage offset profile associated with the ...  
WO/2019/066821A1
Described is an apparatus which comprises: a storage node; a first device coupled to the storage node; a second device coupled to a first reference and the storage node, wherein the second device has negative differential resistance (NDR...  
WO/2019/062245A1
Disclosed are a shift register and driving method therefor, a gate driver circuit, and a display device. The shift register comprises an input circuit, a reset circuit, a first control circuit, a first output circuit, and a second output...  
WO/2019/065345A1
In order to assign an index used for cueing when recorded data is reproduced, and to carry out said assignment onsite by means of a simple operation during the recording of sound or the recording of an image and at an arbitrary timing de...  
WO/2019/062265A1
A shift register unit, a gate driving circuit and driving method, and a display device. The shift register unit comprises: a first input circuit (10), used for outputting the voltage of a first voltage terminal (V1) to a pull-up node (PU...  
WO/2019/066906A1
A 2T-2S SRAM cell exhibiting a complementary scheme, that includes two selector devices that exhibit negative differential resistance. Advantages include lower area and better performance than traditional SRAM cells, according to some em...  
WO/2019/064111A1
The invention is notably directed to a resistive memory device comprising a control unit for controlling the resistive memory device and a plurality of memory cells. The plurality of memory cells includes a first terminal, a second termi...  
WO/2019/067886A1
A storage controller is provided. The storage controller includes a host interface, a media interface, and a processing system. The processing system is configured to receive data from the host system, select write locations within the s...  
WO/2019/064963A1
A rack for a disc storage device comprises: a housing space surrounded by right and left side plates and top and bottom partition plates and accommodating a disc storage device; a guide part provided on the side plates and fitted to a gu...  
WO/2019/061965A1
A shift temporary storage circuit (20) and a display panel using same. The shift temporary storage circuit (20) comprises multi stages of shift registers, each shift register comprising: a first switch (T10), one control end (101a) of th...  
WO/2019/067053A1
A device (10) includes a decoder (204, 365) configured to receive an input signal. The decoder (204, 365) is configured to also output a control signal based on the input signal. The device (10) further includes an equalizer (202, 292, 3...  
WO/2019/067980A1
Provided herein is a computing memory architecture. The non-volatile memory architecture can comprise a resistive random access memory array comprising multiple sets of bitlines and multiple wordlines, a first data interface for receivin...  
WO/2019/067262A1
Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes voltage regulators in an integrated circuit device, and a frequency control block and a module included in the integrated circuit...  
WO/2019/067251A1
Various embodiments can include apparatus and methods to perform a one check failure byte (CFBYTE) scheme in programming of a memory device. In programming memory cells in which each memory cell can store multiple bits, the multiple bits...  
WO/2019/065200A1
Provided is a magnetic tape which comprises, on a non-magnetic supporting body, a magnetic layer that contains a ferromagnetic powder and a binder, and which is configured such that: the magnetic layer contains an oxide polishing agent; ...  
WO/2019/065199A1
Provided is a magnetic tape which comprises, on a non-magnetic supporting body, a magnetic layer that contains a ferromagnetic powder and a binder, and which is configured such that: the magnetic layer contains an oxide polishing agent; ...  
WO/2019/058820A1
This sputtering target contains, as a metal component, Co and one or more metals selected from the group consisting of Cr and Ru, and the molar ratio of the content of the one or more metals selected from the group consisting of Cr and R...  
WO/2019/059970A1
Technology is described for identifying non-volatile memory cells having data that should be refreshed. The technology could be used to identify which groups of memory cells that store cold data should have a data refresh. In one aspect,...  
WO/2019/058209A1
A calibration system for media content comprises a memory, a media device, a plurality of different types of sensors, and a control circuitry. The memory is configured to store a media item and expected-emotions-tagging metadata for the ...  
WO/2019/060083A1
Systems, methods, and apparatus for writing data into a static random access memory (SRAM) are provided. A write driver circuit includes a bitcell array, a bitline coupled to the bitcell array, and a first driving circuit configured to d...  
WO/2019/056803A1
A shift register unit (100), a gate drive circuit (10), a display device (1), and a drive method. The shift register unit (100) comprises an input circuit (110), a pull-up node reset circuit (120), an output circuit (130) and a coupling ...  
WO/2019/058819A1
This sputtering target contains Co and Pt as metal components, and the molar ratio of the Pt content to the Co content is 5/100 to 45/100. The sputtering target also contains Nb2O5 as a metal oxide component.  
WO/2019/059951A1
An apparatus is provided which comprises: a magnetic junction; a first layer exhibiting spin orbit coupling properties, wherein the first layer is adjacent to the magnetic junction, wherein the first layer includes a first side and a sec...  
WO/2019/060191A1
An electronic device includes a pressure-sensitive user interface component, a memory device, and a processor. The memory device stores executable instructions to perform a method that displays a media player on a display of the electron...  
WO/2019/060067A1
Disclosed are methods and apparatus for implementing a memory controller, such as a bus integrated memory controller (BIMC) that includes a memory built-in-self-test (MBIST) controller or logic. The MBIST controller is configured for tes...  
WO/2019/060121A1
In an example, a method of memory repair may include receiving, by a memory repair unit, a plurality of memory identifiers. The method may include determining, by the memory repair unit, that a first memory identifier of the plurality of...  
WO/2019/060019A1
A device (10) includes one or more memory banks (12) configured to store data. The device (10) also includes a data receiver (62) configured to receive distorted input data as part of a data stream, apply a correction factor to the disto...  
WO/2019/056935A1
Provided are an FT4222-based testing system and method for an SPI flash. The testing method comprises: invoking an FT4222 chip device from debugging tools according to a testing statement inputted by a tester; configuring testing conditi...  

Matches 101 - 150 out of 857,375