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Patent Searching and Data


Matches 101 - 150 out of 853,453

Document Document Title
WO/2017/214628A1
This patent document provides implementations and examples of circuits and devices based on low-energy consumption semiconductor structures exhibiting multi-valued states. In one aspect, a semiconductor device is configured to comprise: ...  
WO/2017/209815A1
A system and method is disclosed for fast secure destruction or erasure of data in a non-volatile memory. The method may include identifying a fast erase condition, such as an unauthorized access attempt, and then applying a fast erase p...  
WO/2017/208880A1
A spin-current assist type magnetoresistance effect device (200) according to the invention of the present application is provided with: a spin-current assist type magnetoresistance effect element (100) including a magnetoresistance effe...  
WO/2017/208698A1
The present invention suppresses an increase of a circuit scale. A semiconductor device (1) is provided with control circuits (1a, 1b) and memory (1c). Furthermore, an external element (2) is connected to the semiconductor device (1). Th...  
WO/2017/208016A1
There is provided a method for accessing a memory cell of a plurality of memory cells that are part of a memory unit, the memory cells being grouped into a plurality of memory cell groups, wherein each memory cell group is associated wit...  
WO/2017/206191A1
A data storage method and apparatus. The method comprises: monitoring a rate at which data is written into a mechanical hard drive disk; and when the monitored rate at which the data is written into the mechanical hard drive disk is lowe...  
WO/2017/206542A1
Provided are a shift register and an operation method therefor, a grid drive circuit, and a display device. The shift register comprises: an input module (11), wherein a first end thereof is connected to an input end (INPUT) of the shift...  
WO/2017/209842A1
In an aspect of the disclosure, a method and an apparatus are provided. The apparatus may be a content addressable memory. The content addressable memory includes a plurality of memory sections each configured to store data. Additionally...  
WO/2017/209858A1
Methods, systems, and devices for a sensing scheme that extracts the full or nearly full remnant polarization charge difference between two logic states of a ferroelectric memory cell or cells is described. The scheme employs a charge mi...  
WO/2017/209921A1
According to various aspects, a memory controller may schedule ZQ commands to periodically calibrate individual memory ranks in a multi-rank memory. The memory controller may schedule a ZQ short command at each ZQ interval and record tha...  
WO/2017/209781A1
A post-package repair system includes a memory channel controller, a first error counter, a scrubber, and a data processor. The memory channel controller converts data access requests to corresponding memory accesses, and provides return...  
WO/2017/209912A1
Examples of high-temperature memory modules used in a well operation are disclosed. In one example implementation according to aspects of the present disclosure, a memory module may include: a control unit configured to receive data from...  
WO/2017/208825A1
Provided are a hard disk drive (HDD) unit and electronic device that have high maintainability. In one embodiment of the present invention, the HDD unit includes an HDD case and an HDD holder. The HDD case is provided with an HDD tray an...  
WO/2017/208653A1
This nonvolatile memory cell is provided with: a laminated structure 11 formed by laminating each other a storage layer 20, which stores information corresponding to the magnetization direction, and a magnetization fixing layer 30, which...  
WO/2017/209812A1
A non-volatile memory system includes one or more control circuits configured to read memory cells. The reading of the programmed memory cells includes applying one or more voltages to perform boosting of a channel region associated with...  
WO/2017/209811A1
A non-volatile memory system includes one or more control circuits configured to program memory cells and verify the programming. The verifying of the programmed memory cells includes applying one or more voltages to perform boosting of ...  
WO/2017/208014A1
There is provided a memory unit comprising an array of memory cells and a driver circuit configured to output an output address signal that addresses a portion/subset of the array of memory cells. The driver circuit comprises a logic gat...  
WO/2017/209314A1
The present invention relates to a system finishing apparatus, and disclosed is a system finishing apparatus capable of installing various devices without separate electric wiring, improving assemblability, and enhancing an interior desi...  
WO/2017/210024A1
A device includes a power supply line, an output terminal, a circuit configured to perform a logic operation on a first signal and a second signal to produce a third signal, first, second and third transistors. The first transistor is co...  
WO/2017/208721A1
Provided are a device and a method for generating a reproduction signal with less laser noise. The device includes: a photodetector (PD) that irradiates a disc with laser light and outputs a signal based on the reflection light from the ...  
WO/2017/206751A1
A GOA unit circuit (10) and a drive method therefor, and a GOA circuit, relating to the technical field of display, and used for solving the problem that an existing GOA circuit has high power consumption and occupies a big area. The GOA...  
WO/2017/205007A1
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory device may leverage non-volatile memory properties of a ferroelectric capacitor―e.g., that a ferroelectric capacitor may remain po...  
WO/2017/203477A1
A system and method for editing media content, by embedding graphics, text, images, icons and the like into it. An HTML overlay graphics layer is used to view the additional content in relation to the original media content. The addition...  
WO/2017/204002A1
The present invention pertains to a signal processing device and a signal processing method that enable robust reproduction of data recorded at high density. The frame sync (FS), which represents the header of a frame, is restored by, fr...  
WO/2017/205088A1
The present invention relates to an improved sensing amplifier and related method for use in read operations in flash memory devices. In one embodiment, the sensing amplifier includes a built-in voltage offset. In another embodiment, a v...  
WO/2017/205378A1
A data processing system includes a memory channel and a data processor coupled to the memory channel. The data processor is adapted to access at least one rank and has refresh logic. In response to an activation of the refresh logic, th...  
WO/2017/205029A1
Systems and methods for providing variable trick-play mode playback of media content in accordance with embodiments of the invention are disclosed. A playback device stores images of the media content associated with presentation times a...  
WO/2017/204977A1
One embodiment describes a reciprocal quantum logic (RQL) sense amplifier system. The system includes an input stage configured to amplify a sense current received at an input. The system also includes a detection stage configured to tri...  
WO/2017/204876A1
A system and method of writing data to a memory block includes receiving user data in a memory controller to be written to the memory block. The user data is first written to a buffer. A screening pattern is written to at least one scree...  
WO/2017/202617A1
A system (100) and method for zooming of a video recording are provided. The system is configured to detect, track and select object(s) in a first view (110) of the video recording. The system further is configured to perform at least on...  
WO/2017/204957A1
An apparatus is provided which comprises: a select line; a select transistor coupled to a resistive memory element and to the select line; a word-line coupled to a gate terminal of the select transistor; and a current mirror operable to ...  
WO/2017/204679A1
Claimed is a method for automatically creating video content taking into account the preferences of a user. The invention relates to systems for automatically editing digital films from material filmed by a user, which enable the user to...  
WO/2017/204224A1
The present invention provides: a glass for use in magnetic recording media, which enables reduction of heat cracking arising from a temperature distribution in a glass substrate during a process for heating the glass substrate over 600Â...  
WO/2017/204871A1
Techniques are provided for reducing program disturb and short term data retention loss. Program disturb becomes worse for the drain-side memory cells at higher temperatures, while data retention generally does not become worse at higher...  
WO/2017/204158A1
Provided is a sputtering target material which has an improved strength without using pure Ta, can be prevented from forming cracks or particles during sputtering, and can be prevented from having a non-uniform composition in a sputtered...  
WO/2017/204143A1
The present invention provides: a glass for data storage medium substrates, which is easy to recognize in a production process and which enables shards of the glass caused by cracking or chipping to be easily found; a glass substrate for...  
WO/2017/204980A1
Methods of operating a memory include developing first and second voltage levels in first and second semiconductor materials, respectively, forming channel regions for first and second groupings of memory cells, respectively, of a string...  
WO/2017/204001A1
The present invention pertains to a disc-like recording medium, a recording device, a recording method, a reproduction device, and a reproduction method that enable recording of data at high density and enable robust reproduction of data...  
WO/2017/202619A1
A user interface, UI, (100) for zooming of a video recording by a device comprising a screen, the UI being configured to: register a marking by a user on the screen of an object in the video recording on the screen, associate the marking...  
WO/2017/199677A1
A semiconductor circuit includes first (IV1, IV3) and second (IV2, IV4) circuits, first (31) and second (32) transistors, a first storage element (35), and a driver (22, 23, 52, 53). The first (IV1, IV3) and second (IV2, IV4) circuits, r...  
WO/2017/199743A1
The present invention enables recording, in an MPEG-2 TS format, and playback of a high frame rate image based on an MMT format. MPEG-2 TS format data in which a main stream and a substream based on the MMT format are stored in setting p...  
WO/2017/200710A1
A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory cells includes a column bit line, a first column control gate line for even row c...  
WO/2017/199430A1
A disk transfer device (1) is provided with: a plurality of disk drives (30); a housing unit (20) that holds a plurality of disks (50) in a stacked state such that the disks are not in contact with each other; and a transfer unit (10), w...  
WO/2017/198737A1
An apparatus (1) for processing a multichannel audio signal (100) is provided, comprising a plurality of channel signals (x1, x2). The apparatus performs a time scale modulation of the multichannel audio signal (100) and comprises a phas...  
WO/2017/201339A1
A system and methods for manufacturing devices such as flexures using process coupons are described. The method includes performing a test on at least one feature of a coupon, the coupon is included on an assembly sheet used in manufactu...  
WO/2017/200888A1
The present invention relates to a flash memory cell with only four terminals and decoder circuitry for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the pr...  
WO/2017/200657A1
Systems and methods relate to memory operations in a memory array. A compare operation is performed using a sense amplifier. True and complement versions of a search bit are compared with true and complement versions of a data bit stored...  
WO/2017/197917A1
A shift register and an operation method therefor. The shift register comprises: an input module (31), connected to an input terminal (INPUT) and a pull-up node (PU) of the shift register; a reset module (32), connected to a reset signal...  
WO/2017/196369A1
An integrated circuit device can include a plurality of SRAM cells, each including a pair of latching devices having controllable current paths connected to first and second latching nodes, and control terminals cross-coupled between the...  
WO/2017/196424A1
A memory system includes blocks (or other groupings) of memory cells including data memory cells and dummy memory cells. In order to mitigate program disturb or other issues, the memory system applies a gate voltage based on temperature ...  

Matches 101 - 150 out of 853,453