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Patent Searching and Data


Matches 101 - 150 out of 857,845

Document Document Title
WO/2019/118096A1
A system and a method for power mode selection in a portable computing device is provided herein. The system and method may comprise operations for operating the portable computing device in a normal mode. The normal mode may utilize a p...  
WO/2019/118108A1
Embodiments of the present disclosure may relate to a memory controller that may include a memory interface and a logic circuitry component coupled with the memory interface. In some embodiments, the logic circuitry component is to progr...  
WO/2019/116915A1
The semiconductor circuit is provided with: a first circuit which can apply to a second node the reverse voltage of the voltage in a first node; a second circuit which can apply to the first node the reverse voltage of the voltage in the...  
WO/2019/118214A1
Systems, methods, and devices for providing power to low energy circuits include inrush circuits. Devices include a regulator that includes at least one driver device configured to generate a first current associated with a load comprisi...  
WO/2019/114450A1
A data edge transition method, applied to a memory system. The memory system comprises a processor and a memory driven by the processor. Multiple groups of data lines are connected between the processor and the memory. The transition met...  
WO/2019/117540A1
The purpose of the present invention is to provide a photopolymer composition, a hologram recording medium using the same, an optical device, and a holographic recording method, the photopolymer composition comprising: a polymer matrix h...  
WO/2019/118045A1
A memory device [100] includes a memory cell [101] coupled to a bitline [113] and a bitline complement [114]. A first capacitive structure [121] is charged with a first voltage source such as a memory supply voltage. A second capacitive ...  
WO/2019/118192A1
Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting...  
WO/2019/113921A1
The present invention relates to a flash memory programming circuit and programming method. The programming circuit comprises a programming transistor and a storage unit connected in series, wherein a gate electrode of the programming tr...  
WO/2019/116961A1
This semiconductor circuit is provided with: a first circuit which can apply to a second node the reverse voltage of the voltage on a first node; a second circuit which can apply to the first node the reverse voltage of the voltage on th...  
WO/2019/116932A1
A semiconductor device of the present disclosure is provided with: a memory cell which has a first terminal, a second terminal, a storage element that can assume a first resistance state and a second resistance state, and a non-linear el...  
WO/2019/118317A1
Systems, apparatuses and methods related to subarray addressing for electronic memory and/or storage are described. Concurrent access to different rows within different subarrays may be enabled via independent subarray addressing such th...  
WO/2019/114217A1
A computing array based on a 1T1R device, an operation circuit, and an operating method. The computing array comprises: a 1T1R array and a peripheral circuit, wherein the 1T1R array is used for implementing an operation and storing an op...  
WO/2019/118008A1
A memory device (14) may include a memory array (22) that includes multiple memory cells. The memory device (14) may also include multiple sense amplifiers (70) that, in operation, may each be connected to one or more memory cells. The s...  
WO/2019/117542A1
The present invention relates to a photopolymer composition comprising: a polymer matrix or a precursor thereof, the polymer matrix comprising a reaction product between a polyol having two or more hydroxy groups and a reactive isocyanat...  
WO/2019/118009A1
A memory device may include a memory array, which may also include, multiple memory cells. The memory device may also include one or more counters designed to generate internal memory addresses to sequentially access the multiple memory ...  
WO/2019/118223A1
Apparatuses and methods for data transmission offset values in burst transmissions. An example apparatus may include offset logic configured to provide offset values associated with a receiver circuit of a memory device coupled to a sign...  
WO/2019/114356A1
Disclosed in the present invention are a magnetic tunnel junction and a manufacturing method therefor. The manufacturing method for the magnetic tunnel junction comprises the following steps: a step of forming a first dielectric hole: fo...  
WO/2019/115333A1
Methods of creating and recreating a mix instructions file for mixing two or more music tracks are disclosed including the comparison of the music tracks used in creation and recreation, respectively. If possible and necessary, the recre...  
WO/2019/112937A1
The present disclosure includes apparatuses and methods related to data movement operations in non-volatile memory. An example apparatus can comprise an array of non-volatile memory cells including a plurality of sections each with a plu...  
WO/2019/112742A1
A wave pipeline includes a first stage, a plurality of second stages, and a third stage. The first stage receives a data signal representative of data and a clock signal, and may process the data at a first data rate equal to a clock rat...  
WO/2019/110873A1
A method, apparatus and computer-readable storage medium are provided to define a storyline based on path probabilities for a plurality of paths through the frames of a video. Relative to a method and for a plurality of frames of a video...  
WO/2019/111104A1
The present invention provides a semiconductor device which maintains data without being influenced by a change in temperature. The present invention is provided with a band gap reference circuit, a voltage reference circuit, a voltage c...  
WO/2019/112068A1
A storage circuit (11) is provided with: memory cells (MCij) each of which include a MTJ element; and reference cells (RCi) each of which include a series circuit of a linear resistor (FR) and a MTJ element set in a low resistance state....  
WO/2019/111532A1
Provided is a disk tray capable of extracting a plurality of disks more reliably, and reducing the occurrence of powdering caused by the extraction of the disks. This disk tray is a disk tray that houses a plurality of disks in a stacked...  
WO/2019/113215A1
Methods, devices, systems and computer software/program code products improve the reliability of scene reconstruction through the use of a persistent store or cache to retain scene information observed across one or more previous frames.  
WO/2019/111531A1
Provided is a disk device in which the configuration of a changer unit can be simplified by eliminating the need to provide a lifter. The invention comprises a disk selector spindle that holds a plurality of disks in a stacked state and ...  
WO/2019/112358A1
The present invention relates to: a hologram recording medium having a main relaxation temperature of 0℃ or lower as determined by dynamic mechanical analysis in the -80℃ to 30℃ range, the main relaxation temperature being the poin...  
WO/2019/111088A1
Provided is a storage device capable of performing both a retention operation at high temperatures and a high-speed operation at low temperatures. This storage device has a driver circuit and a plurality of memory cells. The memory cells...  
WO/2019/112280A1
An audio file generating/playing device and method for foreign language listening comprehension are disclosed. The device comprises: an audio file storage module for storing an audio file created in a foreign language voice; an augmented...  
WO/2019/111260A1
A hardware memory includes at least one memory cell, peripheral circuitry and randomization circuitry. The memory cell(s) store data, which may be written to, read from and held in the hardware memory. The peripheral circuitry reads and ...  
WO/2019/110874A1
A method, apparatus and computer-readable storage medium provide information regarding changes in viewing behavior between first and second frame of a video. In a method, a plurality of objects that are included within a respective frame...  
WO/2019/112680A1
Write assist circuitry (106) facilitates increased voltage applied to a memory device (100), such as a memory cell (101), in changing a logical state of the memory device during a write operation. The write assist circuitry includes a se...  
WO/2019/111112A1
Provided is a semiconductor device that exhibits a high on-state current and a fast operation speed. This semiconductor device comprises a transistor and a first circuit. The transistor comprises a first gate and a second gate that have ...  
WO/2019/112675A1
A high-performance write operation to program data to a group of non-volatile memory cells may be completed in response to applying a single programming pulse to the group. Programming of the cells may be verified (and/or corrected) afte...  
WO/2019/111525A1
[Problem] To provide a semiconductor storage device which operates appropriately when arrayed in a memory cell, while avoiding a voltage drop due to an oxide film formed on a surface of a semiconductor substrate. [Solution] This semicond...  
WO/2019/112576A1
Multi-period thin-film structures exhibiting giant magnetoresistance (GMR) are described. Techniques are also described by which narrow spacing and/or feature size may be achieved for such structures and other thin-film structures having...  
WO/2019/109944A1
A method, apparatus and device for storing a parameter of an energy storage battery in an energy storage system and a method, apparatus and device for reading a parameter of an energy storage battery in an energy storage system. The stor...  
WO/2019/112882A1
Apparatuses and methods for providing bias signals in a semiconductor device are described. An example apparatus includes a power supply configured to provide a supply voltage and further includes a bias circuit coupled to the power supp...  
WO/2019/111533A1
Provided is a disk device that improves the maintainability of a drive unit. This disk device comprises: a disk tray; and a disk selector that supplies, to a drive unit, a single disk from among a plurality of disks stacked on the disk t...  
WO/2019/112756A1
A memory device includes a memory cell, a logic device and a high voltage device formed on the same semiconductor substrate. Portions of the upper surface of the substrate under the memory cell and the high voltage device are recessed re...  
WO/2019/110395A1
An aspect of the invention relates to a method for interacting with a subtitle displayed in a display area of a digital television screen, the method comprising: - a calibration step, in which: • a computer displays a first point in th...  
WO/2019/112881A1
Disclosed herein is an apparatus that includes first and second voltage terminals; first, second, and third circuit nodes, a potential of the first circuit node being changed based on an input signal; a flip-flop circuit comprising first...  
WO/2019/112712A1
Reduction of program disturb degradation in a flash memory cell array is facilitated by selectively switching wordline voltage levels in a sequence that reduces the likelihood of trapping electrons in memory cell channels. During a progr...  
WO/2019/110015A1
A DRAM cell includes a transistor, a first diode and a second diode. The transistor has a gate electrically coupled to a word line of an address decoder and a drain electrically coupled to a bit line of the address decoder. The bit line ...  
WO/2019/111437A1
This optical disc wherein information can be recorded on both sides is provided with: a specific information region, which is provided merely on one side of the optical disc, and in which specific information of the optical disc is to be...  
WO/2019/108274A1
A memory device includes a data write circuitry. The data write circuitry is configured to capture a first write command received via an external input/output (I/O) interface. The data write circuitry is further configured to generate a ...  
WO/2019/106479A1
A novel memory device is provided. A first cell array including a plurality of memory cells and a second cell array including a plurality of memory cells are stacked. One of two bit lines of a first bit line pair is electrically connecte...  
WO/2019/108298A1
Apparatuses, systems, and methods are disclosed for current sensing for non-volatile memory. A current to voltage conversion circuit (706) may convert a current coupled to a sense amplifier (150) to an analog voltage at a sense node (708...  
WO/2019/108334A1
An artificial neural network device that utilizes analog neuromorphic memory that comprises one or more non-volatile memory arrays. The embodiments comprise improved mechanisms and algorithms for tuning the non-volatile memory arrays suc...  

Matches 101 - 150 out of 857,845