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Patent Searching and Data


Matches 101 - 150 out of 847,865

Document Document Title
WO/2017/083267A1
A method of accessing data stored in a storage disk of a storage system includes the steps of receiving a read operation to a sector of the storage disk and in response to an error returned from the read operation, determining whether th...  
WO/2017/077602A1
This storage device 101 comprises a shingled magnetic recording device 103, a management unit 108, a selection unit 106, and an execution unit 107. The shingled magnetic recording device 103 uses a band that includes adjacent track group...  
WO/2017/075843A1
Provided is a scan driving device (20), which comprises a plurality of scan driving circuits (21), a detection driving circuit (22), and a regulation module (23), wherein the scan driving circuits (21) each comprise a pull-up control mod...  
WO/2017/075747A1
Methods, systems, and machine-readable storage medium for programming a storage device are disclosed. In some embodiments, the methods include: performing a verify operation on a plurality of storage elements of the storage device to det...  
WO/2017/078920A1
A memory device including a silicon substrate having a planar upper surface in a memory cell area and an upwardly extending silicon fin in a logic device area. The silicon fin includes side surfaces extending up and terminating at a top ...  
WO/2017/078918A1
A non-volatile memory cell that includes a silicon substrate, source and drain regions formed in the silicon substrate (where a channel region of the substrate is defined between the source and drain regions), a metal floating gate dispo...  
WO/2017/078988A1
Disclosed herein is a memory cell. The memory cell may act both as a combined selector device and memory element. The memory cell may be programmed by applying write pulses having different polarities. Different polarities of the write p...  
WO/2017/078877A1
Magnetic tunnel junction (MTJ) devices with a heterogeneous free layer structure particularly suited for efficient spin-torque-transfer (STT) magnetic random access memory (MRAM) (STT MRAM) are disclosed. In one aspect, a MTJ structure (...  
WO/2017/079511A1
Embodiments of an electroentropic memory device comprising an array of electroentropic storage devices (EESDs) are disclosed, as well as methods of making and using the electroentropic memory device. The memory device includes a pluralit...  
WO/2017/076084A1
A shift register unit, gate drive circuit, drive method thereof and display device, the shift register unit comprising two transmission gate modules (221, 212), four AND gate modules (231, 232, 233, 234) and two capacitor modules (241, 2...  
WO/2017/073394A1
According to the present invention, in a memory cell forming unit (3a), four electrical disconnection units (13a, 13b, 13d, 13c (13e, 13f, 13h, 13g)) which can disconnect a source-side selection gate electrode (SG) from a drain-side sele...  
WO/2017/074575A1
Based on performance during programming, the non-volatile memory cells are classified as fast programming memory cells and slow programming memory cells (or other classifications). At a separate time for each programmed state, threshold ...  
WO/2017/075464A1
Systems, methods, and apparatus for operating an integrated circuit (IC) are provided. An apparatus may be configured to receive at one or more switches a signal from at least one circuit positioned on a first die lying within a first ge...  
WO/2017/074581A1
Non-volatile memory systems with mufti-write direction memory units are disclosed in one implementation an apparatus comprises a non-volatile memory and a controller in communication with the non-volatile memory. The controller is config...  
WO/2017/074292A1
A volatile memory device includes a memory array of volatile charge storage cells, a counter to track a time since the volatile memory device has received a read/write command and a control element to automatically change the volatile me...  
WO/2017/073667A1
An audio device that comprises: a network communication unit that communicates with other first and second audio apparatuses; a sound emission unit that emits audio signals as sound; and a control unit. When one channel that is for audio...  
WO/2017/074586A1
Apparatus and method for performing a post-write read in a memory device are disclosed. A memory device may include 3-dimensional memory, with the wordlines in a memory block each having multiple strings. Periodically, the memory device ...  
WO/2017/074600A1
Embodiments include a system, method, and apparatus for creating a trusted speech transcription. Transcription logic can receive a signal of audible speech from an audio source and convert the audible speech signal into text. Sampling lo...  
WO/2017/074263A1
A magnetic memory device (300) comprises a memory component (112) comprising perpendicular magnetic anisotropy material. The writing component comprises electrically-conductive material, the writing component being for writing a magnetic...  
WO/2017/074579A1
Technology is described herein for reclaiming a memory device that has a defective plane. A solution allows a memory device with a defective plane to operate as a single plane device. The memory device with the defective plane may be use...  
WO/2017/074589A1
A data storage device includes a memory including multiple storage elements. The data storage device also includes circuitry configured to determine, for a particular storage element of the multiple storage elements, an indicator associa...  
WO/2017/074604A1
Systems, apparatuses and methods may provide for identifying a target sub-block of NAND strings to be partially or wholly erased in memory and triggering a leakage current condition in one or more target select gate drain-side (SGD) devi...  
WO/2017/074521A1
A tool is disclosed for use in managing waste services, The tool may have an interface configured to receive input from a user indicative of an on-demand service request. The tool may also have a communication device, and a controller in...  
WO/2017/074737A1
According to one embodiment of the present invention, an apparatus is disclosed. The apparatus includes a memory array having a plurality of memory cells. The apparatus further includes memory access circuits coupled to the memory array ...  
WO/2017/074563A1
Systems and methods for managing a data buffer of a non-volatile memory system are disclosed. The method may include a controller of a storage system retrieving host data, storing the retrieved data in a data buffer and transferring the ...  
WO/2017/075622A1
In described examples, a BIST controller (40) generates test data patterns to be applied to embedded memories (45) through a BIST data path. Each embedded memory (45) is coupled to a dedicated local comparator (46) that compares data rea...  
WO/2017/075279A1
Embodiments of the invention provide an audio blending system with a computing device that processes operations including receiving a transition request from a user including an out element and/or an in element of at least one transition...  
WO/2017/075442A1
A data storage device includes a solid-state memory including memory cells and a controller that performs a first programming scheme that programs a first subset of the cells to a first voltage state using a first target voltage, program...  
WO/2017/073358A1
A sample-and-hold circuit includes a sampling capacitor, a first transistor, a first switch between a gate electrode and a source electrode of the first transistor, a current source connected to the source electrode of the first transist...  
WO/2017/074358A1
A circuit includes a resistive memory cell in a memory array to store a memory state for the resistive memory cell. A reference cell in the memory array stores a reference memory state for the resistive memory cell. A function generator ...  
WO/2017/074576A1
Techniques are provided for reducing current consumption while programming non-volatile storage. A smart verify is performed using a subset of memory cells. By applying the smart verify to just a subset of the memory cells current is sav...  
WO/2017/073359A1
A sample-and-hold circuit includes a first transistor; a second transistor disposed between a gate electrode and a drain electrode of the first transistor; a sampling capacitor, an electrode of the sampling capacitor being connected to t...  
WO/2017/069869A1
Techniques are provided for programming a memory device. A pre-charge phase is used to boost the channel of an unselected NAND string by allowing a bit line voltage to reach the channel. To maximize the channel pre-charge while also mini...  
WO/2017/070050A1
The invention pertains to mitigation of row hammer attacks in DRAM integrated circuits. Apparatus and methods are disclosed for an embedded target row refresh (TRR) solution with modest overhead. In operation it is nearly transparent to ...  
WO/2017/067489A1
Provided in the embodiments of the present invention is a method for set-top box audio-visual synchronization, comprising: when determining that a first audio-visual frame in a current synchronization queue is already output, obtaining t...  
WO/2017/068855A1
Provided is a media reproduction device that is capable of presenting annotation information that has been assigned to a derived package generated from a derivation source package, said annotation information being presented together wit...  
WO/2017/070018A1
A method of forming a non- volatile memory cell includes forming spaced apart first and second regions in a substrate, defining a channel region there between. A floating gate is formed over a first portion of the channel region and over...  
WO/2017/068032A1
A method is provided for forming cross-fades between audio files, which includes providing a plurality of audio files, each audio file comprising a plurality of respective audio streams pertaining to a single song, and providing a librar...  
WO/2017/069871A1
A memory device, and method of operation, includes an array of non- volatile memory cells and a controller. The controller is configured to perform an operation (e.g. erase, program, etc.) on a first plurality of the non-volatile memory ...  
WO/2017/069021A1
The present invention realizes a shift register that makes it possible to improve reliability compared with before for long-term operation regarding driving of a gate bus line. According to the present invention, a shift register is oper...  
WO/2017/068478A1
The memory device includes a first transistor and a circuit. The circuit includes a second to a (2n + 1)th transistor, a first to an n-th capacitor, a first wiring, and a first to an n-th retention node (n is an integer greater than or e...  
WO/2017/068328A1
A circuit comprises an array of programmable memory elements fabricated on a substrate, each memory element having one or more processable regions which, when processed by an external process in which a material is applied to at least pa...  
WO/2017/070343A1
Various examples are provided for intelligent mouthguards that can be used in fitness and sport activities. In one example, an intelligent mouthguard system includes a mouthguard including sensors and an internal module in communication ...  
WO/2017/068971A1
Data playback is performed in a mode determined on the basis of disk type information, which is recording data for a disk. A reading rate corresponding to the physical format of a disk and a reading rate corresponding to the disk type ar...  
WO/2017/067038A1
Provided is a semiconductor memory device operation method, comprising: randomizing operation address data to obtain a random code; performing a combinational logical operation on the random code and raw data to obtain randomized data, o...  
WO/2017/070459A1
A non-volatile memory system includes a plurality of non-volatile memory cells, one or more control circuits that perform programming of the memory cells, a power supply line that provides a supply used during a programming operation of ...  
WO/2017/067406A1
A shift register unit, the shift register unit includes an input module (310), a first resetting module (330), an energy storage module (350), a first enhanced resetting module (340), an output control module (320), a first input termina...  
WO/2017/068858A1
[Problem] To provide an information processing device with which it is possible to smoothly re-listen to audio. [Solution] Provided is an information processing device provided with a playback processing unit for performing playback on t...  
WO/2017/067432A1
A shift register unit and driving method thereof, shift register and display device. The shift register unit comprises an input circuit (P1), a pull-down control circuit (P2), a pull-up control circuit (P3), a pull-up circuit (P4) and a ...  
WO/2017/064764A1
As a result of a cam recess (44) sliding in a cam groove (61) of an arm 6, the arm (6) approaches an arm (5) when a shutter (2) is in two positions, namely a closed position and an open position, and the arm (6) moves away from the arm (...  

Matches 101 - 150 out of 847,865