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Patent Searching and Data


Matches 101 - 150 out of 858,320

Document Document Title
WO/2019/146198A1
A nonvolatile memory device (10) includes: a memory group constituted by at least one data cell and at least one dummy cell which are associated with each other and serve as a plurality of variable-resistance memory cells (21) whereby di...  
WO/2019/146623A1
A marching memory (31) includes an alternating periodic array of odd-numbered columns (U1, U2,........, Un-1, Un) and even-numbered columns (Ur1, Ur2,........, Urn-1, Urn). Each of the odd-numbered columns (U1, U2,........, Un-1, Un) has...  
WO/2019/147452A1
A memory device, memory address decoder, a memory system and related method for memory attack detection are disclosed. An apparatus includes a memory decoder include multiple stages in a decoding path configured to generate a select sign...  
WO/2019/143395A1
Methods and systems for internal timing schemes are provided. A data strobe (DQS) signal is received at a memory device. The DQS signal is shifted in a negative direction relative to a clock of the memory device to cause a fail point of ...  
WO/2019/141003A1
Provided are a shift register unit circuit and a drive method therefor, a scanning drive circuit and a display device. The shift register unit circuit comprises: an input sub-circuit used for setting a level at the first node to an activ...  
WO/2019/144076A1
One embodiment provides a method, including: capturing, from each of at least two cameras, video from a vantage point of an event; generating an immersive video stream from the video captured by the at least two cameras; producing a tran...  
WO/2019/143575A1
In various embodiments, a subtitle application generates a subtitle list for a trailer. In operation, the subtitle application performs matching operation(s) between trailer audio associated with a trailer and source audio associated wit...  
WO/2019/133627A9
A touch control system comprising: a first electronic data processing device, a second electronic data processing device, and a tactile control surface, wherein the first electronic data processing device may be a computer, and the secon...  
WO/2019/126416A3
Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the u...  
WO/2019/140887A1
A method for sorting threshold voltage parameters used by a flash memory storage device, comprising: initially reading flash memory data from within a flash memory; detecting that an error occurs in the flash memory data; a certain set o...  
WO/2019/142081A1
[Abstract] Provided is a semiconductor device with which it is possible to acquire a threshold value voltage for a transistor. The semiconductor device has a first transistor, a first capacitive element, a first output terminal, a first ...  
WO/2019/143389A1
A device (10) includes a voltage generator (329) that generates a reference signal (202, 83, 322), a multi-level bias generator (319) coupled to the voltage generator (329) to receive the reference signal (202, 83, 322) and generate a pl...  
WO/2019/143388A1
A device (10) includes a first bias level generator (200) to generate a first bias level (202) of a plurality of bias levels and transmit the bias level (202) having a first voltage value, a second bias level generator (321) to generate ...  
WO/2019/140859A1
Provided are shift register circuit, driving method of the shift register circuit, gate driving circuit and display apparatus. The shift register circuit may include a shift output circuit(10) and N driving output circuits(20). N is an i...  
WO/2019/140693A1
Disclosed is an operation method for the integration of logic calculations and data storage based on a cross array structure of a resistive switching device. The calculation and storage functions of the method are based on the same hardw...  
WO/2019/142093A1
A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work togeth...  
WO/2019/136979A1
Disclosed is a bad block management method for increasing the available capacity of a storage device, wherein the available capacity of a flash memory storage system is related to the number of bad blocks, and the more the bad blocks, th...  
WO/2019/139836A1
A data storage system capable of switching a code rate based on a host command is disclosed. A controller of the data storage system may set a code rate in a data storage device to a first code rate for encoding data to be written to non...  
WO/2019/140074A1
Devices and techniques to recover data from a memory device using a custom Read Retry feature are disclosed herein. A memory device can receive a first read request, read data from the memory array corresponding to the read request, and ...  
WO/2019/138828A1
This semiconductor device is provided with: a first gate electrode comprising a first main wiring part which extends in a first active region of a semiconductor substrate in a first direction and divides the first active region into a fi...  
WO/2019/140361A1
An example device includes at least one processor configured to receive electrical parameter values corresponding to at least one first location within a power network. The at least one processor is further configured to determine, using...  
WO/2019/136980A1
A bad block processing method for a multi-channel memory system. A bad block processing mechanism is provided on flash memory devices of multiple data channels; by weeding bad blocks out of a block group and recombining available blocks ...  
WO/2019/139647A1
A device (10) includes a first terminal configured to receive a reference voltage, a second terminal configured to receive a weighted tap value (86), a local generator circuit (504, 506, 508, 510) configured to create a group (476, 478, ...  
WO/2019/136962A1
The present application discloses an audio conversion apparatus and a multi-sound system. The audio conversion apparatus comprises: a modem configured to convert a received audio signal into a power carrier signal or to convert a receive...  
WO/2019/136976A1
Disclosed is a method for using various error correction code combinations in a encoding and decoding system, comprising a computer, a master control chip and a plurality of storage assemblies, wherein the computer is connected to the ma...  
WO/2019/136972A1
Disclosed is a method for reducing the bit error rate of a flash memory. A flash memory control device and multiple flash memory chips are comprised, wherein the flash memory control device is connected to the multiple flash memory chips...  
WO/2019/140364A1
A memory controller includes a generator circuit configured to generate a predetermined pattern of data, an address input, and a memory interface circuit. The memory interface circuit is configured to write the predetermined pattern of d...  
WO/2019/136138A1
A cloud implementation of a persisted storage device, such as a disk, is provided. The implementation supports a variety of features and protocols, in full analogy with a physical storage device such as a disk drive. The present disclosu...  
WO/2019/135798A1
A device (10) includes a selection circuit (200) that is configured to generate a bias level (202). The device (10) also includes a combinational circuit (80) coupled to the selection circuit. The combinational circuit (80) is configured...  
WO/2019/135012A1
The invention relates to a method for the management of audio dubbing and voice-over production intended for audiovisual media, such that the presence of different dubbing actors is not required in the studio. The implementation of the m...  
WO/2019/135134A1
A technique relates to operating a memory controller. The memory controller drives first memory devices and second memory devices of the memory controller in a dual channel mode. A first error correcting code (ECC) memory device and a se...  
WO/2019/135523A1
The present invention relates to an electronic device, a control method therefor, and a computer program product. The electronic device comprises: a memory in which instructions are stored; and a processor executing the instructions so a...  
WO/2019/135325A1
An encoder includes a layered structure including a metal plate, a dielectric layer arranged on the metal plate, and a plurality of metallic components arranged on the dielectric layer to form a pattern of resonant circuits. The encoder ...  
WO/2019/135866A1
A memory device includes memory cells each configured to produce an output current during a read operation. Circuitry is configured to, for each of the memory cells, generate a read value based on the output current of the memory cell. C...  
WO/2019/135853A1
A pair of memory cells that includes first and second spaced apart trenches formed into the upper surface of a semiconductor substrate, and first and second floating gates disposed in the first and second trenches. First and second word ...  
WO/2019/135796A1
Holographic volume gratings in waveguide cells can be recorded using many different methods and systems in accordance with various embodiments of the invention. One embodiment includes a holographic recording system including at least on...  
WO/2019/135818A1
Disclosed is a memory system comprising a sense amplifier electrically coupled to a first bitline and a second bitline associated with a column of a memory array, a bl transistor electrically coupled to the first bitline, wherein the bl ...  
WO/2019/136175A1
Provided herein are compositions, devices, systems and methods for generation and use of biomolecule-based information for storage. Further provided are devices comprising addressable electrodes controlling polynucleotide synthesis (depr...  
WO/2019/135743A1
A memory device comprises an interconnect having a spin orbit torque (SOT) material. A magnetic tunnel junction (MTJ) device comprises a free layer magnet coupled to the interconnect, a reference fixed magnet, and a barrier material betw...  
WO/2019/134413A1
A shift register unit (300, 400, 500, 600, 700, 900), a gate drive circuit, a display device, and a control method (1200) for the display device. The shift register unit (300, 400, 500, 600, 700, 900) comprises an input sub-circuit (310,...  
WO/2019/134450A1
A shift register unit, a gate drive circuit, a display device and a drive method. The shift register unit comprises an input circuit (110), a first node reset circuit (120), an output circuit (130) and a noise reduction touch circuit (14...  
WO/2019/135132A1
The invention relates to a circuit (10) for monitoring an output voltage of a voltage supply (12). The circuit (10) comprises a microcontroller (14) for controlling a system, a shift register (16a, 16b, 16c) and a diagnostic circuit (22)...  
WO/2019/134367A1
A shift register circuit, a driving method, and a display device. The shift register circuit comprises a noise reduction sub-circuit (50) and a pull-down node control sub-circuit (10); a control end of the noise reduction sub-circuit (50...  
WO/2019/130516A1
In one embodiment, a method for producing an aluminum-made platter is provided, whereby it becomes possible to improve the smoothness of the surface of a substrate on which a magnetic layer is not formed yet and to produce a hard disk su...  
WO/2019/131084A1
Provided is a spacer having excellent magnetic characteristics. This spacer (12) is produced by forming a sheet of a ferrite stainless steel into a ring shape, and thereafter, applying heat and pressure to the ring-shaped sheet at a temp...  
WO/2019/133295A1
A memory device comprising an array of memory cells wherein each memory cell comprises a respective magnetic random access memory (MRAM) element, a respective gating transistor, and a common wordline coupled to gates of gating transistor...  
WO/2019/133328A1
A device includes an array of memory cells, input/output lines coupled to the memory cells, and sense amplifiers coupled to the input/output lines. Each sense amplifier is associated with a respective input/output line. The device also i...  
WO/2019/133299A1
A memory device for storing data is disclosed. The memory device comprises a memory bank comprising a memory array of addressable memory cells and a pipeline configured to process read and write operations addressed to the memory bank. F...  
WO/2019/130596A1
A sound playback control device which is connected to a computer (2) in a bidirectionally communicable manner and controls music data being played back by means of a music playback application (21) operating on the computer (2) is provid...  
WO/2019/133300A1
Techniques to update a trim parameter in non-volatile memory during either a manufacturing stage or a post-manufacturing stage are described. Trim parameters may be stored in a register located within the memory device that is inaccessib...  

Matches 101 - 150 out of 858,320