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Patent Searching and Data


Matches 301 - 350 out of 854,384

Document Document Title
WO/2018/003931A1
A TFT circuit (101) is provided with: a first node (N1) to which a first low potential (Vc) is supplied; a depression-type first TFT (21) that is disposed between the first node (N1) and a low-potential wiring (11) for supplying a second...  
WO/2018/004548A1
A three dimensional (3D) array of magnetic random access memory (MRAM) bit-cells is described, wherein the array includes a mesh of: a first interconnect extending along a first axis; a second interconnect extending along a second axis; ...  
WO/2018/005699A1
Systems and methods for performing word line pulse techniques in magnetoelectric junctions in accordance with embodiments of the invention are disclosed. In one embodiment, a magnetoelectric random access memory (MeRAM) circuit, includin...  
WO/2018/004698A1
Material layer stack structures to provide a magnetic tunnel junction (MTJ) having improved perpendicular magnetic anisotropy (PMA) characteristics. In an embodiment, a free magnetic layer of the material layer stack is disposed between ...  
WO/2018/004663A1
A two transistor memory cell is described with amorphous oxide semiconductors and silicon transistors. In some examples a memory cell includes a sensing transistor having a source coupled to a read bit line and a drain coupled to a read ...  
WO/2018/004840A1
An apparatus includes a memory, a timing circuit configured to emulate a first operation of the memory to activate a second operation of the memory, a sensor configured to emulate a portion of the timing circuit, and a controller configu...  
WO/2018/004796A3
An apparatus is provided which comprises: a first supply node to provide power supply; a column of memory cells coupled to the first supply node; a diode-connected device having a gate terminal coupled to the first supply node, and a sou...  
WO/2018/004830A1
A memory subsystem enables a refresh abort command. A memory controller can issue an abort for an in-process refresh command sent to a memory device. The refresh abort enables the memory controller to more precisely control the timing of...  
WO/2018/004587A1
Approaches for fabricating RRAM stacks with two-dimensional (2D) barrier layers, and the resulting structures and devices, are described. In an example, a resistive random access memory (RRAM) device includes a conductive interconnect di...  
WO/2018/000517A1
A power management circuit, comprising a master control digital logic module (10), an operating mode power voltage regulator circuit (20), and a sleep mode power voltage regulator circuit (30). An operating power output end (202) of the ...  
WO/2018/004659A1
A three transistor memory cell is described with metal oxide semiconductors. The memory cell in some examples has a pass gate transistor having a source coupled to a read bit line and a gate coupled to a read word line, a sensing transis...  
WO/2018/005100A1
Methods, systems, and apparatuses relating to package on package memory refresh and self-refresh rate management are described. In one embodiment, an apparatus includes a processor die, a dynamic memory die mounted to and overlapping the...  
WO/2018/004648A1
Embodiments of the present disclosure describe apparatuses, methods, and systems associated with magnetoelectric cells. A magnetoelectric cell may include a magnetic tunnel junction that includes a fixed magnet layer and a free magnet la...  
WO/2018/004368A1
A technique for managing SSDs in a data storage system generates an endurance value for each of multiple SSDs and arranges the SSDs in RAID groups based at least in part on the generated endurance values. As a result of such arranging...  
WO/2018/004562A1
Approaches for fabricating self-aligned pedestals for resistive random access memory (RRAM) elements and devices, and the resulting structures, are described. In an example, a resistive random access memory (RRAM) device includes a condu...  
WO/2018/003147A1
The present invention provides a reproduction system in which behaviors of two persons can be easily compared with each other. A reproduction system (10) according to the present invention is characterized by comprising: a storage means ...  
WO/2018/004796A2
An apparatus is provided which comprises: a first supply node to provide power supply; a column of memory cells coupled to the first supply node; a diode-connected device having a gate terminal coupled to the first supply node, and a sou...  
WO/2018/003050A1
In the present invention, a nonvolatile memory device reads data from a read source area in a nonvolatile memory using a preset reading threshold, and corrects errors in the data. If the nonvolatile memory device fails to correct errors,...  
WO/2018/004756A1
In an embodiment, a memory system may include at least two types of DRAM, which differ in at least one characteristic. For example, one DRAM type may be a high density DRAM, while another DRAM type may have lower density but may also hav...  
WO/2018/005572A1
A two-dimensional accessible non-volatile memory apparatus includes an array comprising a plurality of non-volatile memory cells, the array being a crossbar-based non-volatile memory structure, the memory cells being arranged in a plural...  
WO/2018/005224A1
Systems and methods for performing an action based on viewing positions of other users are provided. Viewing progress in a media asset of each of a plurality of users is retrieved. The viewing progress of each of the plurality of users i...  
WO/2018/004574A1
Approaches for fabricating RRAM stacks with an amorphous bottom ballast layer, and the resulting structures and devices, are described. In an example, a resistive random access memory (RRAM) device includes a conductive interconnect disp...  
WO/2018/004377A1
The utility model relates to devices, and particularly cases, for storing and using memory devices such as USB flashdrives, memory cards and other solid-state data storage devices. The technical result of the utility model consists in th...  
WO/2018/004998A1
Methods, systems, and devices for preventing disturb of untargeted memory cells during repeated access operations of target memory cells are described for a non-volatile memory array. Multiple memory cells may be in electronic communicat...  
WO/2018/005871A1
A method for improving an integrated circuit design which has transistors with nanowire channels comprises identifying a particular device having a particular transistor with a nanowire channel; and adding to the integrated circuit desig...  
WO/2018/000237A1
Disclosed are apparatuses and methods for controlling gate-induced drain leakage current in a transistor device. An apparatus may include a first biasing circuit stage configured to provide a biasing voltage on a biasing signal line, the...  
WO/2018/006002A1
Embodiments of disk drive head suspensions are described that include a spring metal layer. The spring metal layer includes a base region, support arms extending from the base region, and a slider mounting region. The slider mounting reg...  
WO/2018/004836A1
A disclosed example to reduce a threshold voltage drift of a selector device of a memory cell includes providing an applied voltage to the selector device of the memory cell, the applied voltage being less than a threshold voltage of the...  
WO/2018/004819A2
Techniques and mechanisms to provide a connector for securing to a first printed circuit board (PCB). In an embodiment, the connector is configured to receive a second PCB, where a first hardware interface of the connector includes condu...  
WO/2018/003601A1
Provided are an airtight terminal for an HDD device and a hard disc device having excellent gas barrier properties and capable of reducing the number of man-hours needed for assembly. An airtight terminal (10) for an HDD device includes:...  
WO/2017/222610A1
Described herein is a first system (100) that includes sleds (110) each having sidewalls (122), a mounting plate (126), and a first cover (114). The first cover (114) is movable relative to the sidewalls (122) between a closed position a...  
WO/2017/222818A1
Systems and method for a host-driven data refresh of a Flash memory include registers provided in the Flash memory for storing various settings related to refresh operations, such as, when to start/stop refreshing, target partitions in t...  
WO/2017/219763A1
A GOA signal determining circuit and determining method, by which the GOA output anomaly caused when part of output signals of a GOA are lost in a frame can be avoided. The GOA signal determining circuit is connected to an input end (inp...  
WO/2017/221573A1
The purpose of the present invention is to provide a magnetic recording medium including a magnetic layer or magnetic recording layer which has a granular structure in which magnetic crystal grains have been satisfactorily separated from...  
WO/2017/223119A1
A method of operating a semiconductor device that is powered by a first power supply potential can include detecting a change in at least one voltage window signal, the voltage window signal indicates a predetermined voltage window in wh...  
WO/2017/222786A1
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described, A cell may be written with a value that is intended to convey a different logic state than may typically be associated with the value. For ex...  
WO/2017/222126A1
The present invention relates to a structure for attaching and detaching a storage device of a POS apparatus, and is characterized by enabling the detachment and attachment or replacement of a storage means including a hard disk drive or...  
WO/2017/222899A1
A process for lapping a row of head sliders involves fixing the row to a lapping tool fixture, actuating each of multiple force pins to set each head slider for lapping to a respective target wedge angle, and simultaneously lapping accor...  
WO/2017/222592A1
Electrical switching technologies employ the otherwise undesirable line defect in crystalline materials to form conductive filaments. A switching cell includes a crystalline layer disposed between an active electrode and another electrod...  
WO/2017/219364A1
A method for processing data, a storage apparatus, a solid state disk and a storage system. The method is applied to an SSD, and comprises: an SSD receiving a write request from a controller, wherein the write request carries data to be ...  
WO/2017/219585A1
A shift register unit circuit(10) includes an input port(INPUT) for receiving an input signal, an output port(OUTPUT) for outputting a gate driving signal, a first clock input port(CLK) for receiving a first clock signal, a second clock ...  
WO/2017/221014A1
The present invention provides a magnetic head for erasing data on a magnetic tape, the magnetic head comprising a body having an elongate magnet mounted thereon, and a plurality of magnetisable portions in magnetisable communication wit...  
WO/2017/222775A1
Methods, systems, and apparatuses for memory array bit inversion are described. A memory cell (e.g., a ferroelectric memory cell) may be written with a charge associated with a logic state that may be the inverse of the intended logic st...  
WO/2017/222038A1
The purpose of the present invention is to provide a magnetoresistive element that has a high magnetic resistance (MR) ratio and a suitable device resistance (RA) for device applications. This magnetoresistive element has a structure in ...  
WO/2017/222870A1
The present disclosure includes apparatuses and methods to transfer data between banks of memory cells. An example includes a plurality of banks of memory cells and a controller coupled to the plurality of subarrays configured to cause t...  
WO/2017/223374A1
The present disclosure relates to a liquid crystal writing device including a first conductive layer, a second conductive layer, a cholesteric liquid crystal mixture layer sandwiched by the first conductive layer and the second conductiv...  
WO/2017/220991A1
A method for delivering an interactive video is provided, including delivering a first video clip of the interactive video in a first loop, and upon receiving a first input during delivery of the first video clip, delivering a first exit...  
WO/2017/221968A1
Provided is a processing device capable of, on the basis of data prepared by a recorder that only has recording function, acquiring information related to a time when the data was prepared. The processing device includes an acquisition u...  
WO/2017/219824A1
Provided are a shift register unit, a driving method, a gate driver circuit, and a display device. The shift register unit comprises: an input unit (11); a reset unit (12); a first pull-up node control unit (13); a second pull-up node co...  
WO/2017/222723A1
High aspect ratio vertical interconnect access (via) interconnections in magnetic random access memory (MRAM) bit cells are disclosed.In one aspect, an exemplary MRAM bit cell includes a coupling column interconnecting an access transist...  

Matches 301 - 350 out of 854,384