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Matches 301 - 350 out of 855,529

Document Document Title
WO/2018/106951A1
Techniques are described that enable a high-capacity memory chip based on three-dimensional SpinRAM cells and modules, and support electronics, at least some of which, are implemented with all-metal solid-state components.  
WO/2018/106450A1
A resistive random access memory cell includes three resistive random access memory devices (102, 104, 106), each resistive random access memory device having an ion source layer (156, 166, 186) and a solid electrolyte layer (154, 164, 1...  
WO/2018/105961A3
Provided are a high-quality audio player for an Android operating system-based portable electronic device and a method therefor. A high-quality audio player for an Android operating system-based portable electronic device according to an...  
WO/2018/107076A1
Apparatuses and methods for calibrating adjustable impedances of a semiconductor device are disclosed in the present application. An example apparatus includes a register configured to store impedance calibration information and further ...  
WO/2018/103883A1
The present invention relates to a storage device for secure authentication, comprising a mass data memory and a security element which enables the secure authentication of a storage device in the presence of further hardware components ...  
WO/2018/104699A1
Broadly speaking, embodiments of the present techniques provide apparatus and methods for generating a reference current for a memory array sensing scheme, and for using the generated reference current to sense the state of memory cells ...  
WO/2018/106458A1
A high-density neural network array. In an exemplary embodiment, an apparatus includes a three-dimensional (3D) structure having a plurality of layers forming a neural network. Each layer comprises one or more conductors forming neurons ...  
WO/2018/106866A1
Techniques efficiently assist in performing write operations in memories with resistive bit lines. A memory can comprise memory cells associated with respective word lines and bit lines. A write assist component can be associated with a ...  
WO/2018/104745A1
A method for controlling a playback tempo of an audio track to be presented at an audio output, the audio track comprising a plurality of audio components, a first audio component of the plurality of audio components being associated wit...  
WO/2018/106303A1
A memory device and associated techniques provide a read recovery of data in case of a short circuit between word lines. When cells of a recovery word line WLrec are successfully programmed but cells of an adjacent work line WLrec+1 are ...  
WO/2018/102876A1
Non-volatile Resistive RAM devices are described prepared using various nanocube dispersions and dispersion based deposition techniques including ink-jet printing. Stretchable Resistive RAM devices are described that retain their switchi...  
WO/2018/103420A1
The present invention relates to a method and system for storing an audio file. The method comprises: when a playing apparatus is playing audio data transmitted by a terminal storing an audio file, synchronously performing PCM sampling o...  
WO/2018/106372A1
The apparatus provided includes a memory. The memory is configured to receive a memory clock. The apparatus also includes a single stage logic gate configured to generate the memory clock from a reference clock. The memory clock is a gat...  
WO/2018/106565A1
Magnetic keys having a plurality of magnetic plates are disclosed. The location and orientation of the magnetic plates are controlled to generate magnetic fields that are of sufficient strength to be reliably read and sufficient complexi...  
WO/2018/101096A1
The present invention addresses the problem of providing an output device, which can reduce the impact on an object to which power is supplied even when an output unit continuously fails to supply a voltage. To solve the problem a brake ...  
WO/2018/102557A1
Systems, methods and devices are disclosed that may a user to specify various layout and operational parameters of a resistive-based memory array in a manner that accommodates the unique characteristics of resistance-based memory cells a...  
WO/2018/102079A1
Systems and methods for cache invalidation, with support for different modes of cache invalidation include receiving a matchline signal (208) indicating whether there is a match between a search word and an entry of a tag array (202) of ...  
WO/2018/100363A1
Memory address translation apparatus comprises page table access circuitry to access a page table to retrieve translation data defining an address translation between an initial memory address in an initial memory address space, and a co...  
WO/2018/100331A1
Storage circuitry (64) comprises an array (32) of storage locations (34) arranged in rows and columns, a row buffer (36) comprising a plurality of entries (68) each to store information from a storage location at a corresponding column o...  
WO/2018/100882A1
A disc storage device, provided with: a case capable of storing N rows of M disc-shaped recording mediums which have been stacked (where N and M are positive integers equal to or greater than 2), the case having an opening on the upper s...  
WO/2018/102666A1
A circuit device formed from a functional substrate. The circuit device (100) comprises a functional substrate component (104) and printed electronic elements (102) formed on the functional substrate component. The printed electronic ele...  
WO/2018/101028A1
This spin current magnetization reversal element comprises a first ferromagnetic metal layer having a variable direction of magnetization; and a spin-orbit torque wire that bonds to the first ferromagnetic metal layer and extends in a di...  
WO/2018/102001A1
A memory device and associated techniques provide a uniform erase depth for different blocks of memory cells which are at different distances from pass gates of a voltage source. In one approach, a voltage of a source side select gate tr...  
WO/2018/100790A1
A neuron circuit comprising: an input terminal to which spike signals are input in chronological order; a first switch element with one end connected to the input terminal and the other end connected to an intermediate node, the first sw...  
WO/2018/100954A1
Provided is a data writing device of a resistance variable memory element with which it is possible to perform writing with a low amount of writing energy using a simple circuit. The data writing device of a resistance variable memory el...  
WO/2018/100244A1
A method comprising: causing analysis of a portion of a visual scene; causing modification of a first sound object to modify a spatial extent of the first sound object in dependence upon the analysis of the portion of the visual scene co...  
WO/2018/097261A1
The present invention provides a method for polishing a glass substrate, which is capable of maintaining a polishing rate that is higher than ever before for a long period of time in a glass substrate polishing process wherein cerium oxi...  
WO/2018/097942A1
The disclosure relates to minimizing power consumption of a WiFi system-on-chip (SOC) during idle periods. The disclosed architecture includes memory banks for the WiFi SoC's embedded processor that can be independently powered on/off an...  
WO/2018/097911A1
A method of forming a memory device includes forming a first layer of conductive material having opposing upper and lower surfaces, forming a layer of amorphous silicon on the upper surface of the first layer of conductive material, stri...  
WO/2018/097940A1
The disclosure relates to minimizing power consumption of a WiFi system-on- chip (SOC) during idle periods. The disclosed architecture includes memory banks for the WiFi SoC's embedded processor that can be independently powered on/off a...  
WO/2018/094728A1
Embodiments of the present application relate to the field of power supplies, and provide a dynamic power circuit and a chip. The circuit comprises: a power gating tube circuit, a first drive circuit, a power control tube circuit, and a ...  
WO/2018/097055A1
A problem to be addressed by the present invention is to shorten the distance between a first magnetic gap and a second magnetic gap. Provided as a solution to the problem is a magnetic head (1) for paper currency identification, which i...  
WO/2018/096779A1
The purpose of the present invention is, in recording a high-quality broadcast video signal on a disc, to allow a disc storing a high-quality video signal to be reproduced at the optimum rotation speed for the disc. The purpose is achiev...  
WO/2018/097941A1
The disclosure relates to minimizing power consumption of a WiFi system-on-chip (SOC) during idle periods. The disclosed architecture includes memory banks for the WiFi SoC's embedded processor that can be independently powered on/off an...  
WO/2018/092245A1
The purpose of the present invention is to provide a program or the like that facilitates obtaining additional document data or live performance data for the same performance separate from document data or live performance data that is a...  
WO/2018/092547A1
The present invention provides an aluminum alloy substrate for a magnetic disc and a method of manufacture therefor, the aluminum alloy substrate for a magnetic disc containing Mg: 2.0 to 10.0 mass% (hereinafter simply described as "%"),...  
WO/2018/092611A1
Provided is high-speed, large-scale, non-volatile skyrmion flash memory that has low power consumption, that does not result in erroneous writing, and that comprises a circuit having good detection sensitivity of stored data. In addition...  
WO/2018/093284A1
´╗┐Long term optical memory includes a storage medium composed from an array of silicon nanoridges positioned onto the fused silica glass. The array has first and second polarization contrast corresponding to different phase of silicon. ...  
WO/2018/092610A1
Provided is high-speed, large-scale, non-volatile skyrmion random accessory memory that prevents erroneous writing and erroneous erasing, that comprises a circuit having good detection sensitivity of stored data, that results in little l...  
WO/2018/094416A1
An apparatus and method for memory backup are disclosed as being operational at a memory module that includes a volatile memory device but which is devoid of a non-volatile memory device. The memory module can emulate operations of a non...  
WO/2018/093601A1
In an aspect of the disclosure, an apparatus is provided. In one aspect, the apparatus is a memory controller that includes a logic circuit configured to generate a select signal for selecting between first and second ports of a memory a...  
WO/2018/093375A1
Systems and methods for performing fast-access playback operations are provided. A viewing history is stored that includes a plurality of play positions within a media asset that are associated with user interactions. A user request is r...  
WO/2018/093750A1
An optical storage system includes an optical head configured to split a light beam into a higher power main beam and at least one lower power side beam. The optical storage system also includes a controller configured to alter an optica...  
WO/2018/088563A1
Provided is a glass for magnetic recording medium substrates, which is an amorphous oxide glass that has, in mol%, an SiO2 content of 45-68%, an Al2O3 content of 5-20%, a total content of SiO2 and Al2O3 of 60-80%, a B2O3 content of 0-5%,...  
WO/2018/087630A1
A highly reliable semiconductor device is provided. A memory cell includes a first transistor and a second transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor. The ...  
WO/2018/089937A1
Disclosed is a resistive random access memory (RRAM). The RRAM includes a bottom electrode made of tungsten and a switching layer made of hafnium oxide disposed above the bottom electrode, wherein the switching layer includes a filament ...  
WO/2018/089064A1
An apparatus comprising is disclosed. The apparatus a driver circuit configured to selectively provide a first supply voltage to an output node in a first operating mode and to selectively provide a second supply voltage to the output no...  
WO/2018/088297A1
A semiconductor circuit according to the present invention comprises: a first circuit that generates the inverted voltage for the voltage at a first node and can apply the inverted voltage to a second node; a second circuit that generate...  
WO/2018/089936A1
Disclosed is a resistive random access memory (RRAM). The RRAM includes a bottom electrode made of tungsten and a switching layer made of hafnium oxide disposed above the bottom electrode, wherein the switching layer includes a switchabl...  
WO/2018/088137A1
The present invention provides a semiconductor storage device with a dual-port SRAM cell that has a small area while allowing low current consumption and securing an ample static noise margin. The semiconductor storage device includes a ...  

Matches 301 - 350 out of 855,529