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Patent Searching and Data


Matches 401 - 450 out of 861,271

Document Document Title
WO/2020/083367A1
A chip testing method, device, electronic apparatus, and computer readable medium are provided, relating to the field of chip testing. The method includes: determining a language rule of a chip to be tested; determining product and timin...  
WO/2020/084407A1
The present invention reduces the power used by a semiconductor device. The present invention is a semiconductor device having a latch circuit formed by a dynamic circuit. The latch circuit has: a first circuit having a decoding function...  
WO/2020/026030A3
A method for accessing a dynamic memory module, the method may include (i) receiving, by a memory controller, a set of access requests for accessing the dynamic memory module; (ii) converting the access requests to a set of commands, whe...  
WO/2020/086121A1
An apparatus may include a delay line that receives a command signal and provides a delayed command signal. The apparatus may include an edge starter that provides a clock enable signal responsive, at least in part, to a change in level ...  
WO/2020/085325A1
This cartridge memory is used for a recording medium cartridge and comprises: an antenna part that induces induction voltage by electromagnetic conduction; a load modulation unit in which the size of a load is variable; and a control uni...  
WO/2020/086213A1
A dynamic temperature compensation trim for use in temperature compensating a memory operation on a memory call of a memory component. The dynamic temperature compensation trim is based on a temperature of the memory component and based ...  
WO/2020/086239A1
Methods, systems, and devices for controlled and mode-dependent heating of a memory device are described. In various examples, a memory device or an apparatus that includes a memory device may have circuitry configured to heat the memory...  
WO/2020/082453A1
A method for intelligently adjusting a reference voltage in a flash memory device, comprising the following steps: step I, first initializing the order of reference voltage parameters; step II, determining whether an error occurs in mate...  
WO/2020/085328A1
Provided is a cartridge memory used in a magnetic tape cartridge, the cartridge memory including: an antenna section; a storage unit for storing data; and a control unit that reads data from the storage unit in response to a request from...  
WO/2019/168620A3
The subject disclosure relates to the de-interleaving of captured game data for the creation of separate video data and statistical metadata repositories. In some aspects, a process of the disclosed technology includes steps for capturin...  
WO/2020/084826A1
A cartridge pertaining to the present technology is provided with a cartridge case and a memory. The cartridge case houses a magnetic tape. The memory is disposed in the cartridge case and stores information obtained at the time of recor...  
WO/2020/086195A1
A memory device includes a plurality of input/output (I/O) nodes, a circuit, a latch, a memory, and control logic. The plurality of I/O nodes receive a predefined data pattern. The circuit adjusts a delay for each I/O node as the predefi...  
WO/2020/083275A1
Provided are a shift register unit, a gate driving circuit, a display device and a driving method. The shift register unit comprises a blanking input circuit, a display input circuit, an output circuit and a first control circuit. The bl...  
WO/2020/086771A1
Methods, apparatus, systems and articles of manufacture are disclosed to adjust audio playback settings based on analysis of audio characteristics. Example apparatus disclosed herein include an equalization (EQ) model query generator to ...  
WO/2020/086228A1
Methods, systems, and devices for multi-level receivers with various operating modes (e.g., on-die termination mode, termination-off mode, etc.) are described. Different modes may be utilized for receiving different types of signaling ov...  
WO/2020/082023A1
A Re RAM device manufactured using 2-D Si2Te3(silicon telluride) nanowires or nanoplates. The SiaTeg nanowires exhibit a unique reversible resistance switching behavior driven by an applied electrical potential, which leads to switching ...  
WO/2020/077914A1
Disclosed are an image processing method and apparatus, and a hardware apparatus. The image processing method comprises: acquiring an audio and preprocessing the audio to obtain audio attribute data concerning the audio at each first tim...  
WO/2020/081243A1
Memory devices for embedded applications are described. A memory device may include an array of memory cells having a first area and configured to operate at a first voltage, and circuitry having a second area that at least partially ove...  
WO/2020/081539A1
Systems, methods, and apparatuses for offset cancellation are described. A memory device may determine that a channel is in a state that interrupts an active termination of the channel and enable the calibration of a reference voltage (e...  
WO/2020/081193A1
Embodiments described herein include apparatuses and methods for memory device processing. More specifically, an example apparatus includes a memory device comprising a plurality of banks of memory cells. A particular bank of memory cell...  
WO/2020/079357A1
The representation is controlled by a time bar. The method implemented by the equipment comprises steps of: — displaying the time bar, the time bar comprising a cursor and a round curve rotated toward the edge of the screen closest to ...  
WO/2020/079676A1
Presented herein are methods and systems for generating intermediate code files adjusted to prevent return oriented programming exploitation, comprising receiving compiled intermediate code file(s) comprise a plurality of routines and ad...  
WO/2020/077518A1
A hybrid storage device (200) comprises: an interface (201), for electrically connecting the hybrid storage device (200) to an external device (802), and exchanging data with the external device (802); at least one storage channel (202),...  
WO/2020/081863A1
A dual-power-domain SRAM is disclosed in which the dual power domains may be powered up or down in whatever order is desired. For example, a (CX) power domain may be powered up first, followed by a memory (MX) power domain. Conversely, t...  
WO/2020/081169A1
Methods of operating a memory including applying an intermediate read voltage to a selected access line for a read operation, determining a value indicative of a number of memory cells of a plurality of memory cells connected to the sele...  
WO/2020/081872A1
A computer-implemented method for transforming audio-video data includes automatically detecting substantially all discrete human-perceivable messages encoded in the audio-video data, determining a semantic encoding for each of the detec...  
WO/2020/080639A1
An electronic device includes a foldable housing including a first surface and a second surface opposite to the first surface, a first display arranged on the first surface and configured to be flexible, a second display arranged in at l...  
WO/2020/081260A1
Methods, systems, and devices for performing memory command verification are described. A system may include a memory device and a memory controller, which may be external (e.g., a host device). The memory device may receive, from the me...  
WO/2020/081554A1
Playback devices, groups of playback devices, and methods of operating playback devices, and groupings thereof are provided, to cause the playback devices in a group of playback devices to play audio content together in synchrony, based ...  
WO/2020/081140A1
Numerous embodiments of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non- volatile memory cell within a vector-by- matrix multiplicat...  
WO/2020/078265A1
A data channel aging circuit, a memory, a data channel aging method, and a memory aging method are provided. The data channel aging circuit includes: a memory cell storing a voltage switching signal configured to provide a target voltage...  
WO/2020/080272A1
The purpose of the present invention is to compensate for the radiation resistance of a semiconductor memory. An apparatus (10) for compensating for radiation resistance comprises: a voltage value acquisition unit (11) that acquires a da...  
WO/2020/080363A1
Provided are an aluminum alloy plate for a magnetic disk, a method for manufacturing same, and a magnetic disk using same. The aluminum alloy plate is made of an aluminum alloy composed of 0.10-3.00 mass% of Fe, 0.003-1.000 mass% of Cu, ...  
WO/2020/077897A1
A GOA drive circuit (10) and a display panel, the GOA drive circuit consisting of a plurality of cascading GOA units (100), wherein a current level GOA unit (100) comprises: a pull-up control module (101), a pull-up module (102), a level...  
WO/2020/081131A1
A processing system (100) includes a memory controller (110) that preemptively exits a dynamic random access (DRAM) integrated circuit rank (115) from a low power mode such as power down mode based on a predicted time when the memory con...  
WO/2020/081262A1
Methods, systems, and devices for error correction management are described. A system may include a memory device that supports internal detection and correction of corrupted data, and whether such detection and correction functionality ...  
WO/2020/079514A1
A neuromorphic circuit (500) includes a crossbar synaptic array cell. The crossbar synaptic array cell includes a Complimentary Metal-Oxide-Semiconductor (CMOS) transistor (T6) having an on-resistance controlled by a gate voltage of the ...  
WO/2020/081459A1
Disclosed herein is an apparatus that includes a memory cell array including a plurality of memory cells, a first counter circuit configured to periodically update a count value during a first operation mode, a burst clock generator conf...  
WO/2020/080367A1
An integrated three-dimensional display body (10) is provided with, on a recording surface (14), a calculation element section (16) in which a phase component of light from each of light condensing points (Sn) of a reproduced image (40) ...  
WO/2020/081139A1
Numerous embodiments of an improved charge pump design are disclosed for generating the high voltages necessary to perform erase and program operations in non-volatile flash memory devices. In these embodiments, each boost stage in the c...  
WO/2020/077262A1
A method and system may provide for interactive song generation. In one aspect, a computer system may present options for selecting a background track. The computer system may generate suggested lyrics based on parameters entered by the ...  
WO/2019/089127A3
Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write...  
WO/2020/077283A1
Error correcting memory systems and methods of operating the memory systems are disclosed. In some embodiments, a memory system includes: a data memory; an ECC memory; and a data scrubbing circuit electrically coupled to the ECC memory a...  
WO/2020/073691A1
A flash memory self-test method, a solid hard disk, and a storage device.On this basis, the present invention can trigger a flash memory to perform a self-test according to the working state of the flash memory, can adaptively adjust the...  
WO/2019/236168A3
The present disclosure is directed to a device, a method, and a non-transitory computer readable medium for determining a level of uncertainty of programmed states of memory cells. In one aspect, a memory device includes memory cells, an...  
WO/2020/076159A1
An Circuit (21) arranged for providing a delayed output signal (OUT) from an input signal (IN), wherein the circuit comprises n (4) branches in a sequence of branch 1 to n (4),each having an input and an output, wherein each branch (Bran...  
WO/2020/073916A1
An encryption method for a storage device, applied to a near-field communication (NFC) storage device, the method comprising: acquiring a state indication of an NFC storage device (101); when the state indication indicates that the NFC s...  
WO/2020/076634A1
This disclosure provides a system and method for deploying and configuring a cyber-security protection solution using a portable storage device. The portable storage device may include a memory storing instructions to be executed by a co...  
WO/2020/073466A1
The present application relates to the technical field of electronics, and provides a wireless charging storage device and system. The wireless charging storage device comprises a charging unit, a data read/write unit, and a data storage...  
WO/2020/076986A1
Memory devices and methods of operating memory devices in which refresh management operations can be scheduled on an as-needed basis for those memory portions where activity fe.g., activations in excess of a predetermined threshold) warr...  

Matches 401 - 450 out of 861,271