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Patent Searching and Data


Matches 401 - 450 out of 844,326

Document Document Title
WO/2016/141060A1
A memory device comprises a semiconductor substrate with memory (16) and logic device areas (18). A plurality of memory cells are formed in the memory area, each including first source and drain regions with a first channel region thereb...  
WO/2016/137739A2
The present application is directed to new methods for automatically determining several characteristics of frames in a video sequence and automatically recommending or preparing image output products based on those frame characteristics...  
WO/2016/137670A1
An apparatus includes a static random-access memory (SRAM) and circuitry configured to initiate a correct action. The corrective action may be initiated based on a number of SRAM cells that have a particular state responsive to a power-u...  
WO/2016/137683A3
Dynamic tag compare circuits employing P-type Field-Effect Transistor (PFET)-dominant evaluation circuits for reduced evaluation time, and thus increased circuit performance, are provided. A dynamic tag compare circuit may be used or pro...  
WO/2016/137449A1
In one example in accordance with the present disclosure a method of determining a resistance state of a memristor in a crossbar array is disclosed. In the method, a combined reference-sneak current is determined based on a reference vol...  
WO/2016/137503A1
An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power...  
WO/2016/136518A1
A multilayer film which is obtained by providing at least one surface of a polyester film with a resin layer, and which is characterized in that: the reflectance of the surface of the resin layer at a wavelength of 550 nm is 6.0% or more...  
WO/2016/136528A1
The present invention realizes a shift register circuit that enables a display device to achieve higher definition with as small a number of elements as possible without causing a malfunction. A unit circuit is provided with: a thin film...  
WO/2016/137685A2
Read-assist circuits for memory bit cells employing a P-type Field-Effect Transistor (PFET) read port(s) are disclosed. Related memory systems and methods are also disclosed. It has been observed that as node technology is scaled down in...  
WO/2016/137734A2
A semiconductor device for a one-time programmable (OTP) memory according to some examples of the disclosure includes a gate, a dielectric region below the gate, a source terminal below the dielectric region and offset to one side, a dra...  
WO/2016/137681A3
P-type Field-effect Transistor (PFET)-based sense amplifiers for reading PFET pass-gate memory bit cells ("bit cells") are disclosed. Related methods and systems are also disclosed. Sense amplifiers are provided in a memory system to sen...  
WO/2016/137739A3
The present application is directed to new methods for automatically determining several characteristics of frames in a video sequence and automatically recommending or preparing image output products based on those frame characteristics...  
WO/2016/137889A1
The present disclosure provides a method, apparatus, and computer-readable medium for managing data. A method includes creating, by a first user equipment (UE), a data, and transferring, by the first UE, the data to a server. The method ...  
WO/2016/137760A1
Memory subsystem refresh management enables commands to access one or more identified banks across different bank groups with a single command. Instead of sending commands identifying a bank or banks in separate bank groups by each bank ...  
WO/2016/136748A1
The objective of the present invention is to provide a management system with which it is possible to reduce the required capacity of a storage device, even if the number of events that occur increases, and in which said required capacit...  
WO/2016/137446A1
In one example in accordance with the present disclosure a method of determining a state of a memristor in a crossbar array is described. In the method a bias voltage is applied to a target row line in the crossbar array, which bias volt...  
WO/2016/137402A1
A method for data stripping, allocation and reconstruction in an active drive storage system including a plurality of active object storage devices, each of the plurality of active object storage devices including one or more storage dev...  
WO/2016/137717A1
A memory chip for dynamic approximate storage includes an array of memory cells associated with at least two regions. The chip further includes at least one threshold register for storing values for thresholds for memory cells correspond...  
WO/2016/137681A2
P-type Field-effect Transistor (PFET)-based sense amplifiers for reading PFET pass-gate memory bit cells ("bit cells") are disclosed. Related methods and systems are also disclosed. Sense amplifiers are provided in a memory system to sen...  
WO/2016/138457A1
Compounds useful as fluorescent or colored dyes are disclosed. The compounds have the following structure (I), including salts thereof, wherein R1a, R1b, R1c, R1d, R1e, R1f, R2a, R2b, R2c, R2d, R2e, R2f, R2g, R2h, R2i, R2j, x and y are a...  
WO/2016/137678A1
Write-assist circuits for memory bit cells ("bit cells") employing a P-type Field-Effect transistor (PFET) write port(s) are disclosed. Related methods and systems are also disclosed. It has been observed that as node technology is scale...  
WO/2016/136118A1
The present invention provides a magnetic recording medium capable of achieving high density recording by decreasing the bit transition width during the process of heat-assisted recording on a heat-assisted magnetic recording medium. The...  
WO/2016/137685A3
Read-assist circuits for memory bit cells employing a P-type Field-Effect Transistor (PFET) read port(s) are disclosed. Related memory systems and methods are also disclosed. It has been observed that as node technology is scaled down in...  
WO/2016/137683A2
Dynamic tag compare circuits employing P-type Field-Effect Transistor (PFET)-dominant evaluation circuits for reduced evaluation time, and thus increased circuit performance, are provided. A dynamic tag compare circuit may be used or pro...  
WO/2016/137679A1
Write-assist circuits for memory bit cells ("bit cells") employing a P-type Field-Effect transistor (PFET) write port(s) are disclosed. Related methods and systems are also disclosed. It has been observed that as node technology is scale...  
WO/2016/137546A1
Apparatus and methods implemented therein use an ECC procedure to verify and correct errors in data corresponding to pre-programmed configuration data. Verification and correction is performed in a memory system comprising a non¬¨ volati...  
WO/2016/137716A3
A method of encoding data on single level or variable multi-level cell storage includes receiving a block of encoded data from an approximation-aware application and at least an importance attribute associated with the block of encoded d...  
WO/2016/138317A1
Apparatus, methods, and systems for use in providing tangential (linear) tracking of a stylus on a record during play. In some embodiments, a tonearm assembly includes a tonearm with a laser emission source mounted thereto, and a receive...  
WO/2016/135801A1
The present invention employs a suitable filter shape for equalization when reproducing a high-density recorded hologram to thereby minimize the scale of the circuit without degrading the performance of the equalization. An optical infor...  
WO/2016/137545A1
A non-volatile storage system includes a plurality of non-volatile storage elements arranged in two dimensional or three dimensional structures. The system applies programming to the non-volatile storage elements and performs verificatio...  
WO/2016/137720A1
A memory device that includes a plurality of ROM cells each having spaced apart source and drain regions formed in a substrate with a channel region therebetween, a first gate disposed over and insulated from a first portion of the chann...  
WO/2016/135941A1
A photosensitive holographic medium, on being irradiated with light for reproduction, converts an unreacted monomer therein into a photopolymerizable monomer. Therefore, the recording quality of a holographic medium may deteriorate when ...  
WO/2016/134415A1
A method of generating video data on a portable electronic device, the method including steps of: the portable electronic device accessing pre-generated data representing a pre-generated video synchronized with pre-generated audio; the p...  
WO/2016/137680A1
Write-assist circuits for memory bit cells ("bit cells") employing a P-type Field-Effect transistor (PFET) write port(s) are disclosed. Related methods and systems are also disclosed. It has been observed that as node technology is scale...  
WO/2016/138121A1
A system and method for creating a sports video may include receiving video of a sporting event inclusive of players with unique identifiers on their respective uniforms. At least one unique identifier of the players in the video may be ...  
WO/2016/137734A3
A semiconductor device for a one-time programmable (OTP) memory according to some examples of the disclosure includes a gate, a dielectric region below the gate, a source terminal below the dielectric region and offset to one side, a dra...  
WO/2016/135887A1
A front end (FE) unit manages, as disc replaced/non-replaced information, whether a disc is replaced or not during a period from a time when start-up of the FE unit is completed to a time when start-up of a back end (BE) unit is complete...  
WO/2016/135585A1
A technique for sensing a data state of a data cell. A comparator has a first input at a node A and a second input at a node B. A first n-channel transistor is connected to a first p-channel transistor at the node A. A second n-channel t...  
WO/2016/133866A1
Described examples include a data retention reliability screen (45) of integrated circuits including ferroelectric random access memory (FRAM) arrays. Sampled groups of cells in the FRAM array are tested at various reference voltage leve...  
WO/2016/134011A1
In one aspect of the invention, the memristor includes a monolayer film formed of an atomically thin material, where the monolayer film has at least one grain boundary (GB), a first electrode and a second electrode electrically coupled w...  
WO/2016/133047A1
The present invention is a sputtering target comprising a Co-containing alloy and boron and/or an oxide of boron, the sputtering target being characterized in that the metal boron in boron oxide (B2O3) that dissolves into water is 7000 ¬...  
WO/2016/133677A2
A method of forming an electronic device includes forming an oxygen scavenging layer proximate to a dielectric layer in a gate region of a field effect transistor (FET). The interface layer is between the dielectric layer and a substrate...  
WO/2016/133661A1
In one embodiment, a semiconductor memory device includes a plurality of resistive switching memory cells, where each resistive switching memory cell can include: (i) a programmable impedance element having an anode and a cathode; (ii) a...  
WO/2016/133869A1
Described examples include a method of setting the reference voltage for sensing data states in integrated circuits including ferroelectric random access memory (FRAM) cells of the one-transistor-one capacitor (1T-1C) type. In an electri...  
WO/2016/133677A3
A method of forming an electronic device includes forming an oxygen scavenging layer (230) proximate to a dielectric layer (204) in a gate region of a field effect transistor (FET). An interface layer (214) is between the dielectric laye...  
WO/2016/133611A1
A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an in...  
WO/2016/133930A1
An MTP (Many Times Programmable) memory cell for integrated circuit memory arrays is described. The cell includes an MTP device and a thyristor interconnected so that the MTP device triggers the thyristor to turn on during a Read or Veri...  
WO/2016/131733A1
A sensor interface (10) for interfacing with a sensor (12,14) such as an electrochemical sensor (12), a temperature sensor (14) or the like in which the sensor interface comprises a memory configured to store data received at the sensor ...  
WO/2016/132836A1
The objective of the present invention is to make it possible to acquire image attribute information from a transport stream (TS) file and execute a process corresponding to the acquired attributes. A data processing unit acquires image ...  
WO/2016/133705A1
The disclosed embodiments comprise a flash memory device that can be configured to operate as a read only memory device. In some embodiments, the flash memory device can be configured into a flash memory portion and a read only memory po...  

Matches 401 - 450 out of 844,326