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Matches 401 - 450 out of 857,375

Document Document Title
WO/2019/002179A1
Methods, systems, and computer program products for synchronizing audio signals captured by multiple independent devices during an audio event are described. Multiple recording devices, e.g. several smartphones, record the audio event. A...  
WO/2019/003959A1
An aspect of the present invention provides a polishing liquid composition capable of enhancing polishing speed and reducing short-wavelength undulation after polishing. An aspect of the present invention relates to a polishing liquid co...  
WO/2019/003037A1
Provided is a semiconductor device which is capable of holding a signal detected by a sensor element. This semiconductor device is provided with a sensor element, a first transistor, a second transistor, and a third transistor, wherein o...  
WO/2019/005019A1
Cross-point ferroelectric memory arrays, and methods of fabricating cross-point ferroelectric memory arrays, are described. In an example, an integrated circuit structure includes a first plurality of conductive lines along a first direc...  
WO/2019/004275A1
One embodiment of the present invention is an organofluorine compound represented by the general formula (R-π-E-CH2-A-CH2-E')n-π'-G … (1B) (where n is an integer of 2-5, A is a divalent perfluoropolyether group, π is an arylene grou...  
WO/2019/001711A1
The invention relates to an apparatus (1) for producing an n-layer optical information carrier, which apparatus has an injection molding unit (10) for producing a carrier body having a first information layer; and a first embossing unit ...  
WO/2019/006037A1
Reverse pulse schemes for reducing write error rate in magnetoelectric random access memory applications can be implemented in many different ways in accordance with various embodiments of the invention. One embodiment includes a method ...  
WO/2019/005129A1
A spin Hall effect magnetoresistive random-access memory cell includes first and second access transistors in a device level of a semiconductor device, a wordline in the device level and coupled to gate terminals of the first and second ...  
WO/2019/004161A1
One embodiment of the present invention is a silica slurry for a polishing-liquid composition, said slurry comprising silica particles, a redispersion aid and water, the redispersion aid being an alkali thickening polymer emulsion, and t...  
WO/2019/000054A1
Embodiments involve harmonising one or more geographically or temporally distributed renditions with at least one backing clip, comprising a calibration module for selecting a parameter of one or more aural or visual characteristics of t...  
WO/2018/236937A1
A memory structure includes a semiconductor substrate, a first stack of active strips and a second stack of active strips formed over the semiconductor substrate, a storage layer, and a plurality of conductors each extending lengthwise a...  
WO/2018/236878A1
Systems and methods are disclosed for managing the operation of a plant, such as a chemical plant or a petrochemical plant or a refinery, and more particularly for enhancing system performance of a catalyzed reaction system by, among oth...  
WO/2018/233241A1
An installation frame (1) is provided with a first accommodation portion (11), an inclined insertion opening (13), a second accommodation portion (12), a horizontal insertion opening (14), and a positioning member (15), wherein the posit...  
WO/2018/236443A1
Disclosed herein are printed circuit boards (PCBs) (100) with patterned ground structure filters and data storage devices comprising such PCBs. Each PCB comprises a resonator (120) having an L-shape or a zig-zag shape in a plane of the p...  
WO/2018/236869A1
Systems and methods are disclosed for detecting temperature excursion in a chemical plant or petrochemical plant or refinery. Aspects of the disclosure provide an enhanced control system for a reactor, such as in hydroprocessing. The enh...  
WO/2018/232766A1
A memory (300) and a data writing method. The memory (300) comprises a memory cell array (310) and a controller (320). The memory cell array (310) comprises M rows × N columns of memory cells, M word lines, and N bit line pairs. Each of...  
WO/2018/236435A1
A hermetically-sealed container for one or more data storage devices may include a base having grooves, and corresponding sidewalls disposed within each groove, with an adhesive disposed within each groove and bonding each sidewall to th...  
WO/2018/236439A1
Provided herein are systems and apparatus for reducing vibration interaction between hard drives. In one implementation, a flexible mount electrical connection comprises a mating connector configured to physically couple with a hard driv...  
WO/2018/235011A1
Embodiments of the present invention provide a tape transport control system with enhanced regulation of tape tension and velocity over the entire length of the tape. The tape transport control system comprises of circuitry adapted to ou...  
WO/2018/236786A1
An ultrasound device is describe in which analog ultrasonic transducer output signal are directly converted to digital signals. The ultrasound device includes microfabricated ultrasonic transducers directly coupled to a sigma delta analo...  
WO/2018/236434A1
A data storage system includes multiple hermetically-sealed enclosures containing a lighter-than air gas, multiple data storage devices housed in each enclosure and containing the lighter-than-air gas, a tray pneumatic control system eac...  
WO/2018/237272A1
Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips. Each of the plurality of chips further includes a terminal coupled to the resist...  
WO/2018/234920A1
A memory device includes a non-volatile random access memory. The non-volatile memory includes a suspect bit register configured to store addresses of bits that are determined to have had errors. The non-volatile memory further includes ...  
WO/2018/231423A1
Systems, apparatuses, and methods related to dynamic random access memory (DRAM), such as finer grain DRAM, are described. For example, an array of memory cells in a memory device may be partitioned into regions. Each region may include ...  
WO/2018/230466A1
Provided is a ferromagnetic tunnel junction which, as a tunnel barrier layer disposed between a first magnetic layer and a second magnetic layer, is an oriented crystal body having a laminated structure of a first insulating layer and a ...  
WO/2018/231410A1
A method to integrate silicon-oxide-nitride-oxide-silicon (SONOS) transistors into a complementary metal-oxide-semiconductor (CMOS) flow including a triple gate oxide structure. The memory device may include a non-volatile memory (NVM) t...  
WO/2018/229332A1
An arrangement (100), optionally comprising one or more network accessible servers, for searching for digital video material, wherein the arrangement comprises at least one processor (102) configured to receive a number of video items: s...  
WO/2018/227901A1
A vertically magnetized MTJ device and an STT-MRAM. The vertically magnetized MTJ device comprises a reference layer (2), an insulation barrier layer (3), a free layer (4), an enhancing layer (5), a demagnetization coupling layer (6) and...  
WO/2018/231299A1
A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation for memory cells in a string. During the erase operation, a channel gradient near the select gate transistors is reduced when...  
WO/2018/231981A1
A method and apparatus for quantitatively characterizing performance of a laser steering galvanometer mirror directs a laser beam from a calibration "sensor" onto a side region of the mirror to directly determine rotational positioning, ...  
WO/2018/231482A1
Logic integrated with a memory and related methods for performing background functions are provided. A method in a memory includes, in response to a request from a host separate from the memory, initiating processing of a background func...  
WO/2018/227408A1
A hard disk box, comprising a housing (10), a fixing support (20), shock absorbers (30), and a lower cover (40); the outer sides of two opposite first side plates (22) of the fixing support (20) are respectively provided with one shock a...  
WO/2018/231305A1
Systems and methods are described for predicting an endurance of groups of memory cells within a memory device, based on current characteristics of the cells. The endurance may be predicted by processing historical information regarding ...  
WO/2018/231298A1
A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation. A pre-charge operation occurs in which a channel voltage is increased to a positive level. This reduces a channel gradient w...  
WO/2018/231431A1
Methods and devices for compensating for detected motion when capturing an image may include determining at least one of a global movement of an imaging device and a local movement of one or more objects in a scene captured by the imagin...  
WO/2018/229590A1
Provided is a semiconductor device that performs error detection and correction on multi-valued data. This semiconductor device comprises a first gray code conversion circuit, a second gray code conversion circuit, a gray code reverse co...  
WO/2018/230366A1
The present technique relates to a signal processing device and method, and a program for enabling a decrease in processing load while ensuring safety. The signal processing device is provided with: a control unit which acquires designat...  
WO/2018/231556A1
An integrated circuit comprising an array of logic tiles, arranged in an array of rows and columns. The array of logic tiles includes a first logic tile to receive a first external clock signal wherein each logic tile of a first pluralit...  
WO/2018/231399A1
A memory device and method of operating the same are disclosed. Generally, the device includes an array of Ferro-electric Random Access Memory cells. Each cell includes a first transistor coupled between a bit-line and a storage node (SN...  
WO/2018/227878A1
A chip burner for burning a chip, comprising: a base, on which a burning tray is fixed; a plurality of burning grooves which are fixed on the burning tray; a plurality of latching members, each of the plurality of latching members being ...  
WO/2018/231313A1
Apparatuses, systems, methods, and computer program products are disclosed for a multicore on-die memory controller 150. An integrated circuit device 123, 212, 700 includes an array of non-volatile memory cells 200 and a microcontroller ...  
WO/2018/227174A1
A data security apparatus includes an analog component. The analog component operates internally with a high degree of entropy. This high degree of entropy resides in the interactions between its internal components in response to an ext...  
WO/2018/226478A1
Methods, systems, and devices for dual mode ferroelectric memory cell operation are described. A memory array or portions of the array may be variously operated in volatile and non-volatile modes. For example, a memory cell may operate i...  
WO/2018/225993A1
According to an embodiment, a phase-change memory device comprises: an upper electrode and a lower electrode; a phase-change layer in which a crystal state thereof is changed by heat supplied by the upper electrode and the lower electrod...  
WO/2018/226280A1
Disturbs are reduced during programming and read operations for drain-side memory cells in a string by controlling dummy word line portions separately in selected and unselected sub-blocks. One or more of the dummy word line layers are s...  
WO/2018/224928A1
A magnetic tunnel junction (MTJ) storage element includes a reference layer, a tunnel barrier and a free layer on an opposite side of the tunnel barrier layer from the reference layer. The reference layer has a fixed magnetization direct...  
WO/2018/226179A1
The present invention relates to a multi-layer structure with a [NiMn / Co] content (Si/Pt (tPt) /Ni45Mn55 (tAFM) /Co (tFM)/ Pt (30A) ) formulation in which the spontaneous exchange shift effect (SEB) is observed. In this invention, a mu...  
WO/2018/226474A1
Methods, systems, and devices for time-based access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic state...  
WO/2018/226477A1
Techniques, systems, and devices for time-resolved access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic...  
WO/2018/226021A1
One embodiment provides a method comprising identifying a product placement opportunity for a product in a frame of a piece of content during playback of the piece of content on a display device. The method further comprises determining ...  

Matches 401 - 450 out of 857,375