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Patent Searching and Data


Matches 401 - 450 out of 857,845

Document Document Title
WO/2019/045794A1
A semiconductor device includes a clock gating tree comprising a first clock gating stage and a second clock gating stage. The first clock gating stage is configured to receive an activate detection signal and to activate clocking events...  
WO/2019/041584A1
A scanning driving circuit (20, 701) for a light emitting diode display, and a display panel (70). The scanning driving circuit (20, 701) comprises a plurality of scanning driving units (30) in cascade connection; each stage of the scann...  
WO/2019/046013A1
Apparatuses and methods for providing active an inactive clock signals are disclosed. An example apparatus includes an input clock buffer and a clock divider circuit. The input clock buffer includes a receiver circuit configured to recei...  
WO/2019/046487A1
An apparatus may be designed to enable a user to receive, record, display, edit, arrange, re-arrange, play, loop, extend, export and import audio and video data. The audio and video data to be organized as, for example, but not limited t...  
WO/2019/045074A1
In the present invention, the surface roughness Rz of the outer peripheral edge of a spacer is set to 1.5 µm or greater. Thereby, when assembling a hard disc drive device, errors that may occur while pulling out a spacer using a grippin...  
WO/2019/045087A1
A method for making a semiconductor memory device comprising a plurality of memory cells for storing one or more data values, the method comprising: exposing a pattern on a wafer for creating structures for a plurality of memory cells fo...  
WO/2019/045785A1
Memory devices (10) may provide a communication interface that is configured to receive control signals, and/or address signals from user circuitry, such as a processor. The memory device (10) may receive and process signals employing di...  
WO/2019/045981A1
Methods of operating a memory include determining a target voltage level for an access line voltage, determining a target overdrive voltage level for gating the access line voltage to an access line coupled to a plurality of memory cells...  
WO/2019/042314A1
A shift register (100), a gate drive circuit (10), a display panel (1), and a driving method. The shift register (100) comprises: an input circuit (110), which is connected to a pull-up node (PU) and an input signal terminal (INPUT) resp...  
WO/2019/045784A1
One embodiment of the present disclosure describes a memory system that may include one or more memory devices that may store data. The memory devices may receive command signals to access the stored data as a loopback signal. The memory...  
WO/2019/045931A1
Devices and techniques for random access memory power savings are disclosed herein. Data contained in RAM is compressed in response to obtaining a trigger. Here, the RAM organized into several discrete hardware components with a correspo...  
WO/2019/044370A1
The present invention provides a card reader which, via a simple structure, is capable of detecting a skimming magnetic head attached to the front of a card insertion member provided with a card slot and a skimming magnetic head attached...  
WO/2019/045943A1
A variety of applications can include apparatus and/or methods of operating the apparatus that include a memory device having read levels that can be calibrated. A calibration controller implemented with the memory device can trigger a r...  
WO/2019/045795A1
A semiconductor device may include a plurality of memory banks, a plurality of mode registers that may control an operational mode associated with each of the plurality of memory banks, and a set of global wiring lines coupled to each of...  
WO/2019/046189A1
A memory array including a first memory cell including a first memory gate coupled to receive a first signal. The memory array including a second memory cell including a first memory gate coupled to receive a second signal. The magnitude...  
WO/2019/045913A1
Methods of operating a memory include determining a respective raw data value for each memory cell of a plurality of memory cells; determining the numbers of memory cells of a first subset of the plurality of memory cells having each raw...  
WO/2019/046029A1
In an exmaple, an apparatus includes a memory array separate from a semiconductor, a trigger device separate from the semiconductor and coupled to an access line in the memory array, a select device separate from the semiconductor and co...  
WO/2019/045806A1
A memory device and associated techniques for reducing charge loss in a select gate transistor. A dummy memory cell is weakly programmed using a hot electron injection type of disturb to reduce the movement of holes toward the adjacent s...  
WO/2019/041662A1
A DRAM test device, comprising: a test frame (101) for inserting a DRAM to be tested, a program storage module (102) for storing a test program, a current test module (103) and a test control module (104). The test control module (104) r...  
WO/2019/040501A1
Methods, systems, and devices for mitigating line-to-line capacitive coupling in a memory die are described. A device may include multiple drivers configured to both drive latched data and conduct read and write operations. For example, ...  
WO/2019/040891A1
Back gate biasing magneto-resistive random access memory (MRAM) bit cells to reduce or avoid write operation failures caused by source degeneration are disclosed. In one aspect, an MRAM bit cell includes a magnetic tunnel junction (MTJ) ...  
WO/2019/040304A1
Methods, systems, and devices for memory with a virtual page size are described. Memory cells may be accessed in portions or page sizes that are tailored to a particular use or application. A variable page size may be defined that repres...  
WO/2019/038848A1
The present invention addresses the problem that, in a system in which graphics are combined with a content video and then transmitted to a display device, the brightness of the graphics fluctuates due to dynamic metadata control. A vide...  
WO/2019/037457A1
Disclosed are a shift register, drive method thereof, drive control circuit, and display device. The shift register comprises: an input sub-circuit (1), a first control sub-circuit (2), a second control sub-circuit (3), a third control s...  
WO/2019/040138A1
A non-volatile storage apparatus is proposed that includes a plurality of serially connected non-volatile reversible resistance-switching memory cells, a plurality of word lines such that each of the memory cells is connected to a differ...  
WO/2019/040503A1
Self-referencing memory device, techniques, and methods are described herein. A self-referencing memory device may include a ferroelectric memory cell. The self- referencing memory device may be configured to determine a logic state stor...  
WO/2019/039200A1
Provided is a fluorinated ether compound, which can be used advantageously as a lubricant material for a magnetic recording medium, the lubricant material being capable of forming a lubricant layer having excellent chemical resistance an...  
WO/2019/038409A1
A superconducting logic element (1), comprising: a superconducting tunnel junction (10) comprising a first (20) and a second (30) superconductor; a first insulating ferromagnet (40) in contact with the first superconductor (20), configur...  
WO/2019/040951A1
A method for assisting a plurality of authors to generate a group video. The method comprises connecting a first electronic device of a first author with a server that provides communication among the plurality of authors; allowing the f...  
WO/2019/040871A1
The present invention solves the unmet need by providing a method for encoding and storing digital information in DNA or the sugar phosphate backbone of DNA or analogous structural mediums by use of expanded alphabet channels and derivat...  
WO/2019/039265A1
A fluorine-containing ether compound characterized by being represented by formula (1). R1–R2–CH2–R3–CH2–R4–R5 (1) (In formula (1), R3 indicates a perfluoropolyether chain. R2 and R4 indicate a divalent linking group having a...  
WO/2019/040403A1
The present disclosure includes apparatuses and methods related to sensing operations in memory. An example apparatus can perform sensing operations on an array of memory cells by applying a first signal to a first portion of the array o...  
WO/2019/040194A1
Numerous embodiments for an improved sense amplifier circuit for reading data in a flash memory cell are disclosed. The embodiments each compare current or voltage measurements from a data block with a reference block to determine the va...  
WO/2019/038618A1
A sense amplifier and a semiconductor device which are less likely to be influenced by a variation in transistor characteristics and their operation methods are provided. An amplifier circuit in a sense amplifier includes a first circuit...  
WO/2019/040811A1
A method for combining a plurality of video files with a tune and a recording medium storing an executable program for implementing the method. The method comprises transmitting a service request from an electronic device to a synchroniz...  
WO/2019/038649A1
An Apparatus and method for enhancing read performance in a two-dimensional magnetic recording (TDMR) system, including a grid defining a plurality of read elements, by timing recovery. The method can include the steps of filtering by a ...  
WO/2019/037020A1
Disclosed is a four-dimensional (4D: 3D+time) multi-plane broadband imaging system capable of recording 3D multi-plane multiple images in real time. The imaging system comprises: one or more non-reentry quadratically distorted (NRQD) gra...  
WO/2019/040256A1
Techniques for memory I/O tests using integrated test data paths are provided. In an example, a method for operating input/output data paths of a memory apparatus can include receiving, during a first mode, non-test information at a data...  
WO/2019/037706A1
The disclosure relates to technology for providing determined future fields of view (FoVs) of a 360 degree video stream in a network having multiple video streams corresponding to multiple FoVs. FoV interest messages including requests f...  
WO/2019/036593A1
In some examples of the disclosure, a parameter override mechanism may include a variable length configuration data table with entries for specific models of memory devices. The configuration data table entries may include override param...  
WO/2019/035391A1
The present disclosure includes a server apparatus, a recording method, a non-transitory computer-readable, and a system. In one example, the server apparatus includes a recording unit and a controller. The controller is configured to re...  
WO/2019/035390A1
The present disclosure includes an information processing apparatus, an information processing method, a non-transitory computer-readable medium, and a system. In one example, the information processing apparatus is a camera. The camera ...  
WO/2019/036071A1
A system includes multiple memory banks (12) that store data. The system also includes an address path (40) coupled to the memory banks (12) that provides a row address to the memory banks (12). The system further includes a command addr...  
WO/2019/033783A1
Provided are a shift register unit, a driving method, a gate driving circuit and a display apparatus. The shift register unit comprises: a pull-up node state maintaining circuit, connected to a pull-up node and an input end of a first co...  
WO/2019/036236A1
A script synchronization interface system is disclosed for synchronizing a script, shot properties, and one or more video files by mapping associated metadata. The script synchronization interface system includes an interactive script se...  
WO/2019/033823A1
A shift register unit, comprising a first output control circuit (10), a first output circuit (20), a second output control circuit (30), a second output circuit (40), a reset circuit (50), and a node setting circuit (60). The node setti...  
WO/2019/033441A1
Disclosed in the embodiments of the present invention are a sound volume adjustment method and apparatus, a mobile terminal, and a storage medium, the method comprising: when it is detected that a terminal device performs the playback of...  
WO/2019/036229A1
Apparatuses and methods for latching redundancy repair addresses at a memory are disclosed. An example apparatus includes block of memory including primary memory and a plurality of redundant memory units and repair logic. The repair log...  
WO/2019/036684A1
A method comprising the steps of responding to expiration of a timer, transmitting a signal from the timer to circuitry; responsive to receiving the signal, retrieving by the circuitry (i) first values stored in an analog array, and (ii)...  
WO/2019/034108A1
A method and device for storing video data applied to smart glasses. The method comprises: transmitting a pairing instruction to a mobile terminal; if the pairing between smart glasses and the mobile terminal is successful, receiving a v...  

Matches 401 - 450 out of 857,845