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WO/2019/136979A1 |
Disclosed is a bad block management method for increasing the available capacity of a storage device, wherein the available capacity of a flash memory storage system is related to the number of bad blocks, and the more the bad blocks, th...
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WO/2019/139836A1 |
A data storage system capable of switching a code rate based on a host command is disclosed. A controller of the data storage system may set a code rate in a data storage device to a first code rate for encoding data to be written to non...
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WO/2019/140074A1 |
Devices and techniques to recover data from a memory device using a custom Read Retry feature are disclosed herein. A memory device can receive a first read request, read data from the memory array corresponding to the read request, and ...
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WO/2019/138828A1 |
This semiconductor device is provided with: a first gate electrode comprising a first main wiring part which extends in a first active region of a semiconductor substrate in a first direction and divides the first active region into a fi...
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WO/2019/140361A1 |
An example device includes at least one processor configured to receive electrical parameter values corresponding to at least one first location within a power network. The at least one processor is further configured to determine, using...
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WO/2019/136980A1 |
A bad block processing method for a multi-channel memory system. A bad block processing mechanism is provided on flash memory devices of multiple data channels; by weeding bad blocks out of a block group and recombining available blocks ...
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WO/2019/139647A1 |
A device (10) includes a first terminal configured to receive a reference voltage, a second terminal configured to receive a weighted tap value (86), a local generator circuit (504, 506, 508, 510) configured to create a group (476, 478, ...
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WO/2019/136962A1 |
The present application discloses an audio conversion apparatus and a multi-sound system. The audio conversion apparatus comprises: a modem configured to convert a received audio signal into a power carrier signal or to convert a receive...
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WO/2019/136976A1 |
Disclosed is a method for using various error correction code combinations in a encoding and decoding system, comprising a computer, a master control chip and a plurality of storage assemblies, wherein the computer is connected to the ma...
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WO/2019/136972A1 |
Disclosed is a method for reducing the bit error rate of a flash memory. A flash memory control device and multiple flash memory chips are comprised, wherein the flash memory control device is connected to the multiple flash memory chips...
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WO/2019/140364A1 |
A memory controller includes a generator circuit configured to generate a predetermined pattern of data, an address input, and a memory interface circuit. The memory interface circuit is configured to write the predetermined pattern of d...
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WO/2019/136138A1 |
A cloud implementation of a persisted storage device, such as a disk, is provided. The implementation supports a variety of features and protocols, in full analogy with a physical storage device such as a disk drive. The present disclosu...
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WO/2019/135798A1 |
A device (10) includes a selection circuit (200) that is configured to generate a bias level (202). The device (10) also includes a combinational circuit (80) coupled to the selection circuit. The combinational circuit (80) is configured...
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WO/2019/135012A1 |
The invention relates to a method for the management of audio dubbing and voice-over production intended for audiovisual media, such that the presence of different dubbing actors is not required in the studio. The implementation of the m...
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WO/2019/135134A1 |
A technique relates to operating a memory controller. The memory controller drives first memory devices and second memory devices of the memory controller in a dual channel mode. A first error correcting code (ECC) memory device and a se...
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WO/2019/135523A1 |
The present invention relates to an electronic device, a control method therefor, and a computer program product. The electronic device comprises: a memory in which instructions are stored; and a processor executing the instructions so a...
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WO/2019/135325A1 |
An encoder includes a layered structure including a metal plate, a dielectric layer arranged on the metal plate, and a plurality of metallic components arranged on the dielectric layer to form a pattern of resonant circuits. The encoder ...
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WO/2019/135866A1 |
A memory device includes memory cells each configured to produce an output current during a read operation. Circuitry is configured to, for each of the memory cells, generate a read value based on the output current of the memory cell. C...
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WO/2019/135853A1 |
A pair of memory cells that includes first and second spaced apart trenches formed into the upper surface of a semiconductor substrate, and first and second floating gates disposed in the first and second trenches. First and second word ...
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WO/2019/135796A1 |
Holographic volume gratings in waveguide cells can be recorded using many different methods and systems in accordance with various embodiments of the invention. One embodiment includes a holographic recording system including at least on...
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WO/2019/135818A1 |
Disclosed is a memory system comprising a sense amplifier electrically coupled to a first bitline and a second bitline associated with a column of a memory array, a bl transistor electrically coupled to the first bitline, wherein the bl ...
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WO/2019/136175A1 |
Provided herein are compositions, devices, systems and methods for generation and use of biomolecule-based information for storage. Further provided are devices comprising addressable electrodes controlling polynucleotide synthesis (depr...
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WO/2019/135743A1 |
A memory device comprises an interconnect having a spin orbit torque (SOT) material. A magnetic tunnel junction (MTJ) device comprises a free layer magnet coupled to the interconnect, a reference fixed magnet, and a barrier material betw...
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WO/2019/134413A1 |
A shift register unit (300, 400, 500, 600, 700, 900), a gate drive circuit, a display device, and a control method (1200) for the display device. The shift register unit (300, 400, 500, 600, 700, 900) comprises an input sub-circuit (310,...
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WO/2019/134450A1 |
A shift register unit, a gate drive circuit, a display device and a drive method. The shift register unit comprises an input circuit (110), a first node reset circuit (120), an output circuit (130) and a noise reduction touch circuit (14...
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WO/2019/135132A1 |
The invention relates to a circuit (10) for monitoring an output voltage of a voltage supply (12). The circuit (10) comprises a microcontroller (14) for controlling a system, a shift register (16a, 16b, 16c) and a diagnostic circuit (22)...
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WO/2019/134367A1 |
A shift register circuit, a driving method, and a display device. The shift register circuit comprises a noise reduction sub-circuit (50) and a pull-down node control sub-circuit (10); a control end of the noise reduction sub-circuit (50...
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WO/2019/130516A1 |
In one embodiment, a method for producing an aluminum-made platter is provided, whereby it becomes possible to improve the smoothness of the surface of a substrate on which a magnetic layer is not formed yet and to produce a hard disk su...
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WO/2019/131084A1 |
Provided is a spacer having excellent magnetic characteristics. This spacer (12) is produced by forming a sheet of a ferrite stainless steel into a ring shape, and thereafter, applying heat and pressure to the ring-shaped sheet at a temp...
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WO/2019/133295A1 |
A memory device comprising an array of memory cells wherein each memory cell comprises a respective magnetic random access memory (MRAM) element, a respective gating transistor, and a common wordline coupled to gates of gating transistor...
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WO/2019/133328A1 |
A device includes an array of memory cells, input/output lines coupled to the memory cells, and sense amplifiers coupled to the input/output lines. Each sense amplifier is associated with a respective input/output line. The device also i...
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WO/2019/133299A1 |
A memory device for storing data is disclosed. The memory device comprises a memory bank comprising a memory array of addressable memory cells and a pipeline configured to process read and write operations addressed to the memory bank. F...
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WO/2019/130596A1 |
A sound playback control device which is connected to a computer (2) in a bidirectionally communicable manner and controls music data being played back by means of a music playback application (21) operating on the computer (2) is provid...
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WO/2019/133300A1 |
Techniques to update a trim parameter in non-volatile memory during either a manufacturing stage or a post-manufacturing stage are described. Trim parameters may be stored in a register located within the memory device that is inaccessib...
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WO/2019/133223A1 |
A method of writing data into a memory device is disclosed. The method comprises utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank. Further, the method comprises writing a seco...
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WO/2019/133396A1 |
Apparatuses and methods for sense line architectures for semiconductor memories are disclosed. An example apparatus includes a first array region including first portions of a plurality of sense lines and memory cells coupled to the firs...
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WO/2019/132822A1 |
The invention relates to a universal communication module for establishing connections between electronic devices. The invention relates to a system for communicating with other systems via a communication line connected to a USB (Univer...
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WO/2019/130144A1 |
Provided is a novel storage device. The storage device has a plurality of memory cells arranged in a matrix. Each memory cell has a transistor and a capacitance element. Each transistor has a first gate and a second gate which have regio...
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WO/2019/133198A1 |
Devices and techniques for managing partial superblocks in a NAND device are described herein. A set of superblock candidates is calculated. Here, a superblock may have a set of blocks that share a same position in each plane in each die...
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WO/2019/131393A1 |
Provided are: a position sensing element which is provided with an exchange coupled film that has a large exchange coupling magnetic field; and a position sensor which has good sensing accuracy in a high temperature environment. A positi...
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WO/2019/133239A1 |
Methods and devices for techniques for precharging a memory cell are described. Precharging a memory cell while the memory cell is coupled with its digit line may reduce a total duration of an access operation thereby reducing a latency ...
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WO/2019/133233A1 |
A method of writing data into a memory device is disclosed. The method comprises utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank. The method further comprises writing a secon...
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WO/2019/133243A1 |
Methods, systems, and devices for drift mitigation with embedded refresh are described. A memory cell may be written to and read from using write and read voltages, respectively, that are of different polarities. For example, a memory ce...
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WO/2019/133202A1 |
Apparatuses, methods, and devices that can be utilized to provide temperature-based memory operations are described. One or more apparatuses can include a memory device and a controller coupled to the memory device and configured to: det...
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WO/2019/133868A1 |
An STT-MRAM device incorporating a multiplicity of MTJ junctions is encapsulated so that it dissipates heat produced by repeated read/write processes and is simultaneously shielded from external magnetic fields of neighboring devices. In...
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WO/2019/131025A1 |
This resistance-change type nonvolatile storage device has: a memory cell array that has a plurality of memory cells (10); a writing circuit that executes writing in the memory cells (10); and a control circuit. Each of the memory cells ...
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WO/2019/133244A1 |
A memory device for storing data is disclosed. The memory device comprises a memory bank comprising a plurality of addressable memory cells configured in a plurality of segments wherein each segment contains N rows per segment, wherein t...
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WO/2019/133325A1 |
Methods, systems, and devices for polarity-conditioned memory cell write operations are described. A memory cell may be written with a logic state by performing a write operation that includes applying a first write voltage across the me...
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WO/2019/133638A1 |
Aspects of the technology described herein allow a user to add tags to a video as the video is being recorded. The tags can be added by capturing the user's voice as the video is recorded. Aspects can be performed by a head-mounted displ...
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WO/2019/133258A1 |
Described embodiments relate to look up table operations implemented in a digital data processor (100). A look up table read instruction recalls data elements of a specified data size from table(s) and stores recalled data elements in su...
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