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Matches 1 - 50 out of 857,375

Document Document Title
WO/2019/096083A1
A gate drive sub-circuit, a drive method, and a gate drive circuit. The gate drive sub-circuit comprises: a signal input terminal (STV_IN), a shift signal output terminal (STV_N), a shift reverse-phase signal output terminal (STV_F), a n...  
WO/2019/098054A1
The present technology pertains to an information processing device, an information processing method, a storage medium, a reproduction device, a reproduction method, and a program, in which an unnatural change in brightness during rando...  
WO/2019/099811A1
Algorithms for fast data retrieval, low power consumption in a 3D or planar non-volatile array of memory cells, connected between an accessible drain string and a floating, not directly accessible, source string, in a NOR-logic type of a...  
WO/2019/099274A1
An initialization process is disclosed for a perpendicular magnetic tunnel junction (p-MTJ) wherein the switching error rate is reduced from a typical range of 30-100 ppm to less than 10 ppm. In one embodiment, an in-plane magnetic field...  
WO/2019/099169A1
A memory device that includes a non-volatile memory (NVM) array, divided into a flash memory portion and an electrically erasable programmable read-only memory (EEPROM) portion. The NVM array includes charge-trapping memory cells arrange...  
WO/2019/099737A2
Access to a networked communication session is provided to each of a plurality of user computing devices that are each configured with at least a camera, audio input subsystem, and audio output subsystem. During the networked communicati...  
WO/2019/099106A1
A memory device and associated techniques for reducing hot electron injection type of disturbs of memory cells. In one approach, after a pre-charge operation, voltages of a first group of adjacent word lines comprising a selected word li...  
WO/2019/096120A1
A gate driver circuit, a display device and a driving method therefor. The gate driver circuit comprises a plurality of shift register units, the plurality of shift register units being divided into a first shift register unit group and ...  
WO/2019/099105A1
A memory device and associated techniques for reducing program disturb of memory cells which are formed in a two-tier stack with an increased distance between memory cells at an interface between the tiers. After a verify test in a progr...  
WO/2019/099438A1
A method of fabricating a magnetoresistive device includes forming a magnetically fixed region on one side of an intermediate region. Forming the magnetically fixed region may include forming a first ferromagnetic region and forming an a...  
WO/2019/099930A1
Systems and methods according to one or more embodiments are provided for sensing a current at an output of a switching amplifier. In one example, a system includes a first transistor switch coupled to a load configured to conduct a curr...  
WO/2019/096660A1
Optimized synapses for neuromorphic arrays are provided. In various embodiments, first and second single-transistor current sources are electrically connected in series. The first single-transistor current source is electrically coupled ...  
WO/2019/097347A1
Configuration state registers grouped based on functional affinity. An identification of an in-memory configuration state register for which memory is assigned is obtained. Based on the identification, an offset into the memory at which ...  
WO/2019/097513A1
An analog to digital converter comprises an input for receiving an analog input signal; a plurality of outputs for outputting parallel bits of a digital signal that represents said analog input signal; and a neural network layer providin...  
WO/2019/096416A1
A superconducting memory cell device suitable for a superconducting computer is described. The memory cell comprises two superconducting electrodes and a ferromagnetic component coupled between the two superconducting electrodes to form ...  
WO/2019/094113A1
Systems, methods, and apparatus for operating a central processing unit (CPU) are provided. The CPU includes a plurality of memories including a first group of memories and a second group of memories. The plurality of memories are groupe...  
WO/2019/093467A1
A servo writer comprises a write head that writes a servo signal to a traveling elongated magnetic tape, and two or more first guide rollers that guide the travel of the magnetic tape, the two or more first guide rollers each having a ci...  
WO/2019/094513A1
The invention provides systems, devices, connectors and methods to send compressed audio video serial digital signals thru local systems with significantly reduced bandwidth requirements and device costs, over longer cable runs and with ...  
WO/2019/091865A1
An electronic imager (1) for imaging a photographic medium, comprising at least one array (6) of micromirrors (2), each of which is suitable for reflecting, during a change in position, a light beam coming from at least one light source ...  
WO/2019/092534A1
A tape drive-implemented method includes: determining a servo band configuration of servo bands on a magnetic tape, using servo readers on a magnetic tape head to read one or more of the servo bands based on the determined servo band con...  
WO/2019/094070A1
Methods, systems, and apparatuses related to memory operation with common clock signals are provided. A memory device or system that includes one or more memory devices may be operable with a common clock signal without a delay from swit...  
WO/2019/092610A1
A Voltage Regulator Module (VRM) includes a first voltage rail circuit board oriented in a first plane having formed therein a first plurality of conductors and configured to produce a first rail voltage, a second voltage rail circuit bo...  
WO/2019/094569A1
A driving oriented digital video recorder (DVR) system may comprise a camera; a memory; and a control circuit. The occurrence of a predefined driving event type may be determined based on received data. An event object that includes deta...  
WO/2019/094864A1
A spintronic device controls both the electrical charge and the spin of electrons to transmit, process, and store information. The control of electron spin provides additional degrees of freedom to modify the electric and magnetic proper...  
WO/2019/093469A1
A servo writer comprises: a write head that writes a servo signal to a traveling elongated magnetic tape; a guide roller provided on the upstream side of a travel path from the write head, the guide roller guiding the traveling magnetic ...  
WO/2019/092990A1
When data generated by a device (30) arrive in the order of time points at which the data were generated, the data are added (written) to an actual data recording part (12b) in the order of arrival of the data, and the time point at whic...  
WO/2019/093447A1
Disclosed is a magnetic recording medium wherein average thickness tT satisfies formula of tT≤5.5 [μm], and size change quantity ∆w in the width direction of the magnetic recording medium with respect to a tension change in the long...  
WO/2019/091168A1
A shift register unit, a driving method thereof, a gate driving circuit and a display device. The shift register unit comprises a first input circuit (11), an input control circuit (20), a pull-down control circuit (40), a pull-down circ...  
WO/2019/090162A1
An apparatus for storing data in a magnetic random access memory (MRAM) is provided. The MRAM may store data in one or more resistance-based memory cells and may include a plurality of comparators to compare a voltage generated based on ...  
WO/2019/087769A1
Provided are: a reading circuit which is for a resistance change memory device and which is capable of reducing area size while advantageously saving power; and a method for reading same. A bit line BL to which a memory cell 12 is connec...  
WO/2019/086835A1
The present techniques generally relate to devices, method and/or systems for responding to a request for accessing a portion of a memory prior to completion of a requested operation to place the portion of the memory in an initialized s...  
WO/2019/085617A1
Disclosed in the present invention is a voltage-controlled magnetic anisotropy magnetic random access memory. The voltage-controlled magnetic anisotropy magnetic random access memory comprises a virtual array, a storage array, and a peri...  
WO/2019/089012A1
An image processing system for verifying that embedded digital content satisfies a predetermined criterion associated with display of the content, the image processing system a content embedding engine that embeds content in a resource p...  
WO/2019/089097A1
The present disclosure provides systems and methods that generate a summary storyboard from a plurality of image frames. An example computer-implemented method can include inputting a plurality of image frames into a machine-learned mode...  
WO/2019/090025A1
The present disclosure includes apparatuses and methods related to configurable trim settings on a memory device. An example apparatus can include configuring a set of trim settings for an array of memory cells such that the array of mem...  
WO/2019/090127A1
Methods and systems are described for obtaining, at a phase-error aggregator, a plurality of data-derived phase-error signals for two or more data lanes of a multi-wire bus, each data-derived phase-error signal generated using at least (...  
WO/2019/085931A1
A random access memory (RAM) including a deserializer is disclosed. The RAM further comprises a continuous-time linear equalizer (CTLE) including a first input terminal that receives an input signal for the RAM and a first output termina...  
WO/2019/090021A1
The present disclosure includes apparatuses and methods related to selectable trim settings on a memory device. An example apparatus can store a number of sets of trim settings and select a particular set of trims settings of the number ...  
WO/2019/089168A1
A method of reading a memory device having a plurality of memory cells by, and a device configured for, reading a first memory cell of the plurality of memory cells to generate a first read current, reading a second memory cell of the pl...  
WO/2019/085578A1
Provided are a shift register and a drive method therefor, a gate drive circuit, and a display apparatus. The shift register comprises a first input sub-circuit for outputting, under the control of a first signal input terminal, a voltag...  
WO/2019/088725A1
Disclosed is a method for automatically tagging metadata of music content using machine learning. The method comprises the steps of: generating a metadata automatic tagging model by using machine learning; obtaining one or more audio ana...  
WO/2019/087548A1
Provided is a fluorine-containing ether compound which is capable of forming a lubricating layer that has excellent wear resistance even if the thickness thereof is thin, and which is suitable as a material for a lubricant for magnetic r...  
WO/2019/087775A1
The present technology pertains to a reproduction device, a reproduction method, a program, and a recording medium that enable prevention of an unnatural luminance change when another piece of information is displayed by being superimpos...  
WO/2019/085037A1
Disclosed in the present invention are a method for distributing system media sources by a vehicle-mounted system, and the vehicle-mounted system. The method for distributing system media sources by a vehicle-mounted system comprises: re...  
WO/2019/090036A1
The present disclosure includes apparatuses and methods related to determining trim settings on a memory device. An example apparatus can determine a set of trim settings for the array of memory cells based on the operational characteris...  
WO/2019/089102A1
Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance are disclosed. A memory device of a semiconductor device may be set in an identification mode and provide an identification r...  
WO/2019/089350A1
Devices and techniques for NAN flash thermal alerting are disclosed herein. A NAND array operation is received at a controller of a storage device that includes a NAND array. The controller evaluates a thermal condition of the NAND array...  
WO/2019/090033A1
The present disclosure includes apparatuses and methods related to a memory system including a controller and an array of memory cells. An example apparatus can include a controller configured to receive operational characteristics of an...  
WO/2019/089106A1
A memory device (10) includes memory banks (11) that each have multiple rows with row addresses. The memory device (10) also includes a counter (52, 54) that stores and increments a first row address of a first row of a first set of memo...  
WO/2019/088209A1
According to the present invention, in a particle size distribution for a cerium oxide contained in a polishing liquid as obtained by a laser diffraction/scattering method, D5 is 1 μm or less, and the difference between D95 and D5 is 3 ...  

Matches 1 - 50 out of 857,375