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WO/2019/170913A1 |
A circuit for delaying an electric signal (CI), comprises an input for the electric signal (CI); an input for a control signal (EI); a first storage element (U5) for storing the control signal; a delay element for delaying the electric s...
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WO/2019/171881A1 |
A mark corresponding to recording data is formed on an optical disk medium by: encoding the recording data in accordance with a modulation code and thus generating encoded data; classifying the encoded data by a combination of at least t...
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WO/2019/173035A1 |
Semiconductor memory devices and methods of operating the same are provided. The method of operation may include the steps of selecting a ferroelectric memory cell for a read operation, coupling a first pulse signal to interrogate the se...
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WO/2019/172746A1 |
A method of optimizing a March test algorithm, MTA (11) for memory built-in self-test, MBIST is provided, the method includes the steps of generating a new March test algorithm (13), characterized in that, the method further includes gen...
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WO/2019/172081A1 |
An optical recording medium is provided with a recording layer containing an oxide of a metal MA, an oxide of a metal MB, an oxide of a metal MC, an oxide of a metal MD and an oxide of a metal ME. The metal MA comprises at least one meta...
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WO/2019/171675A1 |
This magnetic disk substrate is provided with an aluminum alloy substrate and a base plating layer formed on a surface of the aluminum alloy substrate. For a boundary region formed between the base plating layer and the aluminum alloy su...
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WO/2019/169911A1 |
Disclosed is an array substrate (110). The array substrate (110) comprises: a substrate; an active switch (T0); and a shift register circuit (300) located on the side edge of the substrate and having multiple stages of shift registers, w...
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WO/2019/171665A1 |
Provided is a magnetic recording tape that exhibits superior tape dimension stability even if there are changes in temperature or humidity, or even if tension is applied to the magnetic recording tape whilst the tape is running. The pres...
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WO/2019/172976A1 |
A method of assessing impact of applications executed by a computing device on a memory of the computing device includes: storing, in the memory, (i) a plurality of reference write operation sizes, and (ii) for each reference write opera...
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WO/2019/172456A1 |
In the present invention, a spacer is interposed between each pair of adjacent substrates from among substrates forming a laminate so as to separate the adjacent substrates from each other, and the spacer has a smaller area than the lami...
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WO/2019/173534A1 |
A temperature related to a memory device is identified. It is determined whether the temperature related to the memory device satisfies a threshold temperature condition. Responsive to detecting that the temperature related to the memory...
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WO/2019/172095A1 |
Provided are a magnetic information reader which does not require sophisticated hardware or a high-capacity memory yet is capable of increasing extreme value detection accuracy, and a method of controlling the magnetic information reader...
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WO/2019/169078A1 |
Methods and apparatuses to fragment data in a flash memory device are presented. The apparatus includes a host configured to request a flash memory device, via a memory bus, to fragment data stored in the flash memory device in response ...
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WO/2019/168241A1 |
A neuromorphic system based on a three-dimensional stacked synapse array, and an operating method and a manufacturing method therefor are disclosed. The neuromorphic system based on a three-dimensional stacked synapse array, according to...
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WO/2019/168581A1 |
Apparatuses, systems, and methods are disclosed for adjusting a programming setting such as a programming voltage of a set of non-volatile storage cells, such as an SLC NAND array. The non-volatile storage cells may be arranged into a pl...
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WO/2019/168830A1 |
Resistive change element cells sharing a selection device and resistive change element arrays including a plurality of resistive change element cells and a plurality of selection devices arranged in a group of at least two resistive chan...
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WO/2019/168675A1 |
Various aspects are described herein. In some aspects, the disclosure provides selective coupling of portions of a memory structure to voltage supplies. Certain aspects provide a computing device. The computing device includes a memory c...
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WO/2019/168752A1 |
Systems and methods using a three-dimensional memory device with a number of memory cells disposed vertically in a number of pillars arranged along a horizontal direction can be used in a variety of applications. In various embodiments, ...
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WO/2019/168880A1 |
A system, method and apparatus for encoding and decoding data. A host processor and host memory are coupled to a block I/O device. The host processor issues encode and decode commands to the block I/O device in accordance with a high-spe...
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WO/2019/147859A3 |
Synaptic resistors (synstors), and their method of manufacture and integration into exemplary circuits are provided. Synstors are configured to emulate the analog signal processing, learning, and memory functions of synapses. Circuits in...
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WO/2019/166960A1 |
A terminal for enjoying at least an audio and/or video content provided by a providing entity through a network via a linear channel comprises: requesting means for sending a first request for a content item to said providing entity, rec...
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WO/2019/168574A1 |
In a memory system, variable resistance circuits, such as transistor circuits, in the word line and bit line decoders are set during bias line set times and/or prior to turn-on times of read operations to increased resistance levels. The...
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WO/2019/166296A1 |
A method and system for detecting and localizing a target audio event in an audio clip is disclosed. The method and system use utilizes a hierarchical approach in which a dilated convolutional neural network to detect the presence of the...
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WO/2019/162802A1 |
Provided is a novel storage device. A first cell array having a plurality of memory cells and a second cell array having a plurality of memory cells are provided so as to overlap each other. Two bit lines included in a first bit line pai...
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WO/2019/161815A1 |
A random access memory device (400) comprises inert-inert electrode cell (210) and inert-active electrode cell (110). The inert-inert electrode cell (210) and inert-active electrode cell (110) are connected in series in a serial connecti...
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WO/2019/164573A1 |
A storage system and method for performing high-speed read and write operations are disclosed. In general, these embodiments discuss ways for performing a fast read in response to determining that the fast read will probably not have a n...
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WO/2019/164547A1 |
Memory devices, systems including memory devices, and methods of operating memory devices and systems in which a memory device can include a voltage regulator for adjusting a supply voltage to an output voltage and providing the output v...
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WO/2019/164663A1 |
Apparatuses and methods for duty cycle distortion correction of clocks are disclosed. An example apparatus includes a clock circuit configured to receive complementary input clocks and a control signal and to provide multiphase clocks re...
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WO/2019/161676A1 |
The present disclosure relates to a shift register, a gate driver on array circuit and a display device. The shift register comprises an input circuit, a pull-up circuit, a pull-down circuit, a pulse width control circuit and an output n...
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WO/2019/164550A1 |
Some embodiments include an apparatus having first and second comparative bitlines extending horizontally and coupled with a sense amplifier. First memory cell structures are coupled with the first comparative bitline. Each of the first ...
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WO/2019/165221A1 |
A method of making a component includes applying a clamping force to the component, the component coupled to a carrier strip of a panel via a polymeric tab and separating a portion of the polymeric tab from a substrate of the component, ...
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WO/2019/165038A1 |
Audio processing systems and methods are configured to receive audio program content and to reproduce the audio program content in accord with at least one audio parameter. The audio parameter is stored with a relation to an identifier a...
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WO/2019/163567A1 |
[Problem] To enable rewrites, which are due to the influence of external factors, of information held in memory elements to be detected in a preferred manner. [Solution] A semiconductor memory device provided with: multiple memory elemen...
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WO/2019/163239A1 |
Provided are a magnetic disc and a production method therefor, said magnetic disc being characterized in that: the magnetic disc is provided with an electroless Ni-P plating layer formed, through a compound removal process, on a surface ...
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WO/2019/164181A1 |
Various embodiments according to the present invention relate to a power conversion device and method, the device comprising: a converter; a capacitor unit including a plurality of capacitors for storing input voltage input thereto; a sw...
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WO/2019/164760A1 |
A method for bit error rate testing a processing unit using a bit error rate tester (BERT) includes transmitting a signal pair to a receiver of the processing unit, the signal pair having jitter levels complying with a jitter threshold, ...
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WO/2019/157862A1 |
A shift register (200, 400, 1000), a gate drive circuit, a display device and a driving method (2000), the shift register (200, 400, 1000) comprising: a first input sub-circuit (210, 410), which is configured to receive a first input sig...
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WO/2019/160585A1 |
Methods and devices (10) include an input buffer configured to receive data. Decision feedback equalizer (DFE) circuitry (52) includes a DFE (70) configured to interpret levels of the data from the input buffer and a DFE buffer (76) that...
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WO/2019/159620A1 |
The imaging device is for recording high dynamic range (HDR) image data obtained by capturing images. When encoding HDR image data obtained by capturing images with an image sensor, control is performed such that HDR image data in an enc...
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WO/2019/160589A1 |
A semiconductor device may include a plurality of memory banks (12) and an output buffer (52) that may couple to the plurality of memory banks (12). The output buffer (52) may produce a data voltage signal representative of data to be re...
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WO/2019/160590A1 |
Embodiments described herein detail the design and architecture in which circuit components may be incorporated into a semiconductor device to control the slew rate of a provided voltage signal (e.g., data), such that the resulting data ...
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WO/2019/159465A1 |
The purpose of the present technology is to provide a magnetic recording tape or the like, in which the tape can stably run at high speed while keeping the distance between a magnetic head and the tape small. The present technology provi...
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WO/2019/159795A1 |
Provided are an aluminum-alloy substrate for a magnetic disk, a manufacturing method for said aluminum-alloy substrate, and a magnetic disk employing the aluminum-alloy substrate for a magnetic disk, the aluminum-alloy substrate comprisi...
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WO/2019/160581A1 |
A semiconductor device may include a number of memory banks, an output buffer that couples to the memory banks, a number of switches that couple a voltage source to the output buffer, and a stagger delay circuit. The stagger delay circui...
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WO/2019/160431A1 |
Disclosed is a device for recording information on a magnetic data storage medium which comprises a magnetic field source designed to be capable of generating a magnetic field in the region where the magnetic storage medium is arranged; ...
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WO/2019/161233A1 |
A protection system for portable electronic devices may include a first impact absorbing panel, a second impact absorbing panel, and multiple spacers adapted to hold the panels apart to accommodate the thickness of a portable electronic ...
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WO/2019/160144A1 |
[Problem] To provide a technology for further improving the recording density of data. [Solution] A magnetic recording medium according to the present technology has a base material and a magnetic layer, and has a tape shape that is long...
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WO/2019/157842A1 |
A shift register unit (10), a gate driving circuit (20), a display device (1), and a driving method. The shift register unit (10) comprises a display sub-shift register (200) and a detection sub-shift register (100). The display sub-shif...
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WO/2019/158441A1 |
A continuous-time sampler has series-connected delay lines with intermediate output taps between the delay lines. Signal from an output tap can be buffered by an optional voltage buffer for performance. A corresponding controlled switch ...
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WO/2019/159962A1 |
Provided is a perpendicular magnetization type three-terminal SOT-MRAM which does not require an external magnetic field. A magnetoresistive effect element wherein: a first magnetic layer (3), a non-magnetic spacer layer (4) and a record...
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