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Matches 1 - 50 out of 859,065

Document Document Title
WO/2019/220259A1
To provide a storage device that comprises gain cell-type memory cells composed of n-channel transistors and that does not require an electric potential lower than the electric potential applied to bit lines. The memory cells of the stor...  
WO/2019/221896A1
A portion of the memory space, supported by memory chips that are being controlled by a memory controller logic, can be set aside and read requests directed to memory addresses within that portion can be redirected, by the memory control...  
WO/2019/221762A1
System and methods for aligning event data recorded by recording devices. Recording devices create, transmit, and store alignment data. Alignment data created by a recording device is stored in the memory of the recording device with a t...  
WO/2019/221898A1
A data-storage system comprises a head receiver configured to variably receive up to a number M of write heads. The data-storage system also includes an installed number N of write heads arranged in the head receiver, a substrate receive...  
WO/2019/221790A1
Apparatuses and techniques are described for programming a memory device with reduced temperature-based changes in the threshold voltage distribution (Vth). Different memory cells can have different values of a temperature coefficient, T...  
WO/2019/221791A1
Apparatuses and techniques are described for reducing an injection type of program disturb in a memory device. A voltage on a selected word line is increased in a first step from an initial level such as 0 V to an intermediate, pass leve...  
WO/2019/221880A1
An apparatus having an analog-to-digital converter with an increased effective resolution is disclosed. The apparatus includes a signal processing functional block and an analog-to-digital conversion block. The signal processing function...  
WO/2019/221102A1
Provided is a glass for a magnetic recording medium substrate, the glass being an amorphous oxide glass having an SiO2 content of 56-80 mol%, an Li2O content of 1-10 mol%, a B2O3 content of 0-4 mol%, a total content (MgO + CaO) of MgO an...  
WO/2019/221867A1
A memory device with memory cells in rows and columns, word lines connecting together the control gates for the memory cell rows, bit lines electrically connecting together the drain regions for the memory cell columns, first sub source ...  
WO/2019/221810A1
In an on-chip copy process, performed by a storage device, data is copied from a plurality of Single Level Cell (SLC) blocks of non-volatile three-dimensional memory (e.g., 3D flash memory) in a respective memory die to a Multilevel Cell...  
WO/2019/222015A1
The subject application is directed to forwarding a code word address. Methods, systems, and devices for forwarding a code word address are described. A memory subsystem, for example, may configure a code word including user data as a fo...  
WO/2019/220919A1
Provided is a polishing fluid composition for magnetic disc substrates, that ensures polishing speed and is capable of reducing: surface defects on the substrate surface after polishing; and short-wavelength undulations during continuous...  
WO/2019/220983A1
Provided is a layout structure capable of suppressing variation in operation of a ROM memory cell using vertical nanowire (VNW) FETs. VNW FETs (T11-T14, T21-T24, T31-T34, T41-T44) provided in the ROM memory cell are configured so that: g...  
WO/2019/218753A1
Disclosed are a method and apparatus for adjusting the position of a data strobe signal (DQS). The method comprises: obtaining effective margin widths of all data signals (DQs) on a transmission bus; determining a left boundary and a rig...  
WO/2019/220630A1
The purpose of the present invention is to provide a technique whereby data can be appropriately stored. This information collection device is provided with a similarity determination unit 111 for obtaining similarity between acquired da...  
WO/2019/220796A1
[Problem] To provide a non-volatile semiconductor memory which is capable of writing or reading at high speed and is suitable for integration at high density. [Solution] The semiconductor device comprises: a first inverter circuit that i...  
WO/2019/219295A1
A charge pump circuit arrangement comprises a multitude of capacitors (110, 111, 112, 113) of a first and a second group controlled by non-overlapping clock pulses (CLK1, CLK2). The capacitors are partly realized in a semiconductor subst...  
WO/2019/216967A1
Memory devices (10) with half-width data path (46) or data buses clocked by double-pumped strobe signals are disclosed herein. The methods (400, 420) and devices (10) may employ a single delay chain (e.g., a column access strobe (CAS) ch...  
WO/2019/217064A1
Methods, systems, and devices for a latency indication in a memory system or sub-system are described. An interface controller of a memory system may transmit an indication of a time delay (e.g., a wait signal) to a host in response to r...  
WO/2019/217454A1
Systems and methods are disclosed, including maintaining an error recovery data structure for a set of codewords (CWs) in a storage system and performing error recovery for the set of CWs using a set of error handing (EH) steps until eac...  
WO/2019/217003A1
The present disclosure generally relates to displaying visual effects in image data. In some examples, visual effects include an avatar displayed on a users face. In some examples, visual effects include stickers applied to image data. I...  
WO/2019/216099A1
Provided are a magnetoresistance effect element having high read operation speed, a magnetic memory array, a magnetic memory device, and a write method for a magnetoresistance effect element. A magnetoresistance effect element 1 is provi...  
WO/2019/216015A1
A recording medium cartridge according to an aspect of the present technology is provided with: an information recording medium; a first cartridge memory; and a second cartridge memory. The first cartridge memory is able to store first i...  
WO/2019/214294A1
A shift register and a driving method therefor, a gate driver circuit, and a display device. The shift register may comprise: a transmission sub-circuit used for providing a signal at a first input end (INPUT1) or second input end (INPUT...  
WO/2019/213760A1
A system for playing audio/video includes a set of triggering objects. Each triggering object has a respective computer readable image. The system further includes a camera for capturing images within a zone of interactivity, an audiovis...  
WO/2019/216205A1
Provided is, as one embodiment, a polishing liquid composition for a glass hard disk substrate that can prevent deterioration of surface roughness of a substrate surface after washing while maintaining the polishing rate. One embodiment ...  
WO/2019/216965A1
A non-volatile memory system includes a control circuit connected to non-volatile memory cells. The control circuit is configured to simultaneously program memory cells connected to different word lines that are in different sub-blocks o...  
WO/2019/216987A1
Systems and devices for routing signals between a memory device and an interface of a host device are described. Some memory technologies may have a defined, preconfigured interface (e.g., bumpout), where each interface terminal may have...  
WO/2019/214346A1
A shift register unit and a driving method therefor, a scan driving circuit and a display device. The shift register unit comprises: an input circuit (11), used for turning on an input terminal (Gn-1) and a first node (P1) when a first c...  
WO/2019/215002A1
The invention relates to a static direct access memory block (20), in particular for a receiving sensor, comprising a memory cell field (21), a row address decoder (22), a column data multiplexer (23), a read and write module (24) compri...  
WO/2019/217086A2
In some embodiments, an electronic device presents indications of usage metrics for the device. In some embodiments, an electronic device sets, configures and/or enforces device usage limits. In some embodiments, an electronic device lim...  
WO/2019/212789A1
A system for increasing data retention time can include a processor to execute code to detect or predict a write event associated with a flash memory. The processor can also control a device to cause a temperature at the flash memory to ...  
WO/2019/212488A1
A crossbar array includes a number of memory elements. An analog-to-digital converter (ADC) is electronically coupled to the vector output register. A digital-to-analog converter (DAC) is electronically coupled to the vector input regist...  
WO/2019/210679A1
Provided are a device battery and an unmanned aerial vehicle. The device battery comprises: a battery microprocessor, an electrically erasable programmable read-only memory and a marking component, wherein the battery microprocessor is c...  
WO/2019/211927A1
A RAM (20) has a plurality of data regions (21-23) for commonly storing predetermined RAM data. A diagnosis unit (60) executes test pattern diagnosis for a data region to be diagnosed among the data regions (21-23). A comparison unit (50...  
WO/2019/212620A1
A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller writes a first data test to a memory device through either the host interface or the memory interfa...  
WO/2019/212699A1
Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network...  
WO/2019/210583A1
A disposable programmable capacitive fuse position. The fuse position comprises an upper polar plate (3). The upper polar plate (3) comprises several fuses (5) arranged side by side at intervals, wherein middle portions of two adjacent f...  
WO/2019/212668A1
A system includes a memory device storing a set of start voltage values, wherein the set of start voltage values each represent voltage levels used to initially store charges in performing operations to corresponding one or more memory l...  
WO/2019/213371A1
Methods and systems are described for a media guidance application that enable a device to repair a corrupt recording. The media guidance application identifies and replaces a corrupt first segment of a plurality of segments correspondin...  
WO/2019/212589A1
A musical instrument recording system is provided. The system includes a recorder capable of receiving MIDI data from an instrument and recording the MIDI data onto a first memory. The recorder further renders the MIDI data into an audio...  
WO/2019/211372A1
The present invention relates to a material of the formula SnTiO3 having a crystal structure comprised of layers, wherein the layers comprise Sn(II) ions, Ti(IV) ions and edge-sharing O6-octahedra, the edge-sharing O6-octahedra form a su...  
WO/2019/213663A1
Advanced magnetic tunneling junctions (MTJs) that dramatically reduce power consumption (switching energy, ESw) while maintaining a reasonably high tunneling magnetoresistance (on/off ratio, TMR) and strong thermal stability at room temp...  
WO/2019/213140A1
Electro-optic devices for classical and quantum microwave photonics are provided. In various embodiments, a device comprises: a waveguide; a first ring resonator; a second ring resonator, the second ring resonator evanescently coupled to...  
WO/2019/212679A1
Methods, systems, and devices for access line management for an array of memory cells are described. Some memory devices may include a plate that is coupled with memory cells associated with a plurality of digit lines and/or a plurality ...  
WO/2019/211697A1
Provided is a semiconductor device in which it is possible to change the storage region for each hierarchy level of a storage device. Specifically provided is a semiconductor device which has a control circuit and a storage device provid...  
WO/2019/213031A1
A module for multiple dies is disclosed. The module can include a group of dies that include a first die having a first voltage block and a second die having a second voltage block. The module can also include an interconnect that electr...  
WO/2019/211601A1
A hybrid analogue-digital computer comprising configurable analogue circuitry arranged to apply functions on analogue signals in the analogue domain received through an analogue input of the computer system and provide an analogue output...  
WO/2019/210860A1
A memory circuit device and a memory test method are disclosed. The memory circuit device includes: a memory cell array, including storage lines and redundant storage lines; and a redundant decoder control circuit, configured to receive ...  
WO/2019/212753A1
A device comprises a stack structure comprising decks each comprising a memory level comprising memory elements, a control logic level vertically adjacent and in electrical communication with the memory level and comprising control logic...  

Matches 1 - 50 out of 859,065