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WO/2024/063126A1 |
The present invention further increases, when an element transfer sheet provided with an adhesive layer having relief on the surface thereof is extended, the interval between elements held by the sheet. This element transfer sheet is p...
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WO/2024/027332A9 |
Provided in the embodiments of the present disclosure are a preparation method for a semiconductor structure and a semiconductor structure. The preparation method for a semiconductor structure comprises: providing a substrate; forming on...
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WO/2024/063886A1 |
A cell layout that implements stacked transistors is disclosed. The cell layout utilizes both topside metal routing and backside metal routing. Various connection routes between components of the transistors (e.g., gates, sources, and dr...
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WO/2024/062662A1 |
Provided is a technique whereby it is possible to improve the quality of a film to be formed on a substrate. The present invention comprises: (a) a step for supplying a raw material gas containing a first element and an organic ligand ...
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WO/2024/063871A1 |
A method of processing a substrate that includes: flowing nitrogen-containing (N-containing) gas, dioxygen (O2), a noble gas, and a fluorocarbon into the plasma processing chamber, the plasma processing chamber configured to hold a subst...
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WO/2024/060435A1 |
Embodiments of the present disclosure provide a wafer and a manufacturing method therefor, and a mask. The wafer comprises a substrate, a plurality of chips, and a photoresist layer; the plurality of chips are arranged on the substrate a...
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WO/2024/064550A1 |
Exemplary methods of semiconductor processing may include etching a first portion of a feature in a substrate disposed within a processing region of a semiconductor processing chamber. The first portion of the feature may at least partia...
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WO/2024/060425A1 |
The present application provides a CIGS solar cell and a preparation method therefor. The CIGS solar cell comprises a soda-lime glass substrate, a Mo back electrode, a CIGS absorption layer, a CdS buffer layer, an i-ZnO and AZO window la...
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WO/2024/063004A1 |
The present invention provides a substrate processing system that is capable of suppressing usage amount of utility. A substrate processing system (1000) includes a substrate processing device (200) and a control device (300). The contro...
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WO/2024/062799A1 |
Provided is a substrate processing device which has improved throughput by increasing the number of provided single-wafer type chambers while suppressing the size of the device. The present invention makes it possible to stack single-waf...
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WO/2024/017091A9 |
A patterned assembly and structure, a columnar array, and a fabrication method for the patterned assembly and a use thereof, which relate to the field of quantum chip fabrication. The fabrication method comprises: performing a patterning...
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WO/2024/064046A1 |
Provided herein is a method for producing a die attach adhesive film sheet, comprising: Providing a first release substrate layer, a die attach adhesive layer, and a dicing tape layer, and joining the first release substrate layer, the d...
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WO/2024/062297A1 |
A semiconductor structure includes a front-end-of-line level including a plurality of field effect transistors electrically connected to a back-end-of-line interconnect level. The back-end-of-line interconnect level is located on a first...
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WO/2024/062683A1 |
A substrate processing apparatus 1 wherein an orientation change region R3 is provided between a transfer block 5 and a batch processing region R1, a sheet substrate transport region R4 is adjacent to the transfer block 5 and the orienta...
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WO/2024/062739A1 |
A substrate processing device (100) comprises: a substrate processing unit (10); piping (32); a filter unit (140); and a pump (114). The substrate processing unit (10) processes a substrate (W). The piping (32) flows a processing liquid ...
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WO/2024/060746A1 |
The embodiments of the present application relate to the technical field of semiconductors. Provided are a standard cell and a splicing method, and an integrated circuit, a standard cell library and an electronic device, which are used t...
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WO/2024/062921A1 |
This press head is provided with a head body and a sheet portion. The head body has a press surface. The sheet portion faces the press surface and is fixed so as to have a gap with respect to the press surface. Further, the sheet portion...
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WO/2024/060240A1 |
Disclosed in the present application are a display panel, and a method for manufacturing a display panel. A display panel (100) comprises a base substrate (105) and a signal line (110) arranged on the base substrate, wherein the base sub...
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WO/2024/063579A1 |
The present invention relates to a manufacturing method for a semiconductor device. The manufacturing method for a semiconductor device, according to one embodiment, may comprise the steps of: forming an insulation layer; forming a barri...
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WO/2024/062760A1 |
According to this invention, in an upper surface protective heating mechanism for heating a substrate while covering the upper surface of the substrate held by a substrate holding unit, a base block, a first underblock, and a second unde...
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WO/2024/063072A1 |
Provided is a bonded substrate in which the generation of voids is suppressed and that has high bonding strength. An aspect of the present disclosure is directed to a bonded substrate in which a first substrate and a second substrate are...
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WO/2024/060260A1 |
Disclosed in the present application are a semiconductor device, a preparation method, a power conversion circuit and a vehicle. The semiconductor device comprises: an N-type semiconductor substrate, a first epitaxial layer, a plurality ...
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WO/2024/062796A1 |
Provided is a semiconductor apparatus including a semiconductor substrate having a front surface on which a wiring layer is formed, a through hole that penetrates the semiconductor substrate, a through wire formed along a side surface of...
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WO/2024/064161A1 |
The present disclosure relates to vertical stacks including heterolayers, as well as processes and methods of their manufacture. Also described herein are apparatuses and systems for preparing and making such stacks.
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WO/2024/062764A1 |
The present invention provides a simple configuration which solves troubles, such as clogging, caused by the passage of vertical resin tablets. A resin feeder according to the present invention is equipped with a resin sending part 81 wh...
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WO/2024/062801A1 |
This film forming apparatus is provided with: a substrate supporting means which supports a substrate; an alignment means which performs an alignment of the substrate and a mask; and a vapor deposition means which discharges a vapor depo...
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WO/2024/060342A1 |
A method for improving thermal cycle reliability of an aluminum nitride direct-bonded aluminum packaging substrate, comprising: performing surface sputtering-based copper plating on an aluminum nitride direct-bonded aluminum ceramic subs...
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WO/2024/063112A1 |
The purpose of the present invention is to provide a resin composition which can suppress the occurrence of voids and floating during heat treatment and can be easily peeled after the heat treatment. Moreover, another purpose of the pres...
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WO/2024/064285A1 |
Embodiments of the present disclosure provide techniques for fabricating a semiconductor device with fewer via voids (e.g., gaps between a dielectric layer and a metal fill of the semiconductor device). One such technique involves formin...
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WO/2024/062469A1 |
An apparatus for automated stacking and bonding of acoustic stack components includes: a tray for storage of stack components, lower jigs, and upper jigs; a first station comprising a plasma dispenser for application of plasma to an uppe...
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WO/2024/061513A1 |
Device (1) for measuring the gaseous contamination of a transport carrier (2) for conveying and storing at least one semiconductor substrate (6) at atmospheric pressure, said carrier (2) comprising a door (4b) and a shell (4a) that can b...
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WO/2024/062789A1 |
This semiconductor device comprises: a first compound semiconductor; a first electrode arranged on the first compound semiconductor and connected to the first compound semiconductor by Schottky contact; a second compound semiconductor ar...
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WO/2024/064146A1 |
This application is directed to integrating metal oxide semiconductor (MOS) transistors and Schottky barrier diodes (SBDs). An integrated planar semiconductor device includes a substrate, an SBD joining an SBD semiconductor and a barrier...
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WO/2024/063366A1 |
A parallel-structured continuous chiller system according to one preferred embodiment of the present invention comprises: a low-temperature refrigerant supply part having a low-temperature refrigerant tank, which contains a relatively lo...
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WO/2024/062577A1 |
The present invention includes: (a) a step for supplying a first processing gas to a substrate; (b) a step for storing a second processing gas in a first storage unit while heating the second processing gas; (c) a step for storing the se...
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WO/2024/063410A1 |
A heat sink-integrated substrate for a power module according to an embodiment of the present invention comprises: a ceramic heat sink provided with a planar part, and a plurality of protruding parts that are spaced and protrude from the...
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WO/2024/061038A1 |
A super-junction LDMOS device and a method for manufacturing same. A super-junction LDMOS device (100) comprises: a substrate (20); an epitaxial layer (21), which covers the surface of one side of the substrate (20); a body region (28) a...
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WO/2024/061264A1 |
Embodiments of the present disclosure relate to a semiconductor device and a manufacturing method therefor. The semiconductor device comprises: a semiconductor body, comprising a substrate, a buried layer, and an epitaxial layer, wherein...
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WO/2024/064423A1 |
A method of moving a susceptor in a processing system, suitable for use in semiconductor processing, is provided. The method includes: moving a first susceptor from an interior volume of a first enclosure to an interior volume of a proce...
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WO/2024/064565A2 |
Vertical channel field-effect transistors (VCFETs) with reduced contact resistance and/or parasitic capacitance, and related fabrication methods. In exemplary aspects, to reduce contact resistance of the VCFET, an end portion of the vert...
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WO/2024/064526A1 |
A method for etching features in a stack comprising a silicon oxide layer below a mask is provided. A substrate support for supporting the stack in an etch chamber is cooled to a temperature below 0° C. An etch gas comprising a halogen ...
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WO/2024/064461A1 |
A wafer carrier includes a base including a generally planar bottom surface and a top surface that includes a plurality of platforms extending above the top surface. The wafer carrier includes a thermal cover defining a plurality of pock...
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WO/2024/064881A1 |
A method of texturing a Group III-V semiconductor is disclosed. The method includes flowing a halomethane compound over a layer of the Group III-V semiconductor after epitaxial growth of the layer to form a textured surface in the layer ...
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WO/2024/064165A1 |
Described are substrate containers that are useful for holding or transporting substrates such as semiconductor wafers and microelectronic devices, in a clean environment, as well as methods of using the substrate containers.
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WO/2024/060362A1 |
Provided in the present disclosure are a super-resolution photoetching structure, a manufacturing method, and a pattern transfer method. The manufacturing method comprises: S1, forming a dielectric layer (2) on a substrate (1); S2, depos...
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WO/2024/062926A1 |
A method for bonding substrates which comprises performing the following steps in the following order: (a) a step in which two substrates each including a plurality of wiring parts and layered parts disposed between the plurality of wiri...
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WO/2024/060639A1 |
The present application discloses a package and a preparation method therefor. The preparation method for a package comprises: acquiring a processing plate, wherein the processing plate comprises a carrier plate two opposite sides of whi...
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WO/2024/064145A1 |
This application is directed to integrating field-effect transistors (FETs) and Schottky barrier diodes (SBDs) on a substrate and forming an integrated and planar semiconductor device. A P-type Metal Oxide Semiconductor (PMOS) transistor...
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WO/2024/063830A1 |
A memory device includes a horizontal source layer which is laterally separated into laterally isolated portions located in adjacent memory blocks by a dielectric backside trench fill structure or a source isolation dielectric structure.
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WO/2024/062988A1 |
[Problem] To provide a resin film which can be interposed between a substrate and a substrate holding part so as to easily hold the substrate on the substrate holding part, and which makes it possible to appropriately remove a plurality ...
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