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WO/2024/012428A1 |
The present application relates to a semiconductor device and a preparation method therefor. The semiconductor device comprises a semiconductor substrate (111), an insulating buried layer (112), a drift region (120), and a plurality of d...
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WO/2024/015623A1 |
The present invention discloses a GaN trench MOSFET and its fabrication method. The GaN trench MOSFET of the current invention has an n-GaN region having both Mg and donor impurities below a trench bottom, extending to an n--GaN drift la...
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WO/2024/011658A1 |
A display panel (100), comprising: providing a protruding structure (21) in a thin film transistor (2) of a non-display area (102), then providing a source/drain layer (25) on the protruding structure (21); a source electrode (251) and a...
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WO/2024/015154A1 |
A stacked gate-all-around (GAA) complementary field-effect transistor (CFET) includes a first GAA FET of a first type and a second GAA FET of a second type. Each of the first GAA FET and the second GAA FET includes at least one three-dim...
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WO/2024/011609A1 |
A semiconductor device includes a substrate, an insulation layer, and a plurality of epitaxial structures. The substrate includes a first substrate layer and a plurality of second substrate layers. The first substrate layer is doped with...
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WO/2024/014401A1 |
Provided is a semiconductor device comprising: a semiconductor substrate; an interlayer insulation film that has a contact hole and is provided above the semiconductor substrate; a first alloy layer that is provided below the contact hol...
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WO/2024/012342A1 |
Embodiments of the present application provide a chip and a preparation method. The chip comprises: a substrate, wherein a first through hole penetrating through the substrate from the upper surface to the lower surface is formed in the ...
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WO/2024/013602A1 |
Provided is a transistor of minute size. Said transistor has a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a second insulating layer, and a semiconductor layer. The first insulat...
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WO/2024/012455A1 |
Provided in the present invention are an insulated gate bipolar transistor and a preparation method therefor. The preparation method for an insulated gate bipolar transistor comprises the following steps: providing a semiconductor layer,...
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WO/2024/015668A2 |
In a general aspect, a diode (100) includes a substrate (102) of a first conductivity type, a semiconductor layer (104) of the first conductivity type disposed on the substrate and including a drift region (120), a shield region (110a) o...
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WO/2024/012437A1 |
The present application relates to a lateral insulated gate bipolar transistor and a preparation method therefor. The lateral insulated gate bipolar transistor comprises a drift region (120), a first well region (171), a first electrode ...
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WO/2024/014068A1 |
Provided are: a palladium cobalt oxide thin film; a delafossite-type oxide thin film; a schottky electrode having a delafossite-type oxide thin film; a method for producing a palladium cobalt oxide thin film; and a method for producing a...
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WO/2024/013808A1 |
In a CMOS circuit (C) provided in a frame region as a portion of a driving circuit, a second TFT (9i) having a second semiconductor layer (16b) formed of an oxide semiconductor comprises: a first gate electrode (18b) provided on one fron...
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WO/2024/015287A1 |
Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a semiconductor material between source regions and drain regions of the device. The method includes formation of a cladding ma...
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WO/2024/014149A1 |
An electronic component (1) includes: a lower electrode (51); intermediate electrodes (52) disposed on the lower electrode so as to form projections and recesses together with the lower electrode; and an upper electrode (53) having raise...
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WO/2024/011664A1 |
The embodiments of the present disclosure relate to the field of semiconductors, and in particular to a semiconductor structure and a preparation method. The semiconductor structure comprises: a substrate, a gate dielectric layer, a firs...
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WO/2024/013868A1 |
The present invention increases maximum unipolar current density while relaxing the electric field that acts on a body diode when a transistor is in an off state. A semiconductor device according to the present invention comprises a firs...
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WO/2024/014402A1 |
Provided is a method for manufacturing a semiconductor device, the method comprising: a step for forming an interlayer insulating film having a contact hole above a semiconductor substrate; a step for forming an initial metal film contai...
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WO/2024/011610A1 |
A semiconductor device includes a substrate, an insulating layer, and an epitaxial structure. The first substrate layer is doped with p-type dopants. The second substrate layer is doped with n-type dopants and disposed over the first sub...
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WO/2024/007443A1 |
The present application discloses a GaN-based HEMT having multiple threshold voltages, and a preparation method therefor and an application thereof. The HEMT structure comprises a channel layer and a barrier layer, wherein a two-dimensio...
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WO/2024/008015A1 |
Provided in the present disclosure is an insulated gate bipolar transistor. The transistor comprises: an epitaxial layer; a drift region formed in the epitaxial layer, the drift region having a first doping type; a plurality of super jun...
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WO/2024/010637A1 |
Disclosed herein are compositions comprising gallium oxide doped with carbon, and methods of making and use thereof. In some examples, the methods comprise contacting a first precursor and a second precursor at a first temperature, where...
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WO/2024/009590A1 |
A semiconductor device according to the present invention comprises: a chip which has a first main surface and a second main surface that is on the reverse side of the first main surface; an active region which is provided in the chip; a...
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WO/2024/007386A1 |
Provided in the present application are an array substrate and a display panel. The array substrate comprises a base and a thin film transistor arranged on one side of the base. The capability of the thin film transistor to sense externa...
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WO/2024/007367A1 |
The embodiments of the present disclosure relate to the field of semiconductors. Provided are a manufacturing method for a semiconductor structure, and semiconductor structures. A semiconductor structure comprises a window area, a transi...
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WO/2024/009712A1 |
Provided is a pressure sensor device that can reduce the arrival of liquid at a detection part. This pressure sensor device comprises a base substrate, a detection element that is mounted on an upper surface of the base substrate and has...
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WO/2024/007385A1 |
The present application provides a semiconductor device and an electronic apparatus. The semiconductor device comprises a metal layer arranged on the side of an active layer facing a buffer layer, the metal layer comprises at least one m...
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WO/2024/009591A1 |
This semiconductor device includes: a chip having a first main surface and a second main surface on the opposite side; an active region provided on the chip; an element structure formed in the active region on the first main surface; and...
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WO/2024/007990A1 |
A shorted-anode lateral insulated gate bipolar transistor and a manufacturing method therefor. The transistor comprises: a drift region (103) having a first conductivity type; a collector region (109) provided in the drift region (103) a...
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WO/2024/009096A1 |
A system for quantum information processing (1) is described which includes a body of material (2) having first and second opposite faces (3, 4) and at least one two- dimensional array (7) of defects (5i,k, 5i+1,k, 5i,k+1... 5n,m) embedd...
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WO/2024/007742A1 |
The present invention provides vertically stacked lateral gate-all-around metal-oxide-semiconductor field-effect transistors (referred to as lateral gate-all-around transistors), a structure of a novel three-dimensional integrated circui...
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WO/2024/009047A1 |
The invention relates to a quantum device (100) with semiconductor qubits, comprising at least:• - a layer (104) of a first semiconductor arranged on a layer (106) of a second semiconductor, the forbidden energy band of which is differ...
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WO/2024/009094A1 |
The device includes a body of material, at least one conduction path running through the body of material and formed by irradiation of a region of the material defining the at least one conduction path. The at least one conduction path i...
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WO/2024/007394A1 |
A semiconductor structure (10), a memory and an operation method thereof. The semiconductor structure (10) comprises: a substrate (100); a first gate structure (110) and a second gate structure (120) which are located on a surface of the...
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WO/2024/004350A1 |
This MEMS accelerometer comprises a substrate on which a first beam and movable second beam, and a third beam and movable fourth beam are provided. The first, second, third, and fourth beams are separated by isolation portions into first...
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WO/2024/001197A1 |
The present application relates to a shorted-anode lateral insulated gate bipolar transistor and a manufacturing method therefor. The transistor comprises a drift region, a collector region arranged in the drift region, an anode region, ...
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WO/2024/004079A1 |
The present invention addresses the problem of suppressing variation in device properties that are caused by a buried gate electrode. This nitride semiconductor device comprises a substrate, a first nitride semiconductor layer, a second ...
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WO/2024/005152A1 |
Provided is a technique with which it is possible to increase the breakdown voltage characteristics of a semiconductor region that includes a crystalline oxide semiconductor that includes gallium, or a semiconductor device that has a sem...
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WO/2024/001276A1 |
A preparation method for a Si-based GaN-HEMT device, relating to the technical field of semiconductors. The method comprises the following steps: S100, preparing a U-shaped groove on an epitaxial wafer; S200, sequentially preparing P-typ...
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WO/2024/001693A1 |
Provided are a device, a module, and an apparatus, which have good reliability and long service life. The device can comprise a first semiconductor layer provided on a substrate, a second semiconductor layer epitaxially formed on the fir...
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WO/2024/002792A1 |
A quantum device comprising an array of quantum dots is disclosed. The quantum device comprises a silicon layer in which quantum dots (201) can be induced by respective gates; gates of the inducible quantum dots (201) for controlling an ...
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WO/2024/005789A1 |
IC devices with logic circuits using vertical transistors with backside source or drain (S/D) regions, and related assemblies and methods, are disclosed herein. An example vertical transistor includes an elongated structure (e.g., a nano...
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WO/2024/005870A1 |
Silicon germanium (SiGe)Zsilicon containing superlattice structure and methods for forming the same are provided. Various embodiments utilize SiGe layers in a SiGe/Si superlattice structure, which include varying concentrations of german...
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WO/2024/001422A1 |
The present invention relates to the technical field of power semiconductor devices, and in particular to a trench silicon carbide MOSFET integrated with a high-speed freewheeling diode and a preparation method therefor. The MOSFET of th...
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WO/2024/000431A1 |
The present disclosure relates to a semiconductor device, comprising: a barrier layer; a channel layer, which is adjacent to the barrier layer, wherein a two-dimensional carrier gas is formed at the position in the channel layer close to...
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WO/2024/001468A1 |
Embodiments herein include semiconductor structures that may include a first field-effect transistor (FET) stacked above a second FET in a non-step nanosheet structure, and a bottom contact electrically connected to a first bottom source...
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WO/2024/000433A1 |
The present invention relates to a diode, comprising: a first barrier layer; a second barrier layer; a channel layer located between the first barrier layer and the second barrier layer and comprising a first portion and a second portion...
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WO/2024/004016A1 |
A semiconductor device (90) comprises, in this order: first to third channel layers (41-43) comprising group III-V semiconductors containing Fe and C; and a barrier layer (50) comprising a group III-V semiconductor having a bandgap wider...
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WO/2024/006912A1 |
A field effect transistor including a substrate having an upper surface thereof. An epitaxial layer including n-type is material disposed over the upper surface of the substrate. A P-well including P-type material is diffused within an u...
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WO/2024/000494A1 |
A display substrate, a preparation method therefor, and a display apparatus. The display substrate comprises: a substrate (101), and at least one transistor (100) provided on the substrate (101). The transistor (100) comprises: an active...
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