| Document |
Document Title |
|
WO/2011/163465 |
A method of forming a transistor over a nitride semiconductor layer includes surface-treating a first region of a nitride semiconductor layer and forming a gate over the first region. Surface-treating the first region can cause the trans...
|
|
WO/2011/162147 |
A semiconductor device includes a source line, a bit line, and first to m-th (m is a natural number) memory cells connected in series between the source line and the bit line. Each of the first to m-th memory cells includes a first trans...
|
|
WO/2011/162977 |
Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack (18) located on an upper surface of a semiconductor substrate (12). The at least one FET ga...
|
|
WO/2011/161791 |
Disclosed is a semiconductor device which comprises: a transistor that comprises an electron transit layer (5) and an electron supply layer (6), said layers being laminated in the thickness direction of a substrate (1); an electron trans...
|
|
WO/2011/163169 |
An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. T...
|
|
WO/2011/162104 |
Disclosed is a semiconductor device having a memory cell which comprises a transistor having a control gate and a storage gate. The storage gate comprises an oxide semiconductor and is able to be a conductor and an insulator depending on...
|
|
WO/2011/163171 |
A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having d...
|
|
WO/2011/162177 |
Provided is an electrode layer that does not delaminate from oxide semiconductors and oxide insulating films, and that does not cause any diffusion of copper atoms on oxide semiconductors and into oxide semiconductors nor any extraction ...
|
|
WO/2011/162136 |
In the film formation method, a substrate W, which is a base of a semiconductor device, is firstly held on a holding stage 34. Then, a source gas is adsorbed on the substrate W (FIG. 6(A)). Subsequently, a process chamber 32 is exhausted...
|
|
WO/2011/162001 |
Disclosed is a curable composition which can be sufficiently cured without a heating step at high temperature, has excellent solvent resistance and is capable of producing a cured film with a low dielectric constant. The curable composit...
|
|
WO/2011/160591 |
A VDMOS device and a manufacturing method thereof are provided. The method includes: providing a semiconductor substrate and forming a first N-type epitaxial layer on the semiconductor substrate (S1); forming a hard mask layer with openi...
|
|
WO/2011/161976 |
A step for preparing a laminate (TX) is performed in such a manner that each substrate of a first single crystal substrate group (10a) and a first base substrate (30a) face each other, each substrate of a second single crystal substrate ...
|
|
WO/2011/163318 |
A gated III-V semiconductor structure and a method for fabricating the gated III-V semiconductor structure includes a threshold modifying dopant region within a III-V semiconductor barrier layer at the base of an aperture through a passi...
|
|
WO/2011/163164 |
An advanced transistor with threshold voltage set dopant structure includes a gate with length Lg and a well doped to have a first concentration of a dopant. A screening region is positioned between the well and the gate and has a second...
|
|
WO/2011/161906 |
Provided is a method for producing a silicon carbide Schottky barrier diode that has high performance at low on-resistance, said method maintaining productivity without there being a reduction in yield. A silicon carbide substrate is thi...
|
|
WO/2011/162242 |
Disclosed is a TFT substrate (100A) comprising a thin film transistor, a gate wiring line (3a) and a source wiring line (13as) all of which are formed on a substrate, and additionally comprising first and second terminals (40a, 40b) whic...
|
|
WO/2011/161338 |
The SRAM memory cell is equipped with two access transistors and two inverters each comprising two transistors. An access transistor is associated with an inverter. Each transistor comprises a semiconductor zone (2) that protrudes from a...
|
|
WO/2011/163344 |
A low voltage protection device that includes a silicon substrate comprises an inner layer of a first dopant type. The device also includes a first outer layer of a second dopant type disposed adjacent a first surface of the inner layer ...
|
|
WO/2011/161721 |
In conventional power semiconductor devices, each of which is provided with a sense pad, and performs switching at a high speed, there have been some cases where a high voltage is generated in a well region of a lower portion of the sens...
|
|
WO/2011/162725 |
According to embodiments of the present invention, a nanowire transistor is provided. The nanowire transistor includes a carrier; a vertical nanowire structure extending from the carrier, the vertical nanowire structure comprising a chan...
|
|
WO/2011/162199 |
Disclosed is a method for controlling an electric current, which comprises: a step of preparing an element device (20) that comprises an electrode (22), an electrode (24), and an organic semiconductor layer (26) that is arranged between ...
|
|
WO/2011/162172 |
Disclosed is a quantum computer that stabilizes the values of quantum bits that are employed thereby, increases the number of quantum bits per element to 100 or more, ensures the stability of the quantum state and the controllability of ...
|
|
WO/2011/161097 |
A phase control thyristor having a new design comprising a main gate structure (306) and a plurality of local emitter shorts dots (304) arranged in a shorts pattern on a cathode side of the thyristor is proposed. Therein, the main gate s...
|
|
WO/2011/160467 |
A method for manufacturing a contact(220) and a semiconductor device with the contact(220) are provided. The method includes the following steps: forming a groove contact(220) with larger size firstly, then forming one or more dielectric...
|
|
WO/2011/161714 |
Disclosed is a method for crystallizing a silicon thin film, wherein the sizes of the crystal grains of the silicon thin film are made uniform. The method includes: a second step wherein a first gate electrode (2) having a first reflecti...
|
|
WO/2011/162243 |
Disclosed is a low-loss Gallium-Nitride semiconductor element that fundamentally eases peak electrical fields that arise locally in conductor channels, simultaneously increasing resilience and eliminating current collapse at a practical ...
|
|
WO/2011/162715 |
The present invention provides a substrate (1) with a bulk layer (3) and a buffer layer (4) having a thickness of less than 2 μm arranged on the bulk layer (3) for growth of a multitude of nanowires (2) oriented in the same direction on...
|
|
WO/2011/161901 |
Disclosed are a method for forming a polycrystalline silicon thin film, wherein the polycrystalline silicon thin film can be formed at a high speed, a polycrystalline silicon thin film substrate, a silicon thin film solar cell, and a sil...
|
|
WO/2011/160338 |
Provided are a metal-oxide-semiconductor (MOS) device structure and a manufacturing method thereof. The MOS device structure includes: a Si substrate (1) and an active region located on the Si substrate (1), the active region including a...
|
|
WO/2011/160422 |
A method for forming a semiconductor device is provided. The method comprises: forming at least one gate stack structure and inter-layer material layers (160, 162) between the gate stack structures on a semiconductor substrate (100); det...
|
|
WO/2011/160937 |
The present invention relates to a method for fabricating a structure such as a transistor, said method comprising the steps of: a. providing a continuous metal layer on an insulating substrate; b. providing a dielectric layer on the con...
|
|
WO/2011/161016 |
A back-gated field effect transistor (FET) includes a substrate, the substrate comprising top semiconductor layer on top of a buried dielectric layer on top of a bottom semiconductor layer; a front gate located on the top semiconductor l...
|
|
WO/2011/160922 |
A method for forming a field effect transistor (FET) includes depositing a channel material on a substrate, the channel material comprising one of graphene or a nanostructure; forming a gate over a first portion of the channel material; ...
|
|
WO/2011/161975 |
Provided is an epitaxial growth substrate wherein the occurrence of a crack at the end of a wafer when a group-III nitride semiconductor is heteroepitaxially grown on a Si single crystal substrate is suppressed. A region (A) is an outerm...
|
|
WO/2011/163465 |
A method of forming a transistor over a nitride semiconductor layer includes surface-treating a first region of a nitride semiconductor layer and forming a gate over the first region. Surface-treating the first region can cause the trans...
|
|
WO/2011/162977 |
Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack (18) located on an upper surface of a semiconductor substrate (12). The at least one FET ga...
|
|
WO/2011/161875 |
Disclosed is an active matrix substrate (20) comprising an insulating substrate (10a), a gate electrode (11) which is arranged on the insulating substrate (10a), a gate insulating layer (12) which is so arranged as to cover the gate elec...
|
|
WO/2011/160337 |
A MOS device structure for preventing floating body effect and self-heating effect and the manufacturing method thereof are provided. The MOS device structure comprises a Si substrate (1) and an active area including a channel area (31) ...
|
|
WO/2011/161910 |
Disclosed is a light-emitting display device that uses side contact structures in order to maintain TFT characteristics (ON current) of a linear region and wherein: a TFT that makes up a switching transistor has a thicker semiconductor l...
|
|
WO/2011/161917 |
The disclosed acceleration sensor comprises a frame, a mass, a beam that connects the mass to the frame, and a detection unit that detects deflection of the beam. The detection unit comprises: a first contact part and second contact part...
|
|
WO/2011/163058 |
Provided herein are sensors and methods for determining properties of single cells, such as cell mass. Sensors disclosed herein include resonant sensors having a suspended platform designed to exhibit a uniform vibration amplitude. Metho...
|
|
WO/2011/160463 |
A semiconductor structure and a fabricating method thereof are provided. The semiconductor structure comprises: a semiconductor substrate (1000); a channel region formed in the semiconductor substrate (1000); a gate stacking structure fo...
|
|
WO/2011/158780 |
Disclosed is a semiconductor device wherein an n-channel type first thin film transistor and a p-channel type second thin film transistor are provided on a same substrate. The first thin film transistor has a first semiconductor layer (1...
|
|
WO/2011/157814 |
A power semiconductor device with a wafer (10) comprising the following layers between an emitter electrode (2) on an emitter side (11) and a collector electrode (25) on a collector side (15) is provided: - an (n-) doped drift layer (3),...
|
|
WO/2011/158703 |
An object is to provide a semiconductor device including an oxide semiconductor, which has stable electric characteristics and high reliability. In a transistor including an oxide semiconductor film, the oxide semiconductor film is subje...
|
|
WO/2011/158424 |
Disclosed is a liquid crystal display device comprising a thin film transistor substrate, in which changes in the potential of a pixel electrode can be suppressed without decreasing the aperture ratio of a pixel. Gate wiring lines and so...
|
|
WO/2011/158319 |
Disclosed is a method for manufacturing a semiconductor device, wherein an interlayer insulating film (PIL) is formed on a semiconductor substrate (1S), and after performing CMP for forming a plug (PL1) in the interlayer insulating film ...
|
|
WO/2011/157461 |
Exemplary embodiments include a method for fabricating a heterojunction tunnel field-effect-transistor (FET), the method including forming a gate region on a silicon layer of a silicon-on-insulator (SOI) substrate, forming a drain region...
|
|
WO/2011/158533 |
Disclosed is a method for manufacturing a SiC semiconductor device, which is provided with: a step (S4) of forming a first oxide film on the first surface of a SiC semiconductor; a step (S5) of removing the first oxide film; and a step (...
|
|
WO/2011/158427 |
Disclosed is an active matrix substrate (20a) which is provided with: a plurality of gate lines (14a) which are arranged so as to each extend in parallel to one another; a plurality of source lines (16a) which are arranged so as to exten...
|
