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Matches 1 - 50 out of 274,349

Document Document Title
WO/2019/155768A1
The invention provides a power semiconductor device wherein leakage currents caused by a defective layer have been reduce and wherein the variations in threshold voltage are small by comprising: a single crystal n-type semiconductor subs...  
WO/2019/156761A1
An integrated circuit includes a silicon carbide (SiC) epitaxial layer disposed on a SiC layer, wherein the SiC epitaxial layer has a first conductivity-type and the SiC layer has a second conductivity-type that is opposite to the first ...  
WO/2019/154219A1
An insulated gate bipolar transistor (IGBT) power device, comprising: a p-type collector region; an n-type drift region located above the p-type collector region; a plurality of first grooves, a second groove being disposed below each of...  
WO/2019/153724A1
A preparation method for a fin field-effect transistor (FinFET) device, the method comprising the following steps: S01: preparing a fin structure (2) on a substrate (1), and forming a gate medium and a gate electrode (3) at a middle posi...  
WO/2019/157384A1
A method of forming doped regions by diffusion in gallium nitride materials includes providing a substrate structure including a gallium nitride layer and forming a mask on the gallium nitride layer. The mask exposes one or more portions...  
WO/2019/155329A1
Provided is a semiconductor device having excellent electrical properties. The semiconductor device is provided with: a first metal oxide layer that has a first region and a second region and third region which sandwich the first region ...  
WO/2019/154385A1
Provided are a high-density three-dimensional nanowire channel array and fabrication method thereof; the high-density three-dimensional nanowire channel array fabricated by said method comprises a substrate material serving as a base, a ...  
WO/2019/155957A1
Provided are: a magnetoresistance effect element that can be used as an element constituting a neural network, etc.; and a circuit device and circuit unit in which the magnetoresistance effect element is used. A write current pulse Pw1 f...  
WO/2019/156752A1
A transistor comprises a pair of source/drain regions having a channel there-between. A transistor gate construction is operatively proximate the channel. The channel comprises Si1-yGey, where "y" is from 0 to 0.6. At least a portion of ...  
WO/2019/156215A1
This semiconductor device is provided with a first transistor (T1) and a second transistor (T2). The first transistor (T1) includes a first body layer (113) and a first connection portion (113A). The second transistor (T2) includes a sec...  
WO/2019/156673A1
Techniques and mechanisms for providing functionality of a transistor which comprises a conformal layer of a gate work function silicide. In an embodiment, the transistor comprises a channel region and a gate dielectric which extends and...  
WO/2019/154222A1
A method for manufacturing an ohmic contact of a nitride semiconductor device, comprising: forming on a GaN substrate (1) a metal stack structure (2) containing an Al layer, performing low-temperature oxidation in an oxygen atmosphere to...  
WO/2019/156121A1
One embodiment of the present invention provides a semiconductor wafer 1 which is provided with: a substrate 10 that is mainly composed of Si; a buffer layer 11 that is formed on the substrate 10 and comprises an AlN layer 11a as the low...  
WO/2019/153431A1
The present invention relates to the technical field of semiconductor devices, and provides a preparation method for a hot electron transistor in a high frequency gallium nitride (GaN)/graphene heterojunction. The method comprises: first...  
WO/2019/155318A1
The present invention provides a high-definition display device. The present invention also provides a display device with low power consumption. The present invention further provides a highly reliable display device. Specifically provi...  
WO/2019/155504A1
This semiconductor device is provided with: a main groove formed in a principal surface of a substrate; a semiconductor region formed so as to abut on a surface of the main groove; an electron supply region which is formed so as to at le...  
WO/2019/156696A1
A compact and thermally efficient traction drive motor inverter featuring an integrated printed circuit board carrying both power circuitry and signal circuitry on separate electrically isolated layers without significant electromagnetic...  
WO/2019/155783A1
A silicon carbide substrate is provided with, in a first principal surface thereof, a first trench and a second trench. The first trench is defined by a first lateral face and a first bottom face. The second trench is defined by a second...  
WO/2019/157222A1
A vertical IGBT device is provided. The vertical IGBT device includes a substrate having a first conductivity type. A drift region of the first conductivity type formed on the top surface of the substrate. The bottom surface of the subst...  
WO/2019/155701A1
Provided herein is a display device that is able to suppress connection failures between wiring layers in a pixel circuit. The display device is provided with: a first wiring layer that includes a first pad part and a first wiring part c...  
WO/2019/151018A1
The present invention provides a method for manufacturing a semiconductor device provided with: a semiconductor fin comprising a source area and a drain area, which constitute an electric field effect; and a fixed potential line provided...  
WO/2019/148327A1
A thin-film transistor and a manufacturing method therefor, a gate drive circuit and a flat panel display. The thin-film transistor comprises: a substrate (11); one of a source layer (12) and a drain layer (14), which is provided on the ...  
WO/2019/148892A1
A thin film transistor and a manufacturing method thereof, a display substrate and a display device. The thin film transistor comprises a gate (2), a semiconductor layer (4) and a gate insulation layer (3) disposed between the gate (2) a...  
WO/2019/149004A1
A thin film transistor and a preparation method therefor, a display apparatus, and a method for detecting ion concentration. The transistor comprises a gate insulating layer (40), wherein the gate insulating layer (40) comprises a solid-...  
WO/2019/151441A1
One embodiment of the present invention provides a semiconductor wafer 1 that is provided with: a substrate 10 which is mainly composed of Si; a buffer layer 11 which is formed on the substrate 10 and is configured from a nitride semicon...  
WO/2019/148592A1
A low-temperature polycrystalline silicon thin-film transistor and a manufacturing method thereof. The thin-film transistor comprises: an annular polycrystalline silicon layer (300) on a substrate (100), the shape of a lengthwise section...  
WO/2019/151022A1
This manufacturing method, in which a pair of semiconductor fins standing upright from a substrate are provided and a fixed potential line conductive material, to which source areas of the semiconductor fins are connected, is provided, i...  
WO/2019/023022A8
A copolymer comprising a repeat unit A, wherein repeat unit A comprises a 1,2,5,6-naphthalenediimide monomer and at least one repeat unit B, wherein repeat unit B comprises an aryl group. The copolymer can be regio-random or regio-regular.  
WO/2019/150526A1
This invention comprises: a source electrode 13 formed on the surface of a semiconductor substrate 11 and joined to the semiconductor substrate 11 at both a source electrode 13a of a first contact region, which is in a region for ohmic c...  
WO/2019/152090A1
A method for fabricating an electrically isolated diamond nanowire includes forming a diamond nanowire on a diamond substrate, depositing a dielectric or a polymer on the diamond nanowire and on the diamond substrate, planarizing the die...  
WO/2019/151277A1
This semiconductor device comprises: a first film (32a, 132a) laminated over a nitride semiconductor; a second film (32b, 132b) laminated over the first film; a third film (32c, 132c) laminated over the second film; and a gate electrode ...  
WO/2019/151254A1
In the present invention, a garnet thin film (12) is laminated on an electrically conductive substrate (11) connected to ground, a magnetoelectric coupling layer (13) is provided on the garnet thin film, and in the magnetoelectric coupli...  
WO/2019/150856A1
This semiconductor device comprises a stacked structure in which channel forming region layers CH1, CH2 and gate electrode layers G1, G2, G3 are alternately stacked on a substrate 50. A lowermost layer of the stacked structure is occupie...  
WO/2019/149581A1
The invention relates to a short-circuit semiconductor component (15, 22, 29, 34, 40, 45, 49, 52, 56, 59, 62, 66, 70, 72) comprising a semiconductor body (16) having a rear-side base region (6) of a first conduction type, an inner region...  
WO/2019/151024A1
The present invention provides a method for manufacturing a semiconductor device, the method comprising: a first step for preparing, in a bottom section of a recess part of an insulation layer, an intermediate body provided with a base b...  
WO/2019/151377A1
Provided is a technique for layering a sheet battery. A layering method of this embodiment comprises: a step in which a plurality of sheet batteries (10), each having an opening (31), are prepared; and a step in which the plurality of sh...  
WO/2019/150947A1
This semiconductor device has a structure formed by alternately disposing, in parallel, N layers of gate electrode layers G and (N-1) layers of channel forming region layers CH (where N≥3) on an insulating material layer 61 of a substr...  
WO/2019/151508A1
This nanocrystal film manufacturing method includes a light radiation step for radiating light onto the surface of a metal member immersed in water, thereby forming on the surface of the metal member a nanocrystal film having a prescribe...  
WO/2019/145813A1
Provided is a semiconductor device having a high on-current. The semiconductor device comprises: a first oxide; a second oxide over the first oxide; a third oxide over the second oxide; a first insulator over the third oxide; a conductor...  
WO/2019/146354A1
The present invention provides a laser irradiating apparatus, a projection mask, and a laser irradiating method which are capable of reducing the imbalance of characteristics of laser light irradiated onto a channel area, and reducing th...  
WO/2019/147402A1
A method for forming a gate structure for a Field Effect Transistor includes providing a semiconductor. A dielectric layer is formed over the semiconductor with an opening therein over a selected portion of the semiconductor. A depositio...  
WO/2019/144915A1
A high electron mobility transistor (HEMT) epitaxy structure having a high-resistance GaN-based buffer layer prepared by growing a p-i-n multi-quantum-well heterojunction, and a method therefor. By utilizing the great difference between ...  
WO/2019/146264A1
The problem to be addressed by the present invention is to achieve a display device having a TFT that uses an oxide semiconductor which is highly reliable. In summary, the present invention is a display device containing a base board hav...  
WO/2019/146695A1
This sensor chip comprises: a base plate; first supporting portions; a second supporting portion around which the first supporting portions are disposed, and which is disposed at the center of the base plate; first detection beams linkin...  
WO/2019/145818A1
Provided is a semiconductor device having a high on-state current. The semiconductor device comprises: a first oxide; a second oxide over the first oxide; a third oxide over the second oxide; a first insulator over the third oxide; a con...  
WO/2019/147859A2
Synaptic resistors (synstors), and their method of manufacture and integration into exemplary circuits are provided. Synstors are configured to emulate the analog signal processing, learning, and memory functions of synapses. Circuits in...  
WO/2019/145277A1
To provide a lanthanoid compound for forming a lanthanoid-containing thin film that has high stability and a melting point lower than the use temperature, and therefore can be used in a liquid state; and a film formation process. SOLUTIO...  
WO/2019/145407A1
A synthetic diamond material comprises a surface, wherein the surface comprises a first surface region comprising a first concentration of quantum spin defects. A second surface region has a predetermined area and is located adjacent to ...  
WO/2019/146945A1
The present invention relates to a high electron mobility transistor and a method for manufacturing the same and, more specifically, to a high electron mobility transistor comprising a crack-free high reliability field plate and a method...  
WO/2019/145827A1
Provided is a semiconductor device which suppresses variations in characteristics, deterioration of elements, or charging phenomena that lead to dielectric breakdown. The semiconductor device comprises: a first transistor over a substrat...  

Matches 1 - 50 out of 274,349