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Matches 1 - 50 out of 264,521

Document Document Title
WO/2018/011648A1
Provided is a novel metal oxide. Specifically provided is a metal oxide having a plurality of energy gaps, wherein the metal oxide is provided with a first layer in which the energy level at the bottom of the conduction band of the energ...  
WO/2018/013713A2
A semiconductor device includes an upper and lower mirror. At least one active region for light generation is between the upper and lower mirror. At least one cavity spacer layer is between at least one of the upper and lower mirror and ...  
WO/2018/012546A1
Provided is a manufacturing method for a semiconductor laminated film, which comprises a step for forming a semiconductor layer containing silicon and germanium on a silicon substrate via sputtering, wherein, during sputtering, the film ...  
WO/2018/010545A1
A Silicon Carbide (SiC) power device (100, 200, 300) employing a heterojunction termination comprises: a cathode electrode (110, 210, 310), a substrate layer (120, 220, 320), an N-type SiC extension layer (130, 230, 330), an anode electr...  
WO/2018/012508A1
Provided are: a novel aromatic compound which has properties of a semiconductor showing excellent carrier mobility; an organic semiconductor material and a composition for thin film formation use, each of which contains the compound; an ...  
WO/2018/012868A1
Disclosed are a switching atomic transistor having a diffusion barrier layer and a method for operating same. As a result of introducing a diffusion barrier layer onto an intermediate layer having a variable resistance characteristic, a ...  
WO/2018/012241A1
The present invention relates to a semiconductor device and is provided with: a first semiconductor layer which is disposed on a first main surface of a semiconductor substrate; a plurality of first semiconductor regions which are select...  
WO/2018/012510A1
This semiconductor device comprises: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type, which is arranged on the first semiconductor layer; an MIS transistor structure wh...  
WO/2018/011646A1
A novel metal oxide is provided. A semiconductor device with favorable electrical characteristics is provided. The metal oxide has a plurality of energy gaps, and includes a first region having a high energy level of a conduction band mi...  
WO/2018/011645A1
A novel metal oxide or a novel sputtering target is provided. A sputtering target includes a conductive material and an insulating material. The insulating material includes an oxide, a nitride, or an oxynitride including an element M1. ...  
WO/2018/010056A1
A reverse conducting insulated gate bipolar transistor structure and a corresponding manufacturing method therefor, and a high-performance RC-IGBT structure capable of being manufactured without a thin-wafer process; provided is an RC-IG...  
WO/2018/013459A1
A method of fabricating ultra-thin semiconductor devices includes forming an array of semiconductor dielets mechanically suspended on a frame with at least one tether connecting each semiconductor dielet of the array of semiconductor die...  
WO/2018/010151A1
A preparation method for a field effect transistor and a field effect transistor, relating to the field of technological development of field effect transistors. The preparation method comprises: forming a source electrode (2), a drain e...  
WO/2018/012159A1
According to the present invention, first to third electric field relaxation layers (11-13) are provided in an edge termination region so as to be concentric around the circumference of an active region. First to third p-type spatial mod...  
WO/2018/011647A1
A novel metal oxide is provided. The metal oxide has a plurality of energy gaps, and includes a first region having a high energy level of a conduction band minimum and a second region having an energy level of a conduction band minimum ...  
WO/2018/012598A1
This semiconductor apparatus has an MIS structure that includes: a semiconductor layer; a gate insulating film on the semiconductor layer; and a gate electrode on the gate insulating film. The gate insulating film has a laminate structur...  
WO/2018/008422A1
An inductor (101) with an ESD protection function is provided with an LGA-type chip inductor (1) and a diode chip (2). The LGA-type chip inductor (1) has: a base material (10) having a first main surface (VS1), i.e., a mounting surface; ...  
WO/2018/009169A1
An apparatus including a transistor device including a channel including germanium disposed on a substrate; a buffer layer disposed on the substrate between the channel and the substrate, wherein the buffer layer includes silicon germani...  
WO/2018/008181A1
The present invention relates to an electrostatic capacitance type sensor manufactured using MEMS technology, and provides a technique which enables a high SN ratio to be obtained, and which enables an increase in resistance to input pre...  
WO/2018/006739A1
A microwave transistor of a patterned gate structure. The transistor is provided with a patterned region between a source (5) and a drain (6) on a barrier layer (4). Within the patterned region, the surface of the barrier layer partially...  
WO/2018/009158A1
An apparatus including an integrated circuit device structure including a metal layer including a composition of General Formula I: M-Alm-X1 n-X2 p-Cq-Or, wherein M includes a metal selected from one or more of titanium, zirconium, hafni...  
WO/2018/009162A1
Embodiments are generally directed to a semiconductor device with released source and drain. An embodiment of a method includes etching a buffer layer of a semiconductor device to form a gate trench under a gate channel portion of a chan...  
WO/2018/006779A1
According to the embodiments of the present invention, the doping for a surrounding medium of a two-dimensional semiconductor or local filling of a solid material in the surrounding medium of the semiconductor is adopted to form a fillin...  
WO/2018/009163A1
An apparatus including a transistor device including a channel disposed on a substrate between a source and a drain, a gate electrode disposed on the channel, wherein the channel includes a length dimension between source and drain that ...  
WO/2018/009175A1
A high speed single transistor suitable for a non-volatile memory cell is described. In one example, the memory cell has a source, a drain coupled to the source through a gate channel, a gate coupled to the gate channel, a floating gate ...  
WO/2018/009161A1
An apparatus including a transistor device including a body including a channel region between a source region and a drain region; and a gate stack on the body in the channel region, wherein at least one of the source region and the drai...  
WO/2018/008527A1
All of the intervals between adjacent p-type guard rings (21) are made to be equal to or smaller than the interval between p-type deep layers (5). As a result, the intervals between the p-type guard rings (21) become larger, i.e. trenche...  
WO/2018/006441A1
A thin film transistor (1), comprising an active layer (13) formed on a substrate (00). The active layer (13) comprises a first semiconductor layer (131) and a second semiconductor layer (132) arranged in a stacked manner. The material o...  
WO/2018/008528A1
The intervals in portions of a frame-like part (32) and a p-type guard ring (21) at the side of a cell section are narrowed in comparison to other portions, and the portions in which the intervals are narrowed are formed as dot line port...  
WO/2018/007918A1
A method for preparation of high-quality graphene on the surface (0001) of silicon carbide by superficial graphitisation of the compound in a stream of silicon atoms from an external sublimation source is disclosed.  
WO/2018/009931A1
Provided are van der Waals (VDW) films comprising one or more transition metal chalcogenide (TMD) films. Also provided are methods of making VDW films. The methods are based on transfer of monolayer TMD films under vacuum, for example, u...  
WO/2018/008529A1
The widths of p-type guard rings (21) are set in accordance with the intervals between adjacent p-type guard rings (21), and the widths increase as the intervals between the p-type guard rings (21) become larger. Furthermore, the width o...  
WO/2018/008526A1
P-type extension areas (40) are connected to the tips of p-type connecting layers (30). As a result of forming these p-type extension areas (40), areas in which the intervals between the p-type connecting layers (30) and p-type guard rin...  
WO/2018/006412A1
The present application discloses a thin film transistor including a base substrate; an active layer on the base substrate having a first semiconductor region, a second semiconductor region, and a plurality of semiconductor bridges each ...  
WO/2018/008524A1
A semiconductor device in which a semiconductor chip (2) has electrode portions (19, 24) which are electrically connected to bonding members (5 to 7), wherein electric current flows through the bonding members (5 to 7) to the semiconduct...  
WO/2018/009026A1
Disclosed are a nanoimprint replica mold, a manufacturing method therefor, and a nanoimprint replica mold manufacturing device. The nanoimprint replica mold of the present invention comprises: a base made of a plastic film; a stamping un...  
WO/2018/004046A1
Disclosed are a two-dimensional semiconductor in which an energy band gap changes with thickness, a manufacturing method therefor, and a semiconductor device comprising the same. A two-dimensional semiconductor according to an embodiment...  
WO/2018/004770A2
Colloidal nanocrystal electronic devices including multiple types of nanocrystal device elements including nanocrystal metallic electrodes, nanocrystal insulators, and nanocrystal insulators. Colloidal nanocrystal electronic devices may ...  
WO/2018/004632A1
An apparatus is described. The apparatus includes a FINFET transistor. The FINFET transistor comprises a tapered subfin structure having a sidewall surface area that is large enough to induce aspect ratio trapping of lattice defects alon...  
WO/2018/004565A1
Techniques are disclosed for forming III-N semiconductor devices including integrated diamond heat spreader structures. In accordance with some embodiments, through-hole features may be formed in a silicon (Si) or other semiconductor sub...  
WO/2018/002757A1
Provided is a novel transistor. This transistor is provided with a gate electrode, a first and a second conductor, a gate insulator, and first to third metal oxides. The gate insulator is positioned between the gate electrode and the fir...  
WO/2018/003219A1
The present invention has a substrate, an electron transit layer comprising a group III nitride semiconductor provided on the substrate, and an electron supply layer comprising a group III nitride semiconductor provided on the electron t...  
WO/2018/004554A1
Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, a doped layer, and a bar...  
WO/2018/004700A1
Embodiments herein describe techniques for a semiconductor device comprising a channel having a first semiconductor material; a source contact coupled to the channel, comprising a first Heusler alloy; and a drain contact coupled to the c...  
WO/2018/004654A1
Techniques are disclosed for forming group III-N transistors including a source to channel heterostructure design. As will be apparent in light of this disclosure, the source to channel heterostructure design may include inserting a rela...  
WO/2018/004660A1
A gate stack structure is disclosed for inhibiting charge leakage in III-V transistor devices. The techniques are particularly well-suited for use in enhancement-mode MOSHEMTs, but can also be used in other transistor designs susceptible...  
WO/2018/004008A1
Provided are: a novel and useful oxide semiconductor film which has good p-type semiconductor characteristics; and a method for producing this oxide semiconductor film. According to the present invention, a mist is formed by atomizing a ...  
WO/2018/003001A1
The present invention comprises: element isolation regions (14); projected semiconductor regions (11); a plurality of first gate electrodes (12A) which are formed between a pair of opposing ends of the element isolation regions and each ...  
WO/2018/004680A1
Self-aligned gate edge trigate and finFET devices and methods of fabricating self-aligned gate edge trigate and finFET devices are described. In an example, a semiconductor structure includes a plurality of semiconductor fins disposed ab...  
WO/2018/004607A1
Techniques are disclosed for forming integrated circuits configured with co-integrated group III-N transistors and group IV transistors. The diverse transistors can be formed in a neighboring fashion or otherwise adjacent to one another ...  

Matches 1 - 50 out of 264,521