Login| Sign Up| Help| Contact|

Patent Searching and Data


Matches 1 - 50 out of 267,709

Document Document Title
WO/2018/128193A1
The present invention provides a hexagonal boron nitride thin film and a novel method for manufacturing a hexagonal boron nitride thin film that is suitable for application to electronics and other industrial uses, and whereby it is poss...  
WO/2018/126703A1
A dual-gate thin-film transistor and a preparation method therefor, an array substrate and a display apparatus. The dual-gate thin-film transistor comprises: a base substrate (10), and a first gate electrode (130), a first gate insulatio...  
WO/2018/127514A1
Three port active semiconductor device (1) comprising an active, reverse biased, semiconductor junction region. The active semiconductor junction region has an intrinsic capacitance (Ci, 11) which is non-linear as function of a voltage a...  
WO/2018/126318A1
A process for purifying semiconducting single-walled carbon nanotubes (sc- SWCNTs) extracted with a conjugated polymer, the process comprising exchanging the conjugated polymer with an s-tetrazine based polymer in a processed sc-SWCNT di...  
WO/2018/121109A1
A flash storage structure and a manufacturing method therefor. The method comprises: depositing a polysilicon layer on a substrate structure (S110); forming, using the polysilicon layer, a floating gate and a field oxide structure coveri...  
WO/2018/122866A1
The invention provides a universal semiconductor switch. The universal semiconductor switch includes a switching arrangement having an input and an output, at least one trigger circuit operably coupled to the switching arrangement and a ...  
WO/2018/121136A1
A flash memory storage structure and a manufacturing method therefor. The method comprises: depositing a polycrystalline silicon layer (200) on a substrate structure (100); using the polycrystalline silicon layer (200) to form a floating...  
WO/2018/125082A1
Techniques are disclosed for forming transistors for forming Ge-rich transistors employing a Si-rich source/drain (S/D) contact resistance reducing layer. As can be understood based on this disclosure, the Si-rich layer may be utilized a...  
WO/2018/121131A1
A junction field-effect transistor and a fabricating method thereof. The junction field-effect transistor comprises a substrate (100), and an epitaxial layer (200) and a dielectric mask layer sequentially arranged on the substrate. A fir...  
WO/2018/126093A1
Disclosed examples include a resistor (110) comprising a semiconductor structure (118) having a length dimension with first and second ends (126, 128) spaced from one another and an intermediate region (130) between the first and second ...  
WO/2018/125148A1
The disclosure illustrates systems and methods for removing at least some excess gate material of a FinFET transistor. A FinFET transistor with the excess gate material removed may include a gate with a T-shaped cross-section. The narrow...  
WO/2018/125519A1
Ferroelectric-modulated Schottky non-volatile memory is disclosed. A resistive memory element is provided that is based on a semiconductive material. Metal elements are formed on a semiconductive material at two places such that two semi...  
WO/2018/119958A1
A thin film transistor (100), a preparation method for the thin film transistor (100) and an array substrate, the thin film transistor (100) comprising a gate electrode (102), an active layer (104), a source electrode (106), a drain elec...  
WO/2018/125723A1
A method of forming a semiconductor device includes providing an engineered substrate. The engineered substrate includes a polycrystalline ceramic core, a barrier layer encapsulating the polycrystalline ceramic core, a bonding layer coup...  
WO/2018/119654A1
A thin film transistor, comprising a substrate (10), a gate electrode (11), at least one auxiliary electrode (12), an insulating layer (13), a semiconductor layer (14), a source electrode (15), and a drain electrode (16), the gate electr...  
WO/2018/119879A1
Provided in the present invention are a thin film transistor and a manufacturing method therefor. The manufacturing method for a thin film transistor of the present invention, by means of forming a first photoresist layer on an upper sid...  
WO/2018/123659A1
Provided is a method for manufacturing a semiconductor device, the semiconductor device comprising a substrate (1), and an oxide semiconductor TFT that is supported by the substrate (1) and includes an oxide semiconductor film as an acti...  
WO/2018/123660A1
Provided is a semiconductor device comprising a substrate (21) and an oxide semiconductor TFT (20) supported by the substrate, said oxide semiconductor TFT (20) comprising: an oxide semiconductor layer (27) that includes In, Ga, and Zn; ...  
WO/2018/125035A1
Techniques are disclosed for forming transistors including final source/drain (S/D) material processed after replacement gate processing. In some cases, at least one of the S/D regions of a transistor may initially be formed with sacrifi...  
WO/2018/125206A1
A 1T-1R memory cell includes a transistor structure where an ambipolar layer is disposed on an insulator layer formed on a substrate. The transistor further includes a gate dielectric layer that is disposed on the ambipolar layer and a g...  
WO/2018/123435A1
A semiconductor device is provided with: a substrate (10); an insulating film (12) formed between the top surface of the substrate (10) and a floating gate (13); a first oxide film (21) formed on the top surface of the floating gate (13)...  
WO/2018/125034A1
Integrated circuit structures are described that include back end memory devices that are integrated into one or more back end interconnect layers of an integrated circuit. Examples of the back end memory devices described include one tr...  
WO/2018/125065A1
An apparatus is provided which comprises: a beam disposed in a void disposed above a substrate, the beam having anchored portions at opposite ends, wherein the beam comprises an atomic thick layer of 2-D material, a first conductive regi...  
WO/2018/123188A1
The purpose of the present invention is to provide a temperature characteristic adjustment circuit capable of making an adjustment to various positive/negative temperature characteristics with extremely small characteristic variation, an...  
WO/2018/123799A1
A semiconductor device (1) is provided with: an N-type semiconductor substrate (32) made of silicon; an N-type low-concentration impurity layer (33) in contact with an upper surface of the semiconductor substrate (32); a metal layer (31)...  
WO/2018/121132A1
Provided are a Lateral Double-diffused MOS (LDMOS) device and a method for manufacturing same. A LOMOS device comprising a substrate (10), a drift region (20) located on the substrate (10), a source zone (201) and a drain zone (220) prov...  
WO/2018/125191A1
A subfin liner is described for use with FinFET devices. In one example, a FinFET device includes a semiconductor substrate having a front side surface, a fin extending from the front side surface, a node of the fin applied over the fin,...  
WO/2018/125118A1
Techniques are disclosed for forming integrated circuit (IC) devices that include ferroelectric field-effect transistors (FE-FETs) formed in the back end of the IC structure. The disclosed back-end FE-FET devices may be implemented with ...  
WO/2018/123664A1
The present invention provides a semiconductor substrate having: a substrate; a nitride crystal layer comprising a single layer or multiple crystal layers of a group III nitride; and a cap layer. The substrate, the nitride crystal layer,...  
WO/2018/121440A1
Provided is a laterally diffused metal-oxide semiconductor field-effect transistor, comprising a second conductivity type substrate (101), a first conductivity type drift region (102) on the substrate (101), a second conductivity type ch...  
WO/2018/125112A1
An integrated circuit structure includes a channel body including a first group IV semiconductor material (e.g., Si1-xGex, where 0.2 ≤ x ≤ 1.0), and a sub-fin below the channel body, the sub-fin including a second group IV semiconduc...  
WO/2018/121600A1
The invention discloses a super junction power transistor and a preparation method thereof. The super junction power transistor comprises a first substrate type epitaxial layer (200) of a first doping type and a second substrate type epi...  
WO/2018/125074A1
Asymmetric transistors and related methods and devices are disclosed. A transistor includes a semiconductor material doped with a first type of charge carriers along the gate oxide according to an asymmetric doping profile with a halo re...  
WO/2018/120170A1
Disclosed are a manufacturing method for a tunnelling field-effect transistor, and a tunnelling field-effect transistor. The manufacturing method comprises: first using a spindle structure (13) to define a source region (21), and then fo...  
WO/2018/125211A1
A semiconductor device includes a silicon pillar disposed on a substrate, the silicon pillar has a sidewall. A group III-N semiconductor material is disposed on the sidewall of the silicon pillar. The group III-N semiconductor material h...  
WO/2018/121369A1
Provided are a compound semiconductor transistor and a power amplifier having the transistor. The transistor comprises a collector layer (4), a secondary collector layer (2), and an intermediate layer (3) provided between the collector l...  
WO/2018/123148A1
This silicon carbide epitaxial substrate comprises a silicon carbide substrate and a silicon carbide epitaxial film. The silicon carbide epitaxial film is present on the silicon carbide substrate. The polytype of the silicon carbide subs...  
WO/2018/120076A1
A thin-film transistor, a manufacturing method therefor, and a display device. The thin-film transistor comprises a substrate (101), a semiconductor layer (10), a source electrode (20), a drain electrode (30), a gate electrode (50), insu...  
WO/2018/125212A1
Embodiments herein describe techniques for forming multiple cut regions with orthogonal corners on multiple fins of a semiconductor device based on multiple masks formed by using sacrificial layers with embedded grating lines. A cut regi...  
WO/2018/124489A1
The present invention relates to a split type TFT element structure for a large screen display, and a defective TFT treatment method therefor. In the designing of pixels of a large screen display, the present invention splits a TFT const...  
WO/2018/125108A1
Disclosed herein are methods for manufacturing devices using nanotubes, such as e.g. carbon nanotubes or boron nitride nanotubes, as a guide for selective deposition of materials. For example, in some embodiments, the methods include gro...  
WO/2018/123905A1
Provided are: an x-ray imaging panel that achieves improved producibility; and a production method for the same. An imaging panel 1 generates an image on the basis of scintillation light obtained from x-rays that have passed through a su...  
WO/2018/125258A1
An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region of doped semiconductor material on the substrate adjacent a first side of the semiconductor region...  
WO/2018/125257A1
An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region of doped semiconductor material on the substrate adjacent a first side of the semiconductor region...  
WO/2018/125140A1
Embodiments herein describe techniques for a semiconductor device including a HDB layer protecting the channel layer of a TFT from hydrogen diffusion, e.g., from the gate dielectric layer. Embodiments may include a substrate, and a gate ...  
WO/2018/125179A1
Fin-based transistor structures, such as finFET and nanowire transistor structures, are disclosed. The fins have a morphology including a wave pattern and/or one or more ridges and/or nodules which effectively mitigate fin collapse, by l...  
WO/2018/122659A1
A semiconductor device with a high on-state current is provided. The semiconductor device includes a first conductor over a substrate, a first insulator over the first conductor, a first oxide over the first insulator, a second oxide ove...  
WO/2018/122658A1
A semiconductor device comprises a lookup table comprising a memory, a first circuit and a second circuit. The first circuit receives a first signal and a second signal. The second circuit receives a third signal. When the first circuit ...  
WO/2018/120087A1
An array substrate, comprising a substrate (10), a TFT switch (12) formed on the substrate (10), a protective layer (13) covering the substrate (10) and the TFT switch (12) and a pixel electrode (14) being formed on the protective layer ...  
WO/2018/125154A1
A transistor including a channel; a source and a drain formed; a gate electrode on the channel; and a spacer between the gate electrode and each of the source and the drain, wherein the sidewall spacer includes a concentration of a halog...  

Matches 1 - 50 out of 267,709