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Matches 1 - 50 out of 272,796

Document Document Title
WO/2019/090762A1
Provided is a method for forming gates (1100, 1300), containing forming a first patterned photoresist layer (310) on a substrate (200); forming spacer walls (510d, 510s) on the side wall of said first patterned photoresist layer (310), s...  
WO/2019/092313A1
A photosensitive field-effect transistor configured to provide an electrical response when illuminated by electromagnetic radiation incident on the transistor. The photosensitive field-effect transistor comprises a layer of two-dimension...  
WO/2019/090861A1
A thin film transistor, a method for manufacturing the thin film transistor, and a liquid crystal display device. The thin film transistor (1) comprises a substrate (10), a gate (11), a gate insulating layer (12), an active layer (13), a...  
WO/2019/090868A1
Provided is are manufacturing method of a vertical-structure thin film transistor and the vertical-structure thin film transistor. The manufacturing method comprises the steps of providing a substrate (210) (S110); respectively forming a...  
WO/2019/092541A1
Provided is a semiconductor device having excellent reliability. This device is provided with a first insulating body, a first oxide disposed upon the first insulating body, a second oxide disposed upon the first oxide, a first conductor...  
WO/2019/093479A1
The present technique relates to: a solid-state imaging device which is able to prevent deterioration of the Dark characteristics; and an electronic device. A solid-state imaging device according to the present invention is provided with...  
WO/2019/092871A1
A wide gap semiconductor device, having: a drift layer 12 in which a first-conductivity-type wide gap semiconductor material is used; a plurality of second-conductivity-type well regions 20 formed on the drift layer 12; a polysilicon lay...  
WO/2019/093207A1
Provided are: an electroconductive laminate in which adhesion performance and barrier function of preventing diffusion of copper, in an electrode or a wire, etc., are improved; a method for manufacturing the electroconductive laminate; a...  
WO/2019/092870A1
A wide gap semiconductor device has: a drift layer 12 of a first electrical conductivity type; a well region 20 comprising a second electrical conductivity type, the well region 20 being provided to the drift layer 12; a source region 31...  
WO/2019/093459A1
The present invention addresses the problem of providing a manufacturing method for an electronic device that is provided with an organic thin film functioning as a passivation film against moisture permeation in an electronic device suc...  
WO/2019/090842A1
The present invention discloses a thin film transistor and a display device. The thin film transistor comprises a gate electrode, a source electrode, a drain electrode, an active layer and a heat transmission layer; the heat transmission...  
WO/2019/093458A1
The present invention addresses the problem of providing a desiccant that can be used for passivation of an electronic device such as an organic electroluminescence element against moisture permeation, as well as an organic thin film inc...  
WO/2019/093465A1
According to the present invention, a silicon carbide semiconductor device is produced without lowering the off-state breakdown voltage. A silicon carbide semiconductor device according to the present invention is provided with: a second...  
WO/2019/092511A1
A method of manufacturing semiconductor wafers comprises: selectively growing a nitride buffer layer on a first surface of a patterned substrate, the patterned substrate including at least the first surface and a second surface; and grow...  
WO/2019/092872A1
This wide gap semiconductor device comprises: a drift layer 12 that uses a wide gap semiconductor material of a first conductivity type; a well region 20 comprising a second conductivity type and provided in the drift layer 12; a source ...  
WO/2019/090477A1
An optical waveguide (10), a single-photon source (30) and a manufacturing method for an optical waveguide (10), the optical waveguide (10) comprising: a regulating electrode (103), a passive waveguide (101) and an active waveguide (102)...  
WO/2019/094338A1
A power transistor assembly and method of mitigating short channel effects in a power transistor assembly are provided. The power transistor assembly includes a first layer of semiconductor material formed of a first conductivity type ma...  
WO/2019/094052A1
A semiconductor-on-insulator (SOI) substrate includes a (111) crystalline substrate layer advantageous for seeding an epitaxial III-N material upon which III-N devices may be formed. The SOI substrate may further include another crystall...  
WO/2019/093206A1
Provided are: a semiconductor device that realizes a reduction in contact resistance of a metal contact part of a source/drain of a CMOS, etc.; and a method for manufacturing said semiconductor device. There is realized a semiconductor d...  
WO/2019/089727A1
Devices and methods of the invention use a plurality of Fin structures and or combine a planar portion with Fin structures to compensate for the first derivative of transconductance, gm. In preferred methods and devices, Fins have a plur...  
WO/2019/085011A1
A method for fabricating a low-temperature polycrystalline silicon thin film, comprising: forming a buffer layer (22) on a substrate (21); forming a gate electrode (23) on the buffer layer (22); forming a patterned elevated layer (26) on...  
WO/2019/087328A1
According to the present invention, in an SRAM cell circuit, when seen in a plan view, first gate connection W layers 22c, which are disposed between first gate connection W layers 22a, 22b respectively connected to gate TiN layers 23a, ...  
WO/2019/087937A1
The purpose of the present invention is to provide an excellent integrated circuit by means of a simple process. The present invention pertains to an integrated circuit provided with: at least a memory array for storing data; a rectifica...  
WO/2019/089050A1
Integrated circuit transistor structures are disclosed that reduce band-to-band tunneling between the channel region and the source/drain region of the transistor, without adversely increasing the extrinsic resistance of the device. In a...  
WO/2019/087850A1
The present invention provides an etching method in which the etching rates for a silicon nitride layer and a silicon oxide layer can be controlled so as to be about the same and even a hole having a high aspect ratio can be formed into ...  
WO/2019/085850A1
An insulated gate bipolar transistor (IGBT) power device comprises a bipolar transistor (400), a first MOS transistor (501), a second MOS transistor (502), a body diode (305) and a body region contact diode (304), wherein an anode of the...  
WO/2019/087023A1
Provided is a display device which can achieve the appropriate display without converting an image signal. For high-resolution display, individual items of data are supplied to pixels through a first signal line and a first transistor pr...  
WO/2019/089277A1
A method may include providing a substrate, the substrate comprising a substrate base and a patterning stack, disposed on the substrate base. The substrate may include first linear structures in the patterning stack, the first linear str...  
WO/2019/085835A1
A super field plate structure adapted for a power semiconductor device, and an application thereof. The super field plate structure adapted for a power semiconductor device comprises: an adjustable field plate (131-133) and a regulating ...  
WO/2019/087002A1
Provided is a semiconductor device having excellent electrical characteristics. Also provided is a semiconductor device having stable electrical characteristics. This semiconductor device is configured to include a first insulation layer...  
WO/2019/085009A1
A fabrication method for a low-temperature polycrystalline silicon thin film, comprising: forming a buffer layer on a substrate; forming a first silicon layer on the buffer layer; forming a second silicon layer on the first silicon layer...  
WO/2019/085752A1
A power MOSFET device comprises a source, a drain, a first gate, a second gate, a body diode, and a body contact diode. The source, the drain and the first gate form a first MOSFET structure. The source, the drain and the second gate for...  
WO/2019/089916A1
A method of fabricating a semiconductor device comprises forming, within a single process flow on a silicon on insulator (SOI) wafer, at least one of an n channel, digital VeSFET, a p channel, digital VeSFET, an n channel, analog VeSFET ...  
WO/2019/087424A1
The present invention provides a semiconductor device, a MOSFET 100, provided with: a semiconductor substrate 110 in which a super junction structure is formed in an n-type column region 113 and a p-type column region 115; and a gate ele...  
WO/2019/085577A1
The present invention provides an insulated gate bipolar transistor device and a manufacturing method therefor, and power electronic equipment, so as to improve the overall performance and the applicability of the insulated gate bipolar ...  
WO/2019/087341A1
The present invention provides a semiconductor device, a MOSFET 100, provided with: a semiconductor substrate 110 in which a super junction structure is formed in an n-type column region 113 and a p-type column region 115; and a gate ele...  
WO/2019/087784A1
A method for producing a thin film transistor according to one embodiment of the present invention comprises the formation of an active layer on a substrate. A source region and a drain region are formed such that the regions are able to...  
WO/2019/085851A1
A trench power transistor comprises a source, a drain, a first gate, a second gate, a body diode, and a body region contact diode, wherein the body diode and the body region contact diode are connected in series, the first gate controls ...  
WO/2019/088241A1
This semiconductor device is provided with a semiconductor substrate (10) which comprises a drift layer (11), a base layer (12) that is arranged on the drift layer, and a collector layer (22) of a second conductivity type, which is forme...  
WO/2019/085013A1
Provided is a fabrication method for a low-temperature polycrystalline silicon thin-film, comprising: forming a buffer layer (32) on a substrate (31); forming a silicon layer (33) on the buffer layer (32), and forming an impurity trappin...  
WO/2019/085374A1
Disclosed are a global-exposure photosensitive detector based on a composite dielectric gate MOSFET, an imaging chip formed using the photosensitive detector, and a detection method. The photosensitive detector comprises an array formed ...  
WO/2019/086664A1
The invention relates to a semiconductor element comprising an enhancement-type transistor structure (12) with a layer construction having a base substrate (14), a first semiconductor layer (16) and a second semiconductor layer (18), whi...  
WO/2019/085973A1
An array substrate comprises a substrate, an active layer, and an amorphous silicon shielding layer. The substrate has a first surface and a second surface, which are opposing to each other. The active layer is over the first surface of ...  
WO/2019/087005A1
A method of forming a vertical transport fin field effect transistor is provided. The method includes forming a doped layer on a substrate, and forming a multilayer fin on the doped layer, where the multilayer fin includes a lower trim l...  
WO/2019/089762A1
A non-volatile memory device (VeSFlash) comprises a vertical slit field effect transistor (VeSFET) device comprising a semiconductor portion defining a source end, a drain end, and a slit portion between the source end and the drain end....  
WO/2019/084609A1
Described herein is a structure including: means for generating an electric field; a topological Dirac semimetal layer, wherein the topological Dirac semimetal layer is non- conductively separated from the means for generating the electr...  
WO/2019/083338A1
The present invention provides an oxide thin-film transistor and a method for manufacturing the same. An oxide thin-film transistor according to an embodiment of the present invention comprises: a substrate; a first gate electrode formed...  
WO/2019/083017A1
The first electroconductivity-type impurity concentration in the entire area of a drift layer (2) is configured to be between 1.0 × 1015/cm3 and 5 × 1016/cm3, a Z½ center (2a) is formed within the drift layer (2), and the lifetime of ...  
WO/2019/080480A1
A thin film transistor may include a gate pattern (11), an active layer pattern (12), a gate insulating layer (13) between the gate pattern (11) and the active layer pattern (12); a first conductive pattern (14) including a first pattern...  
WO/2019/082048A1
A semiconductor device includes a source region and a drain region formed in a transistor structure. A channel region is disposed between the source region and the drain region. A cladding layer is formed on the channel region, the cladd...  

Matches 1 - 50 out of 272,796