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Matches 1 - 50 out of 275,732

Document Document Title
WO/2019/178004A3
Semiconductor-on-insulator field effect transistor (FET) integrated circuit (IC) structures and fabrication processes that mitigate or eliminate the problems caused by the secondary parasitic back-channel FET of conventional semiconducto...  
WO/2019/212646A1
Certain aspects of the present disclosure provide a semiconductor device. One example semiconductor device generally includes a substrate, a well region (128) disposed adjacent to the substrate, a first fin (130) disposed above the well ...  
WO/2019/210770A1
Disclosed in the present invention is an enhanced type III-V HEMT device implemented by using a full solid-state battery, in which a second semiconductor layer and a first semiconductor layer are formed on a substrate in sequence, and a ...  
WO/2019/210862A1
Provided in an embodiment of the present invention are a semiconductor device and a manufacturing method therefor, the semiconductor device comprising: a substrate; a semiconductor layer disposed at a side of the substrate, the semicondu...  
WO/2019/211888A1
[Problem] To provide a transistor that exhibits excellent properties. [Solution] Provided is a method for forming a gate insulation film for a bottom gate-type transistor, the method comprising: forming a resist layer on a gate electrode...  
WO/2019/213663A1
Advanced magnetic tunneling junctions (MTJs) that dramatically reduce power consumption (switching energy, ESw) while maintaining a reasonably high tunneling magnetoresistance (on/off ratio, TMR) and strong thermal stability at room temp...  
WO/2019/211697A1
Provided is a semiconductor device in which it is possible to change the storage region for each hierarchy level of a storage device. Specifically provided is a semiconductor device which has a control circuit and a storage device provid...  
WO/2019/211989A1
The present technology pertains to an electrostatic protection element and an electronic apparatus in which the protection performance against static electricity can be improved. The electrostatic protection element is provided with: a f...  
WO/2019/210370A1
The present disclosure is directed to a methodology for embedding a deterministic number of dopant atoms in a surface portion of a group IV semiconductor lattice. The methodology comprises the steps of: forming one or more lithographic s...  
WO/2019/211299A1
A technique comprising: providing on an outer side of a support film of a liquid crystal cell one or more first components having an oxygen transmission rate (OTR) at least 100,000 times lower than said support film of the liquid crystal...  
WO/2019/213420A1
A semiconductor device comprises a complementary metal oxide semiconductor (CMOS) device and a heterojunction bipolar transistor (HBT) integrated on a single die. The CMOS device may comprise silicon. The HBT may comprise III-V materials...  
WO/2019/208206A1
Provided is a method of manufacturing an organic semiconductor device that includes: forming an organic semiconductor film on a first substrate; forming, on a second substrate that is different from the first substrate, a conductor film ...  
WO/2019/205540A1
An array substrate and manufacturing method and performance improvement method therefor, a display panel, and a display device. The array substrate comprises: a substrate base (10); a shielding layer (20) provided on one surface of the s...  
WO/2019/204977A1
Provided in the present invention is an array substrate, the array substrate comprising: a substrate, an active layer, an insulation layer, and a protective layer, the active layer, the insulation layer, and the protective layer all bein...  
WO/2019/208294A1
The present invention is provided with: a low resistance material layer (102) formed on a substrate (101); a metal layer (103) formed on the low resistance material layer (102); a bipolar transistor (104) formed on the substrate (101); a...  
WO/2019/207411A1
Provided is a semiconductor device having a large on-state current and excellent reliability. The semiconductor device includes first to fifth insulators, first to third oxides, and first to fourth conductors. The fifth insulator has an ...  
WO/2019/209039A1
The present invention relates to polycyclic aromatic hydrocarbon-based compounds, for a molecular electronic device, enabling molecular rectification, and molecular electronic devices comprising a molecular layer formed by means of the c...  
WO/2019/207440A1
Provided is a display device that can increase image quality. A display device has a plurality of pixel blocks in a display region. Each pixel block has a first circuit and a plurality of second circuits. The first circuit has a function...  
WO/2019/207410A1
Provided is a semiconductor device capable of miniaturization or high integration. The semiconductor device includes: a first layer; and a second layer on the first layer. The first layer and the second layer each has a transistor. The t...  
WO/2019/207404A1
Provided is a semiconductor device which, from the result of a calculation by an artificial neural network, updates the weighting factors that were used for the calculation. This semiconductor device has first to third circuits and first...  
WO/2019/205539A1
Provided is an insulated gate bipolar transistor. The insulated gate bipolar transistor comprises: a drift region; a P well region provided at one side of the drift region; an N+ emitter provided at the side of the P well region distant ...  
WO/2019/207354A1
An electronic product comprising a component having a first electrode comprising a first surface (103) and a pillar (104) extending from the first surface in a first direction, the pillar comprising three protrusions (106, 107, 108), the...  
WO/2019/209870A1
A semiconductor device comprises a heterojunction bipolar transistor (HBT). The HBT (104) comprises an emitter, a collector, and a base between the emitter and the collector. A width of the emitter is smaller than 100 nanometers, which i...  
WO/2019/208241A1
The purpose of the present invention is to provide a technique with which an electrode that has no level difference with the surrounding area can be formed by a simpler manufacturing process. A method of forming an electrode for an organ...  
WO/2019/195192A3
An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (24) (e.g., a substrate), an n- epi layer (26), a p-well (14), trenched insulated gate regions (12) formed in the p-well, and n+ regi...  
WO/2019/208295A1
An element section comprising a collector layer (105), a base layer (106), an emitter layer (107), an emitter cap layer (108), an emitter electrode (109), and a base electrode (110) is formed on a heat-dissipating substrate (101). Furthe...  
WO/2019/207429A1
Provided is a semiconductor device having excellent reliability. Specifically provided is a semiconductor device having a first insulator, a second insulator, and a transistor, wherein the transistor has an oxide in a channel formation r...  
WO/2019/205340A1
Provided are a low-temperature polysilicon thin film transistor and a manufacturing method thereof. A first contact hole and a second contact hole are provided at a thin film transistor. The first contact hole and the second contact hole...  
WO/2019/208578A1
A recessed portion (14, 23) is formed in at least one of a plurality of silicon substrates (11, 13, 21). Further, in at least one of the plurality of silicon substrates, a silicon dioxide film (12, 22) in which a groove portion (17, 28) ...  
WO/2019/207418A1
Provided is a semiconductor device which suppresses variations in characteristics, the deterioration of elements, and shape anomalies. The device has a first region that is provided with a plurality of elements, and a second region that ...  
WO/2019/205537A1
A dual-gate MOSFET structure, comprising: a channel region having a gradually changing thickness. A source region is provided at the side of the channel region having a small thickness, and a drain region is provided at the side of the c...  
WO/2019/210156A1
A resistive switching device that comprises an ion source and a resistive switching oxide separated by an electrolyte layer. The ion source can comprise cations that move from the ion source to the resistive switching oxide, and from the...  
WO/2019/209440A1
A transistor comprises semiconductor material that is generally L-shaped or generally mirror L-shaped in at least one straight-line vertical cross-section thereby having an elevationally-extending stem and a base extending horizontally f...  
WO/2019/208755A1
A first electrode film (91) is electrically connected to a source region (4) of a semiconductor substrate (50), while being provided on a main surface (S2) of the semiconductor substrate (50). A second electrode film (92) is electrically...  
WO/2019/206215A1
Provided in the embodiments of the present invention are a semiconductor device, a semiconductor chip, and a method for manufacturing the semiconductor device, the semiconductor device comprising a substrate and a semiconductor layer man...  
WO/2019/209330A1
Devices and methods are provided. In one aspect, a device for driving a memristor array includes a substrate including a well having a bottom layer, a first wall and a second wall. The substrate is formed of a strained layer of a first s...  
WO/2019/208034A1
[Problem] To provide a switching transistor and a semiconductor module which achieve further reduction in distortion in a signal. [Solution] A switching transistor provided with: a channel layer formed by a compound semiconductor, and ha...  
WO/2019/205837A1
Provided in the present invention is a superjunction Insulated Gate Bipolar Transistor (IGBT) device, wherein a carrier storage layer of a first conduction type is provided between a voltage-standing layer and a base area, and a Metal-In...  
WO/2019/191465A9
A vertical gallium oxide (Ga2O3) device havinga substrate, an n-type Ga2O3 drift layer on the substrate, an, n-type semiconducting channel extending from the n-type Ga2O3 drift layer, the channel being one of fin-shaped or nanowire shape...  
WO/2019/202440A1
Provided is a novel semiconductor device. The semiconductor device comprises a plurality of cell arrays and a plurality of peripheral circuits, wherein: each cell array has a plurality of memory cells; each peripheral circuit has a first...  
WO/2019/204829A1
The present invention provides semiconductor devices with super junction drift regions that are capable of blocking voltage. A super junction drift region is an epitaxial semiconductor layer located between a top electrode and a bottom e...  
WO/2019/202350A1
A semiconductor device comprising: a substrate (1); a first conductivity-type drift region (4) disposed on a major surface of the substrate (1); a second conductivity-type first well region (21) which extends from a second major surface ...  
WO/2019/201002A1
A gallium nitride transistor with a gap-type composite passivation medium and a manufacturing method therefor; using composite passivation medium technology, a composite passivation medium layer at least comprises a stacked lower medium ...  
WO/2019/203966A1
Certain aspects of the present disclosure provide a semiconductor device. One example semiconductor device generally includes a semiconductor region, an insulative layer, a first terminal, and a first non-insulative region coupled to the...  
WO/2019/202774A1
This ESD protective element (10) comprises: a semiconductor substrate (20); a wiring layer (30); and an inductor conductor (40). A Zener diode is formed on the semiconductor substrate (20). The inductor conductor (40) is formed on the wi...  
WO/2019/202923A1
A laser processing device (1) according to one embodiment of the present invention has a laser light irradiation unit (20), and a conveying stage (40) on which a substrate (31) can be caused to float and conveyed. The conveying stage (40...  
WO/2019/204795A1
A semiconductor structure for a DRAM is described having multiple layers of arrays of memory cells. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that ...  
WO/2019/204120A1
The present disclosure relates to a method for forming a p-metal work function nitride film having a desired p-work function on a substrate, including: adjusting one or more of a temperature of a substrate, a duration of one or more temp...  
WO/2019/202431A1
Provided is a semiconductor device which has low power consumption and enables stable operation. The semiconductor device comprises a logic circuit having a transistor circuit configuration having an oxide semiconductor in a channel form...  
WO/2019/200561A1
Embodiments of a channel hole plug structure of 3D memory devices and fabricating methods thereof are disclosed. The memory device includes an alternating layer stack disposed on a substrate, an insulating layer disposed on the alternati...  

Matches 1 - 50 out of 275,732