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Matches 1 - 50 out of 6,246

Document Document Title
WO/2019/188457A1
[Problem] To provide a semiconductor device and multiply-accumulate operation device with which higher-density integration can be achieved by further reducing the installation area for each synapse. [Solution] Provided is a semiconductor...  
WO/2019/187032A1
A variable resistance element (1) comprises: a variable resistance layer (3) which can store and emit at least one type of ion, and the resistance of which changes in accordance with the amount of the at least one type of ion; an ion sto...  
WO/2019/186045A1
Memory device provided with a support and several superimposed levels of resistive memory cells (91, 92, 93, 94, 95, 96) formed on said support, each level (N1; N2;...;) comprising one or more rows (x; x+1) of one or more resistive memor...  
WO/2019/183828A1
A self-rectifying resistive memory, comprising: a lower electrode (101); a resistive material layer (201) that is formed on the lower electrode (101) and used for serving as a storage medium; a barrier layer (301) that is formed on the r...  
WO/2019/190392A1
Various embodiments may provide a memory cell. The memory cell may include an active electrode including an active electrode material. The memory cell may also include a first noble electrode contact with the active electrode, the first ...  
WO/2019/186117A1
The disclosed method of fabricating a correlated electron material (CEM) switching device comprises depositing at least one transition metal containing layer, preferably Ni, over a conductive substrate, depositing at least one carbon con...  
WO/2019/186120A1
A disclosed method of fabricating correlated electron material (CEM) devices, which may be used to perform a switching function, comprises: depositing one or more layers of a CEM film, for example, nickel oxide comprising from about 0.1 ...  
WO/2019/190502A1
A resistive random-access memory device comprises a transistor and a filmstack. The memory stack comprises a bottom electrode coupled to the transistor. A primary dielectric is formed over the bottom electrode. An oxygen exchange layer i...  
WO/2019/181116A1
The titanium suboxide according to the present invention stores or dissipates heat through irradiation with light or an action of pressure or heat, and contains Ti3O5, which has a crystal structure that undergoes phase transition between...  
WO/2019/180404A1
Disclosed is a method for the fabrication of a correlated electron material (CEM) device comprising: forming a layer of a conductive substrate (202) on a substrate (210); forming a layer of a correlated electron material (204) on the lay...  
WO/2019/182591A1
Embedded non-volatile memory structures having selector elements with negative differential resistance (NDR) elements are described. In an example, a memory device includes a word line. A selector element is above the word line. The sele...  
WO/2019/180405A1
Disclosed is a method for the fabrication of a correlated electron material (CEM) switching device, the method comprising: forming a layer of a conductive substrate (202); forming a layer of a correlated electron material (204) on the co...  
WO/2019/181273A1
A cross point element according to an embodiment of the present disclosure is provided with: a first electrode; a second electrode that is disposed oppositely to the first electrode; and a memory element, a selection element, and a resis...  
WO/2019/175671A1
A memory device is disclosed. The memory device includes a bottom contact. The memory device also includes a memory layer connected to the bottom contact, where the memory layer has a variable resistance. The memory device also includes ...  
WO/2019/175672A1
A memory device is disclosed. The memory device includes a bottom contact and a memory layer connected to the bottom contact. The memory layer has a variable resistance. The memory device also includes a top electrode on the memory layer...  
WO/2019/177632A1
One embodiment provides a method of making a memory device. The method includes forming a via in a bit line, an interlayer and a dielectric region. The bit line is formed on the interlayer. The interlayer is formed partially on the diele...  
WO/2019/175673A1
A memory device including a template layer is disclosed. The memory device also includes a memory layer connected to the template layer, where the memory layer has a variable resistance, and where the crystalline structure of the memory ...  
WO/2019/174032A1
Provided in embodiments of the present application are a memristor fabrication method, a memristor, and a resistive random access memory (RRAM), the memristor fabrication method comprising: depositing a lower electrode of a memristor; pr...  
WO/2019/176833A1
In order to suppress moisture absorption in a variable resistance layer included in a variable resistance element and to reduce variations in set voltage, this semiconductor device is provided with: a first electrode; a first insulation ...  
WO/2019/172879A1
A stacked device structure includes a first device structure including a first body that includes a semiconductor material, and a plurality of terminals coupled with the first body. The stacked device structure further includes an insula...  
WO/2019/167538A1
A switching element according to one embodiment of the present disclosure is provided with: a first electrode; a second electrode which is arranged so as to face the first electrode; and a switching layer which is arranged between the fi...  
WO/2019/168123A1
This nanogap electrode comprises: a first electrode which has a first electrode layer and a first metal particle that is arranged on one end of the first electrode layer; and a second electrode which has a second electrode layer and a se...  
WO/2019/168830A1
Resistive change element cells sharing a selection device and resistive change element arrays including a plurality of resistive change element cells and a plurality of selection devices arranged in a group of at least two resistive chan...  
WO/2019/161815A1
A random access memory device (400) comprises inert-inert electrode cell (210) and inert-active electrode cell (110). The inert-inert electrode cell (210) and inert-active electrode cell (110) are connected in series in a serial connecti...  
WO/2019/146268A1
A storage element according to an embodiment of the present disclosure is provided with: a first electrode; a second electrode disposed opposite the first electrode; and a storage layer which is disposed between the first electrode and t...  
WO/2019/146534A1
In order to provide a logic integrated circuit having a reduced chip area, the present invention provides a logic integrated circuit comprising a switch cell array that has: a plurality of first wirings extending in a first direction; a ...  
WO/2019/132997A1
Described herein are systems, methods, and apparatuses for using negative differential resistance (NDR) materials in circuits to store memory states for memory devices. In an embodiment, such NDR materials can have a voltage dependent vo...  
WO/2019/132888A1
Provided herein are structures, including memory structures, and methods of forming structures. The memory structures may include selectors and memory elements. The memory elements may include a material that can change resistance. The s...  
WO/2019/132994A1
In an embodiment, described herein are systems, methods, and apparatuses directed towards segmentation of a large cross-point memory a memory array (or tile) into two or more memory arrays (sub-tiles) of smaller size for use as an embedd...  
WO/2019/132995A1
Disclosed herein are systems, methods, and apparatuses that are directed to a selector for use in connection with memory devices. In an embodiment, the selector can comprise a device that has current-voltage characteristics that are symm...  
WO/2019/133117A1
A semiconductor device assembly is provided. The assembly comprises a package substrate, a first stack of semiconductor dies having a first set of planform dimensions disposed over a first location on the substrate, a second stack of sem...  
WO/2019/125392A1
Integrated circuit structures are provided that may include a first insulating-to-metallic transition material, a second insulating-to-metallic transition material, and a third layer. The third layer may have an electron affinity that is...  
WO/2019/125994A1
One aspect of the invention relates to a multi-terminal memtransistor. The memtransistor includes a substrate having a first surface and an opposite, second surface, a polycrystalline monolayer film formed of an atomically thin material ...  
WO/2019/121796A1
An aspect of the invention is a memory according to the preceding claim (CO) comprising a plurality of first electrodes (EP), referred to as flat electrodes (EP), each flat electrode (EP) of the plurality of flat electrodes (EP) defining...  
WO/2019/118931A1
Three-dimensional vertical memory array cell structures and processes. In an exemplary embodiment, a 3D vertical memory array structure is formed by performing operations that include forming an array stack having alternating metal layer...  
WO/2019/097341A1
A method is presented for forming a semiconductor device. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form a plurality of trenches for receiving a first conducting ma...  
WO/2019/087050A1
A liner is deposited conformally to a pore within a first dielectric material of a semiconductor device. The pore extends through the first dielectric material to a top surface of a first metal electrode. The liner is etched such that th...  
WO/2019/078367A1
Provided is a memristor which can be manufactured at low temperature and does not include metals that could potentially dry up as a resource. The memristor 1 is provided with: a first electrode 2; a second electrode 3; and an oxide memri...  
WO/2019/066829A1
An integrated circuit structure includes a stack of alternating first conductive layers and insulator layers. A plurality of etch pits are through the first conductive layers. A plurality of selectors are in the etch pits adjacent to the...  
WO/2019/062198A1
A gate tube device and a preparation method therefor, applied to the technical field of gate tube devices. The gate tube device comprises a first metal electrode layer (1, 9), a second metal electrode layer (4, 12), and a switch layer. T...  
WO/2019/008328A3
The present techniques relate to a method for the manufacture of a CEM device comprising forming a thin film of a correlated electron material having a predetermined electrical impedance when the CEM device in its relatively conductive (...  
WO/2019/066894A1
Embedded non-volatile memory structures having an independently sized selector element and memory element are described. In an example, a memory device includes a metal layer. A selector element is above the metal layer. A memory element...  
WO/2019/066898A1
An integrated circuit comprising a self-aligned embedded phase change memory cell is described. In an example, the integrated circuit includes a bottom electrode. A conductive line is above the bottom electrode along a first direction ab...  
WO/2019/066826A1
Embedded non-volatile memory structures having asymmetric selector elements are described. In an example, a memory device includes a word line. An asymmetric selector element is above the word line. The asymmetric selector element includ...  
WO/2019/068094A1
A self-aligned memory device includes a conductive bottom plug disposed within an insulating layer and having a coplanar top surface, a self-aligned planar bottom electrode disposed upon the coplanar top surface and having a thickness wi...  
WO/2019/066851A1
An apparatus, includes an interconnect, including a conductive material, above a substrate and a resistive random access memory (RRAM) device coupled to the interconnect. The RRAM device includes an electrode structure above the intercon...  
WO/2019/066996A1
A memory device includes a first electrode, a non-volatile memory element having a first terminal and a second terminal, where the first terminal is coupled to the first electrode. The memory device further includes a selector having a f...  
WO/2019/063926A1
Proposed is a method of producing a recurrent neural network computer, which method comprises consecutive steps of providing a substrate comprising a first electrode; structuring the first electrode by etching using a first mask made of ...  
WO/2019/066828A1
Embedded non-volatile memory structures having double selector elements are described. In an example, a memory device includes a word line. A double selector element is above the word line. The double selector element includes a first se...  
WO/2019/066769A1
Disclosed herein are selector devices, and related devices and techniques. In some embodiments, a selector device may include a first electrode, a second electrode, a selector material between the first electrode and the second electrode...  

Matches 1 - 50 out of 6,246