| Document |
Document Title |
|
WO/2018/009156A1 |
Embodiments of the present invention include RRAM devices and their methods of fabrication. In an embodiment, a resistive random access memory (RRAM) cell includes a conductive interconnect disposed in a dielectric layer above a substrat...
|
|
WO/2018/009155A1 |
Resistive random access memory (RRAM) devices having a bottom oxygen exchange layer and their methods of fabrication are described. In an example, an RRAM cell includes a conductive interconnect disposed in a first dielectric layer above...
|
|
WO/2018/006131A1 |
A memristor device is provided, comprising a first electrode; a second electrode; a cathode metal layer disposed on a surface of the first electrode; and an active region disposed between and in electrical contact with the second electro...
|
|
WO/2018/009157A1 |
A memory including a top electrode and a bottom electrode; and an oxide layer including a plurality of intimately mixed oxides throughout the oxide layer. A memory including a top electrode and a bottom electrode; an oxygen exchange laye...
|
|
WO/2018/004697A1 |
Approaches for integrating a dual layer stack for a resistive random access memory cell and the resulting structures, are described. In an example, a resistive random access memory (RRAM) cell includes a conductive interconnect disposed ...
|
|
WO/2018/004670A1 |
Approaches for integrating resistive random access memory (RRAM) memory arrays into a logic processor, and the resulting structures, are described. In an example, a logic processor includes a logic region including a first portion of an ...
|
|
WO/2018/004650A1 |
Techniques are disclosed for forming a one transistor, one resistor (1T-1R) resistive random-access memory (RRAM) cell including a group III-N access transistor, such as a gallium nitride (GaN) access transistor. Use of a group III-N acc...
|
|
WO/2018/004587A1 |
Approaches for fabricating RRAM stacks with two-dimensional (2D) barrier layers, and the resulting structures and devices, are described. In an example, a resistive random access memory (RRAM) device includes a conductive interconnect di...
|
|
WO/2018/004562A1 |
Approaches for fabricating self-aligned pedestals for resistive random access memory (RRAM) elements and devices, and the resulting structures, are described. In an example, a resistive random access memory (RRAM) device includes a condu...
|
|
WO/2018/003864A1 |
Provided are: a semiconductor device in which a non-volatile switch on which a rectifier is mounted and a non-volatile element on which a rectifier is not mounted are formed in the same wiring; and a method for producing a semiconductor ...
|
|
WO/2018/004147A1 |
The present invention relates to a method for manufacturing a phase change memory including an electrode unit, which causes a phase change in a phase change material and is disposed at the lower side of the phase change material, and the...
|
|
WO/2018/004625A1 |
Approaches for fabricating conductive bridge random access memory (CBRAM) devices with engineered sidewalls for filament localization, and the resulting structures and devices, are described. In an example, a conductive bridge random acc...
|
|
WO/2018/004588A1 |
Approaches for fabricating back end of line (BEOL)-compatible resistive random access memory (RRAM) elements and devices, and the resulting structures, are described. In an example, a resistive random access memory (RRAM) device includes...
|
|
WO/2018/004574A1 |
Approaches for fabricating RRAM stacks with an amorphous bottom ballast layer, and the resulting structures and devices, are described. In an example, a resistive random access memory (RRAM) device includes a conductive interconnect disp...
|
|
WO/2018/004671A1 |
Approaches for fabricating RRAM stacks with a bottom ballast layer, and the resulting structures and devices, are described. In an example, a resistive random access memory (RRAM) device includes a conductive interconnect disposed in an ...
|
|
WO/2017/222525A1 |
Approaches for fabricating RRAM stacks with two intrinsic ballast layers, and the resulting structures and devices, are described. In an example, a resistive random access memory (RRAM) device includes a conductive interconnect disposed ...
|
|
WO/2017/218057A1 |
A three terminal ReRAM device, which combines a Schottky barrier transistor and a Schottky barrier ReRAM into a single device is provided. The device includes a source region (106), a drain region (108), a gate electrode (114), and a ReR...
|
|
WO/2017/217119A1 |
[Problem] To provide a circuit element, a storage device, an electronic instrument, a method for writing information to the circuit element, and a method for reading information from the circuit element. [Solution] A circuit element prov...
|
|
WO/2017/190719A1 |
The invention relates to a method for producing layers of ReRAM memories and the use of an implantation device. According to the invention, in order to produce ReRAM memories, TMO layers are applied to an electrode in a desired sequence,...
|
|
WO/2017/185326A1 |
Provided are a self-gating resistive storage device and a method for fabrication thereof; said self-gating resistive storage device comprises: lower electrodes (301, 302, 303); insulating dielectric layers (201, 202, 203, 204) arranged p...
|
|
WO/2017/189072A1 |
A volatile resistive memory device includes a resistive memory element including a barrier material portion and a charge-modulated resistive memory material portion. The barrier material portion includes a material selected from germaniu...
|
|
WO/2017/181417A1 |
Disclosed are a manufacturing method of a Cu-based resistive random access memory, and a memory. The manufacturing method comprises: forming a copper wire in a groove by means of a damascene process for forming a copper interconnection, ...
|
|
WO/2017/182826A1 |
The present invention relates to novel memristive devices, uses thereof, and processes for their preparation. In a first aspect the invention provides a quantum memristor, comprising a first quantum dot (QD1 ) which is capacitively coupl...
|
|
WO/2017/181418A1 |
Provided are a manufacturing method of a Cu-based resistive random access memory, and a memory. The manufacturing method comprises: chemically reacting a pattern of a lower copper electrode (10) to form a compound buffer layer (40), the ...
|
|
WO/2017/171820A1 |
An embodiment includes an apparatus comprising: first and second electrodes; first and second insulation layers between the first and second electrodes; and a middle layer between the first and second insulation layers; wherein (a) the m...
|
|
WO/2017/172071A1 |
A method is provided that includes forming a vertical bit line disposed in a first direction above a substrate, forming a multi-layer word line disposed in a second direction above the substrate, the second direction perpendicular to the...
|
|
WO/2017/171819A1 |
An embodiment includes a memory comprising: a top electrode and a bottom electrode; an oxygen exchange layer (OEL) between the top and bottom electrodes; and an oxide layer between the OEL and the bottom electrode; wherein the oxide laye...
|
|
WO/2017/170149A1 |
To stabilize programming operation and to reduce leakage current. A variable resistance element according to the present invention is provided with: an interlayer insulating film; a first electrode that is formed within the interlayer in...
|
|
WO/2017/171780A1 |
One embodiment provides an apparatus. The apparatus includes a first memory cell and a second memory cell. The first memory cell includes a first resistive element. The first resistive element includes a first top electrode, a common bot...
|
|
WO/2017/171821A1 |
An embodiment includes a programmable metallization cell (PMC) memory comprising: a top electrode and a bottom electrode; a metal layer between the top and bottom electrodes; and a solid electrolyte (SE) layer between the metal layer and...
|
|
WO/2017/164487A1 |
A memory device according to the present invention comprises: a substrate; a coupling layer having electrical conductivity and located on the substrate; a meta-atomic layer located above or below the coupling layer; a memory layer locate...
|
|
WO/2017/164689A2 |
The present invention relates to a technology wherein a memristor element that joins a memory and a resistor is laminated on a predetermined metal compound layer so as to manufacture the same as a characteristic element capable of contro...
|
|
WO/2017/160233A1 |
Embodiments provide a memory device, including a plurality of insulating layers and a plurality of lateral layer arrangements. The lateral layer arrangements and the insulating layers are arranged alternately on each other such that each...
|
|
WO/2017/157074A1 |
Disclosed are a selector for use in a bipolar resistive memory and a manufacturing method for the selector. The method comprises: providing a substrate (20) (S101); forming a lower substrate (21) on the substrate (20) (S102); forming a f...
|
|
WO/2017/155668A1 |
A method is provided that includes forming a vertical bit line (LBL11) disposed in a first direction above a substrate (502), forming a word line (WL10) disposed in a second direction above the substrate, the second direction perpendicul...
|
|
WO/2017/149285A1 |
Subject matter disclosed herein relates to correlated electron switch devices, and relates more particularly to one or more barrier layers (615, 625) having various characteristics formed under and/or over and/or around correlated electr...
|
|
WO/2017/151296A1 |
A memory device and method comprising a metal oxide material disposed between and in electrical contact with first and second conductive electrodes, and a voltage source configured to apply a plurality of voltage pulses spaced apart in t...
|
|
WO/2017/150617A1 |
Provided is a thin film in which the semiconductor characteristics of an In-Ga-Zn-O-based oxide are reversible, and a method of manufacturing the same. A semiconductor/insulator reversible-change thin film comprising an In-Ga-Zn-O-based ...
|
|
WO/2017/146927A1 |
The present invention provides a method for creating patterns, with features down to the nanometer scale, in phase change materials using a heated probe. The heated probe contacts the phase change material thereby inducing a local phase ...
|
|
WO/2017/141042A1 |
A method for forming a thin film (302) comprising a metal, metal compound, or metal oxide on a substrate, which method comprises forming one or more thin film layers (303, 304, 305) of a metal or metal oxide by a deposition process emplo...
|
|
WO/2017/140647A1 |
The disclosed composition, particularly suitable for resistance switching memories based on metal ion transport, comprises a matrix material of a metal oxide/sulphide/selenide of at least two metals M1 and M2, and a metal M3 which is mob...
|
|
WO/2017/142790A1 |
Systems and methods for improving performance of a non-volatile memory that utilizes a Vacancy Modulated Conductive Oxide (VMCO) structure are described. The VMCO structure may include a layer of amorphous silicon (e.g., a Si barrier lay...
|
|
WO/2017/140646A1 |
The disclosed resistive switching memory cell comprises a switchable solid electrolyte matrix comprising a metal oxide/sulphide/selenide comprising at least two metals M1 and M2, and a metal M3 which is mobile in the matrix, wherein - th...
|
|
WO/2017/141031A1 |
The present techniques generally relate to the fabrication of correlated electron materials used, for example, to perform a switching function. In embodiments, precursors, in a gaseous form, may be utilized in a chamber to build a film o...
|
|
WO/2017/141043A1 |
The present techniques generally relate to fabrication of correlated electron materials used, for example, to perform a switching function. In embodiments, precursors, in a gaseous form, may be utilized in a chamber to build a film of co...
|
|
WO/2017/138886A1 |
Various embodiments may provide a device for controlling an electromagnetic wave according to various embodiments. The device may include a medium. The device may further include an array of elements in contact with the medium and may be...
|
|
WO/2017/131897A1 |
A vacancy-modulated conductive oxide (VMCO) resistive random access memory (ReRAM) device includes at least one interfacial layer between a semiconductor portion and a titanium oxide portion of a resistive memory element. The at least on...
|
|
WO/2017/131642A1 |
A resistive memory cell is integrated with a selector. The device structure includes a stack of a first electrode, one of a selector or a resistive switching layer, and a second electrode formed in a device layer of a multilayer structur...
|
|
WO/2017/129970A1 |
The present techniques generally relate to fabrication of correlated electron materials used, for example, to perform a switching function. In embodiments, precursors, in a gaseous form, may be utilized in a chamber to build a film of co...
|
|
WO/2017/129972A1 |
The present techniques generally relate to fabrication of correlated electron materials used, for example, to perform a switching function. In embodiments, a correlated electron material may comprise a dominant ligand and a substitutiona...
|
