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Matches 501 - 550 out of 6,078

Document Document Title
WO/2012/111205A1
According to one embodiment, a variable resistance layer 2 includes a semiconductor element. A resistance change is reversibly possible in the variable resistance layer according to supply and collection of a metal element of a second el...  
WO/2012/108151A1
A nonvolatile latch circuit (100) according to the present invention is formed by connecting both the outputs of an inverter circuit (20) and an inverter circuit (21) cross-coupled to each other through a series circuit formed by sequent...  
WO/2012/108185A1
A non-volatile storage element drive method comprises: an initialization step of applying an initialization voltage pulse to a series circuit wherein a load resistor (5) having a first resistance value is connected in series to a resista...  
WO/2012/105139A1
The present invention has an ion-conducting layer (11), and a first electrode (21) and a second electrode (22) respectively formed on front and reverse surfaces of the ion-conducting layer (11). The first electrode (21) is formed from a ...  
WO/2012/105225A1
Provided is a method for manufacturing a variable resistance nonvolatile storage device such that a metal electrode that forms a lower electrode on the bottom of a memory cell hole can be formed reliably without having electrical conduct...  
WO/2012/105232A1
Provided is a data read method that, in a variable-resistance non-volatile recording element, is difficult to be affected by the phenomenon of resistance value fluctuations during data reading. The data read method of a variable-resistan...  
WO/2012/105214A1
Provided is a method for manufacturing a variable resistance element that can improve the endurance characteristics of nonvolatile storage. This method for manufacturing a variable resistance element (112) comprises: a step (A) for formi...  
WO/2012/102025A1
A nonvolatile memory device (100) comprises the following: a nonvolatile memory element (101) having a first electrode, a second electrode, and a resistance change layer that is disposed between the first electrode and the second electro...  
WO/2012/100501A1
A resistance conversion type random memory unit and a memory device are provided. The memory unit is constitutive of an upper electrode (2), a resistance conversion function layer, a middle electrode (4), a dissymmetrical tunnel barrier ...  
WO/2012/100562A1
Provided are a resistive random access unit and a resistive random access memory. The resistive random access unit is formed by a resistive random access memory and a two-state resistor connected in series. Because the two-state resistor...  
WO/2012/100502A1
A nonvolatile memory unit and a memory device are provided. The memory unit includes an upper electrode (1), a dissymmetrical tunnel barrier structure and a lower electrode (5) in turn from top to bottom, wherein the dissymmetrical tunne...  
WO/2012/097565A1
The present invention provides a phase change memory cell and a manufacture method thereof The phase change memory cell includes a semiconductor substrateļ¼Œa first electrode layer, a phase change material layer, a second electrode layer...  
WO/2012/098879A1
A resistance change element has a first electrode (107), a second electrode (105), and a resistance change layer (106) provided interposed between the first and second electrodes (107, 105) so as to be in contact with the first and secon...  
WO/2012/090404A1
A nonvolatile storage element of the present invention is provided with a variable resistance element (104a), which has: a first electrode layer (103); a second electrode layer (105); and a variable resistance layer (104), which is dispo...  
WO/2012/087183A2
In the method, a pre-selected working area of a graphene film with a linear dimension of 2,000 nm, which working area is divided into sections having a dimension of 50-100 nm, is subjected to the effect of a pulsed alternating magnetic f...  
WO/2012/083672A1
A three-dimension (3D) semiconductor memory device based on 1T1R memory structure with a vertical surrounding gate transistor (SGT) and a manufacturing method thereof are provided. The ratio of on/off current can be effectively controlle...  
WO/2012/086169A1
[Problem] To provide a method of manufacturing a dielectric device and an ashing method, which are capable of minimizing resist residue. [Solution] In the aforementioned ashing method, a base material, having its surface etched with a pl...  
WO/2012/087183A3
In the method, a pre-selected working area of a graphene film with a linear dimension of 2,000 nm, which working area is divided into sections having a dimension of 50-100 nm, is subjected to the effect of a pulsed alternating magnetic f...  
WO/2012/079296A1
A multilayer phase change material with low thermal conductivity is provided. The periodic multilayer film structure is formed by alternately stacking two kinds of single layer film phase change materials which are different from at leas...  
WO/2012/080967A1
The invention relates to a memristive element (M) formed by: a first electrode (10); a second electrode (30); and an active region (20) making direct electrical contact with said first and second electrodes, characterized in that said ac...  
WO/2012/081248A1
A nonvolatile memory device comprises: a first electrode wiring (151) formed in a strip shape; a third interlayer insulating layer (16); a variable resistance layer which is a laminated structure that is formed on the region covering the...  
WO/2012/077518A1
[Problem] To provide a perovskite manganese oxide thin film that: (1) is capable of primary phase transition; and (2) is ordered at the A site. [Solution] The present invention provides a perovskite manganese oxide thin film (2) that inc...  
WO/2012/077174A1
When, in the present invention, a thin channel semiconductor layer formed on the side wall of a laminated film in which an insulating film and gate electrode are alternately laminated is removed on that laminated film, increases in conta...  
WO/2012/077517A1
[Problem] To increase the transition temperature of a perovskite manganese oxide thin film to above that of the bulk thereof. [Solution] An embodiment of the present invention provides a perovskite manganese oxide thin film (2) which is ...  
WO/2012/073471A1
The present invention provides a nonvolatile memory element comprising a variable resistance layer having a layered structure, wherein the variable resistance layer has a high resistance change ratio, and the present invention also provi...  
WO/2012/071892A1
A resistance conversion memory and a method for manufacturing the same are provided. The resistance conversion memory includes a lower electrode (1), a resistance conversion function layer(2) and an upper electrode(3) in turn from bottom...  
WO/2012/074131A1
A semiconductor device capable of being produced with few steps and a production method therefor are provided. The semiconductor device comprises: a variable resistance element; a first interlayer insulating film; a second interlayer ins...  
WO/2012/073503A1
A non-volatile storage element (10) according to the present invention is provided with: a first metal wire (103); a plug (107) which is formed on the first metal wire (103) and is connected to the first metal wire (103); a layered body ...  
WO/2012/070238A1
This nonvolatile memory element is provided with a resistance change layer (116) which is interposed between a bottom electrode (105) and an upper electrode (107) and in which the resistance value reversibly varies on the basis of electr...  
WO/2012/070096A1
An upright chain memory comprising: a two-level select transistor comprising first select transistors, which are upright transistors disposed in a matrix arrangement, and second select transistors, which are upright transistor formed res...  
WO/2012/070551A1
Provided are a device for manufacturing and a method for manufacturing a memory element having a metal oxide layer with etching resistance. Anisotropic etching is performed by the metal oxide layer (14) reacting with etching gas containi...  
WO/2012/070236A1
A non-volatile storage device in which the bit lines and word lines of a memory cell array can be wired at minimum intervals is provided. Basic array planes (0 to 3) of the non-volatile storage device comprise: first via groups (121 to 1...  
WO/2012/068127A3
A nonvolatile memory device with a first conductor extending in a first direction and a semiconductor element above the first conductor. The semiconductor element includes a source, a drain and a channel of a field effect transistor (JFE...  
WO/2012/066787A1
Provided is a nonvolatile storage element with which deterioration of the oxygen concentration profile of a variable resistance layer due to the thermal budget can be suppressed, and which is capable of stable operation at a low voltage;...  
WO/2012/066786A1
Provided are a method for manufacturing a variable resistance-type nonvolatile semiconductor storage element, and a nonvolatile semiconductor storage element that is capable of low-voltage high-speed operation during initial breakdown an...  
WO/2012/063495A1
The purpose of the present invention is to provide a process for manufacturing a resistance-variable non-volatile semiconductor storage element which has a reduced initial braking voltage, can be operated at a high velocity, and does not...  
WO/2012/061830A1
A method and apparatus for making analog and digital electronics which includes a composite including a squishable material doped with conductive particles. A microelectromechanical systems (MEMS) device has a channel made from the compo...  
WO/2012/056689A1
A nonvolatile memory device (800) comprises a resistance changing nonvolatile memory element (100), and a control circuit (810). The control circuit (810) determines whether or not the resistance value of the nonvolatile memory element (...  
WO/2012/049789A1
In the present invention, a select transistor (20) comprising an N-type MISFET has N-type source/drain regions (4) and (5) which are both provided on the upper part of a semiconductor substrate (1) with a space therebetween, a channel re...  
WO/2012/049865A1
According to one embodiment, a first electrode, a second electrode, and a variable resistance layer are provided. The variable resistance layer is arranged between the first electrode and the second electrode and contains a polycrystalli...  
WO/2012/048521A1
Disclosed are an NiO-based resistive random access memory and a method for manufacturing same. The memory unit comprises a substrate (100) and a Metal-Insulator-Metal (MIM) structure, wherein a top electrode (401) is a metal thin film ma...  
WO/2012/051041A1
A memory array is provided that includes a first memory cell (200-1) having a first conductive line (202a); a first bipolar storage element (102-1) formed above the first conductive line; and a second conductive line (302) formed above t...  
WO/2012/046454A1
Provided are a variable resistance nonvolatile storage element, which stably varies resistance with a low voltage, is suitable for a capacity increase, and has excellent reliability, and a method for manufacturing the variable resistance...  
WO/2012/043502A1
Provided is a semiconductor device comprising: a unit element having a first switch and a second switch that include a variable resistance layer having a resistance state that varies in accordance with the polarity of the applied voltage...  
WO/2012/042828A1
Provided is a memory element, wherein deterioration of and damages to a diode can be prevented even when miniaturizing the memory element. A memory element (100) of the present invention is provided with: a substrate (10); a plurality of...  
WO/2012/042897A1
This method for manufacturing a variable resistance non-volatile memory element comprises: a step for forming a first electrode (2) on a substrate (1); a step for forming a first metal oxide layer (31) having a prescribed oxygen content ...  
WO/2012/042866A1
A resistance change non-volatile memory element has a first electrode, a second electrode, and a transition metal-oxide film layer interposed between the first electrode and the second electrode. In the initial state of this resistance c...  
WO/2012/043154A1
Disclosed is a method for forming a Ge-Sb-Te film, wherein a substrate is disposed within a process chamber and a gaseous Ge material, a gaseous Sb material and a gaseous Te material are introduced into the process chamber, so that a Ge-...  
WO/2012/044473A1
A method of forming a memory cell is provided, the method including forming a diode including a first region having a first conductivity type, counter-doping the diode to change the first region to a second conductivity type, and forming...  
WO/2012/039284A1
The present invention addresses the problem of providing a three-terminal switch (electrochemical transistor) which implements a sharp on/off operation. A source electrode and a drain electrode are disposed side by side with an insulator...  

Matches 501 - 550 out of 6,078