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WO/2017/131643A1 |
A stable threshold switching material for selectors employed in resistive memories is provided. The material is amorphous and has a composition given by (V, Nb)1-x(Si, Hf, W)xOy, where 0 < x < 1 and y is within a range of 1.5 to 3.
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WO/2017/126664A1 |
A microswitch configured from a first electrode, a second electrode, and a porous polymer metal complex conductor, wherein the microswitch is characterized in that the porous polymer metal complex conductor is expressed by formula (1) be...
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WO/2017/124443A1 |
Provided are a multi-layer boron nitride-based RRAM device and a preparation method therefor. The RRAM device comprises a dielectric layer, a lower electrode and an upper electrode, wherein the dielectric layer is a multi-layer boron nit...
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WO/2017/121975A1 |
A solid state plasma monolithic microwave integrated circuit having single or multiple elemental devices with at least three terminals operating within the microwave, millimetre wave or terahertz bands, that can be configured within a pa...
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WO/2017/123498A1 |
A method is provided for forming a monolithic three-dimensional memory array. The method includes forming a first vertically-oriented polysilicon pillar above a substrate, the first vertically-oriented polysilicon pillar surrounded by a ...
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WO/2017/119752A1 |
Provided is a non-volatile memory device according to an embodiment of the present invention. The non-volatile memory device comprises: a boron-doped silicon layer having a first surface and a second surface opposite thereto; a boron-dop...
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WO/2017/111776A1 |
A non-volatile memory device is disclosed, in which a ballast resistor layer is disposed between the selector element and memory element of a given memory cell of the device. The material composition of the ballast resistor can be custom...
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WO/2017/107504A1 |
A thermal effect estimation and thermal crosstalk reduction method for a three-dimensional integrated resistive random access memory (3D RRAM) array, comprising the following steps: step 1, calculating temperature distribution in an arra...
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WO/2017/112439A1 |
Methods and apparatus for processing a substrate are disclosed herein. In some embodiments, a process chamber includes: a chamber body defining an interior volume; a substrate support to support a substrate within the interior volume; a ...
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WO/2017/111813A1 |
An embodiment includes a resistive random access memory (RRAM) comprising: top and bottom electrodes; first and second oxygen exchange layers (OELs) between the top and bottom electrodes; an oxide layer between the first and second OELs;...
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WO/2017/111812A1 |
An embodiment includes a resistive random access memory (RRAM) system comprising: a bi-polar complimentary resistive switch (CRS) comprising a top electrode, a bottom electrode, and an oxide layer between the top and bottom electrodes; w...
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WO/2017/107505A1 |
A method for improving endurance of a three-dimensional resistive random access memory (3D RRAM), comprising: step 1, calculating temperature distribution in an array by means of a 3D Fourier heat conduction equation; step 2, selecting a...
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WO/2017/109471A1 |
Subject matter disclosed herein may relate to programmable fabrics including correlated electron switch devices.
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WO/2017/106317A1 |
Resistive RAM (RRAM) devices having increased reliability and related manufacturing methods are described. Greater reliability of RRAM cells over time can be achieved by avoiding direct contact of metal electrodes with the device switchi...
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WO/2017/106515A1 |
A resistive random access memory device is formed in an integrated circuit between a first metal layer and a second metal layer and includes a first barrier layer disposed over the first metal layer, a tunneling dielectric layer disposed...
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WO/2017/104577A1 |
In order to obtain a phase-change material having a novel composition suitable for obtaining a highly practical phase-change type memory element, and a phase-change type memory element using the same, a phase-change material comprises Cr...
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WO/2017/093906A1 |
Propulsion apparatus (10) for space vehicles, comprising a solid state oxygen-rich source layer (11), means (12) for extracting oxygen from said solid state oxygen-rich source layer (11), means (16, 14, 17) for accelerating corresponding...
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WO/2017/091276A1 |
Embodiments of the present disclosure are directed towards techniques to provide structural integrity for a memory device comprising a memory array. In one embodiment, the device may comprise a memory array having at least a plurality of...
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WO/2017/091780A1 |
Three-dimensional cross-point array and process flows. In an exemplary embodiment, a method is provided that includes forming stacked layers, performing a first lithography operation on the stacked layers to form cell columns, and perfor...
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WO/2017/091151A1 |
Various embodiments may provide a pressure sensing electronic device. The electronic device may include a tactile sensor configured to determine an external pressure. The electronic device may also include a memory device electrically co...
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WO/2017/088016A1 |
A memristor device is disclosed comprising: a first electrode; a second electrode; a cathode metal layer disposed on a surface of the first electrode; and an active region disposed between and in electrical contact with the second electr...
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WO/2017/084237A1 |
A three-dimensional memory and a preparation method therefor. The three-dimensional memory is formed by vertically stacking a plurality of layers of memories, each layer comprising: strip-shaped electrodes (101, 105, 109); electro-therma...
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WO/2017/086399A1 |
According to the present invention, electrode layers 24, 26 are connected to a bismuth ferrite layer 22 by being arranged so as to sandwich the bismuth ferrite layer 22 from a direction that is perpendicular to the c-axis of a bismuth fe...
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WO/2017/078932A1 |
A three dimensional (3D) memory array is disclosed. The 3D memory array may include an electrode plane and a memory material disposed through and coupled to the electrode plane. A memory cell included in the memory material is aligned in...
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WO/2017/074548A1 |
A memory device includes at least one memory cell. The at least one memory cell includes a steering element, a resistive memory element, and a tunneling dielectric element located between the steering element and the resistive memory ele...
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WO/2017/074580A1 |
Methods for improving the operation of a memory array by arranging a Metal-Insulator-Metal (MIM) structure between a word line and an adjustable resistance bit line structure are described. The MIM structure may correspond with a metal/R...
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WO/2017/069772A1 |
In one example in accordance with the present disclosure an electrostatic discharge protection system is described. The system includes a number of electrostatic discharge absorption units coupled in parallel. An electrostatic discharge ...
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WO/2017/067314A1 |
A phase change material for a phase change memory and a preparation method therefor. A general chemical formula of the phase change material for a phase change memory is Sc100 － x-y-zGexSbyTez, 0≤x≤60, 0≤y≤90, 0≤z≤65, and 0...
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WO/2017/062786A1 |
A method for forming an electronic device may comprising the steps of selecting a substrate for an electronic device, and depositing a porous film utilizing physical vapor deposition, dry deposition, evaporative deposition, e-beam evapor...
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WO/2017/058300A1 |
A memory cell is provided that includes a vertically-oriented adjustable resistance structure including a control terminal coupled to a word line, and a reversible resistance-switching element coupled in series with and disposed above or...
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WO/2017/057046A1 |
The present art relates to a semiconductor device capable of improving yield. A volatile logic circuit of the present invention has a storage node, and stores inputted information. A plurality of nonvolatile elements are connected to the...
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WO/2017/051527A1 |
The purpose of the present invention is to enable manufacture of a metal-precipitating resistance changing element in which variations in program voltage and high-resistance-state leak current are decreased while decreasing the program v...
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WO/2017/042587A1 |
The present techniques generally relate to correlated electron switches that are capable of asymmetric set or reset operations.
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WO/2017/038095A1 |
The purpose of the present invention is to provide a method for efficiently performing characterization of a programmable logic integrated circuit having a crossbar switch involving the use of a resistance change element, in order to per...
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WO/2017/039982A1 |
Thermally-regulated electronic devices, structures, and systems having incorporated high thermal conductivity dielectric (HTCD) materials are disclosed and described, including associated methods.
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WO/2017/034741A1 |
A method of fabrication of a device includes forming a first electrode (158) and a second electrode (162). The method further includes forming a resistive material (160) between the first electrode and the second electrode to form a resi...
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WO/2017/025760A1 |
The present techniques generally relate to apparatus and methods for providing programmable currents for correlated electron switches.
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WO/2017/027175A1 |
Some embodiments include a memory cell having a pair of electrodes, and a plurality of switching levels between the electrodes. Each switching level has an ion buffer region and a dielectric region. At least one switching level differs f...
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WO/2017/021721A1 |
Subject matter disclosed herein relates to correlated electron switches.
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WO/2017/018933A1 |
A sensor element for sensing optical light may be provided. The sensor element may include a first electrode for electrically coupling to a first supply voltage, a second electrode for electrically coupling to a second supply voltage, an...
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WO/2017/019242A1 |
An array of cross point memory cells comprises spaced first lines which cross spaced second lines. Two memory cells are individually between one of two immediately adjacent of the second lines and a same single one of the first lines.
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WO/2017/019346A1 |
A method of forming an array of cross point memory cells comprises forming spaced conductive lower electrode pillars for individual of the memory cells being formed along and elevationally over spaced lower first lines. Walls cross eleva...
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WO/2017/007563A1 |
A three-dimensional (3D) non-volatile memory array having a silicide bit line and method of fabricating is disclosed. The fabrication technique may comprise forming a metal silicide for at least a portion (546a, 546b) of the bit line (53...
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WO/2017/003959A1 |
The present disclosure provides a system and method for forming a resistive random access memory (RRAM) device. A RRAM device consistent with the present disclosure includes a substrate and a first electrode disposed thereon. The RRAM de...
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WO/2016/203751A1 |
Provided is a rectifying element wherein current-voltage characteristics are improved. The rectifying element has: a first electrode and a second electrode; a rectifying layer that is provided between the first electrode and the second e...
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WO/2016/199556A1 |
Provided is a memory device having a structure suitable for higher integration while ensuring ease of manufacture. The memory device is provided with n memory cell units which are layered on a substrate successively from a first memory c...
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WO/2016/199412A1 |
In order to improve the number rewrites by improving the dielectric breakdown resistance of an ion conducting layer in a variable resistance element, this variable resistance element is provided with: a first electrode that contains at l...
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WO/2016/195763A1 |
A variable resistance memory device (100, 200, 300, 400) includes a first electrode (110, 210, 310) and a second electrode (160, 260, 360). The device may includes a chalcogenide glass (140, 240, 340) layer between the first electrode an...
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WO/2016/181609A1 |
Disclosed is a semiconductor storage device (1000) wherein: a first selection line (108) and a second selection line (109) are provided; a first storage element (100) of a plurality of storage elements has a first upper electrode (101) a...
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WO/2016/162053A1 |
A memristor function based on an orthogonal electrode is disclosed. One example is a memristor device with a plurality of electrodes (108, 110, 112, 114), including a first group of electrodes (108, 110), a second group of electrodes (11...
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