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Matches 51 - 100 out of 6,078

Document Document Title
WO/2018/144457A1
Methods for scaling dimensions of resistive change elements, resistive change element arrays of scalable resistive change elements, and sealed resistive change elements are disclosed. According to some aspects of the present disclosure t...  
WO/2018/143611A1
The present invention relates to a method for manufacturing a large-area metal chalcogenide thin film and a device comprising the large-area metal chalcogenide thin film manufactured thereby, the method comprising the steps of: preparing...  
WO/2018/138482A1
The present techniques generally relate to fabrication of correlated electron materials used, for example, to perform specified application performance parameters 277-283. In embodiments, CEM devices fabricated at a first stage of a wafe...  
WO/2018/138275A1
The invention relates to a metal-insulator-graphene diode, comprising a metal electrode (34) having an electrode surface, comprising an insulator layer (28), which is in planar contact with the electrode surface via a first main surface ...  
WO/2018/134561A1
An electronicfilter circuit comprising resistive and capacitive elements, wherein a resistive element of the filter circuit is provided by a correlated electron material device. The electronic filter circuit may form part of a tuneable a...  
WO/2018/136140A1
Resistive memory cells containing nanoparticles are formed between two electrodes. The nanoparticles may be embedded in a matrix or sintered together without a matrix. The memory cells may be projected memory cells or barrier modulated c...  
WO/2018/134699A1
A phase change memory array and method for fabricating the same. The phase change memory array includes a plurality of bottom electrodes, top electrodes, and memory pillars. Each of the memory pillars includes phase change material surro...  
WO/2018/130914A1
A memristive device includes a first conductive material layer. An oxide material layer is arranged on the first conductive layer. A second conductive material layer is arranged on the oxide material layer, where in the second conductive...  
WO/2018/123678A1
Provided is a metal-bridged-type resistance variable element in which a switching voltage and variations thereof are decreased, and which is suitable for high-density integration. The resistance variable element comprises: a metal precip...  
WO/2018/125174A1
Substrates, assemblies, and techniques for a transmission gate that includes an n-type back end transistor and a p-type back end transistor in parallel with the n-type back end transistor. The transmission gate can be on a non-silicon su...  
WO/2018/125238A1
In various embodiments, low-density dielectrics (for example, interlayer dielectrics, ILDs) can be used as the active layer in conduction bridging random access memory (CBRAM) devices. Further, such low-density dielectrics may permit a p...  
WO/2018/125386A1
Doping a storage element, a selector element, or both, of a memory cell with a dopant including one or more of aluminum (Al), zirconium (Zr), hafnium (Hf), and silicon (Si), can minimize volume or density changes in a phase change memory...  
WO/2018/122156A1
The invention relates to a solution for using elementary electrochemical components, manufactured from the same arrangement of materials and incorporated in a single electronic circuit, for information storage or for energy storage. Elec...  
WO/2018/125237A1
In one embodiment, systems, methods, and apparatus are described that can reduce the peak current through semiconductor memory devices such as RRAM devices. In one embodiment, transition metal dichalcogenide (TMD) materials can be used t...  
WO/2018/113142A1
A porphyrin memristor device and a method of fabrication of the device are described that include a three-tier structure as anode, switching layer and cathode, the switching layer is interposed between the anode and cathode, also include...  
WO/2018/117358A1
Provided is a soft electronic system having an integrated memory and logic device, comprising: a substrate (100); a first electrode (110) provided in the form of a plurality of bars stacked on the substrate; a resistance-variable substan...  
WO/2018/115831A1
The present techniques generally relate to forming a nucleation layer in connection with fabrication of correlated electron materials used, for example, to perform, for example, a switching function. In embodiments, processes are describ...  
WO/2018/104733A1
The present techniques generally relate to fabrication of correlated electron materials used, for example, to perform a switching function. In embodiments, processes are described in which a correlated electron material film may be forme...  
WO/2018/104727A1
The present techniques generally relate to fabrication of a correlated electron material (CEM) device (300). In embodiments, after formation of the one or more CEM traces (330, 331), a spacer (335) is deposited in contact with the one or...  
WO/2018/106450A1
A resistive random access memory cell includes three resistive random access memory devices (102, 104, 106), each resistive random access memory device having an ion source layer (156, 166, 186) and a solid electrolyte layer (154, 164, 1...  
WO/2018/100372A1
The present techniques generally relate to correlated electron switch devices, and may relate more particularly to digital to analog conversion using correlated electron switch devices.  
WO/2018/100380A1
The present techniques generally relate to fabrication of a correlated electron material (CEM) switch. In embodiments, processes are described in which conductive traces (222) may be formed on or over an insulating material (210). Respon...  
WO/2018/101573A1
A light-emitting element display device and a manufacturing method therefor are disclosed. According to the present invention, the light-emitting element display device comprises a light-emitting element array including a plurality of li...  
WO/2018/101956A1
Self-aligned electrode nano-contacts for non-volatile random access memory (RAM) bit cells, and methods of fabricating electrode nano-contacts for non-volatile random access memory (RAM) bit cells, are described. In an example, semicondu...  
WO/2018/100341A1
The present techniques generally relate to an improved CEM switching device (350) and methods for its manufacture. In this device, a conductive substrate (370) and/or conductive overlay (380) each comprises a primary layer (370a, 380a) o...  
WO/2018/095368A1
A phase change electronic device (100), comprising: a first conductive layer (120); a second conductive layer (140) spaced apart from and disposed oppositely to the first conductive layer (120); and a phase change material layer (150) di...  
WO/2018/095367A1
A regulation and control method of a phase change of a hydrogen-containing transition metal oxide, the method comprising the following steps: S100, providing a hydrogen-containing transition metal oxide having a structural formula ABOxHy...  
WO/2018/097911A1
A method of forming a memory device includes forming a first layer of conductive material having opposing upper and lower surfaces, forming a layer of amorphous silicon on the upper surface of the first layer of conductive material, stri...  
WO/2018/091828A1
The invention relates to a process for manufacturing a resistive random-access memory, comprising the following steps: depositing a layer (410) made of an active material of variable electrical resistance on a substrate (300) containing ...  
WO/2018/089937A1
Disclosed is a resistive random access memory (RRAM). The RRAM includes a bottom electrode made of tungsten and a switching layer made of hafnium oxide disposed above the bottom electrode, wherein the switching layer includes a filament ...  
WO/2018/089936A1
Disclosed is a resistive random access memory (RRAM). The RRAM includes a bottom electrode made of tungsten and a switching layer made of hafnium oxide disposed above the bottom electrode, wherein the switching layer includes a switchabl...  
WO/2018/089936A9
Disclosed is a resistive random access memory (RRAM). The RRAM includes a bottom electrode made of tungsten and a switching layer made of hafnium oxide disposed above the bottom electrode, wherein the switching layer includes a switchabl...  
WO/2018/066320A1
A switch element according to one embodiment of the present disclosure is provided with a first electrode, a second electrode that is arranged to face the first electrode, and a switch layer that is disposed between the first electrode a...  
WO/2018/063287A1
Substrates, assemblies, and techniques for enabling a resistive random access memory cell are disclosed herein. For example, in some embodiments, a device may include a top electrode, a modulated interfacial region, and a bottom electrod...  
WO/2018/063265A1
Substrates, assemblies, and techniques for enabling a dual pedestal for resistive random access memory are disclosed herein. For example, in some embodiments, a device may include a substrate, wherein the substrate includes a fill metal,...  
WO/2018/063320A1
Conductive bridge random access memory (CBRAM) devices with low thermal conductivity electrolyte sublayers are described. In an example, a conductive bridge random access memory (CBRAM) device includes a conductive interconnect disposed ...  
WO/2018/060692A1
The present techniques generally relate to correlated electron switch devices, and may relate more particularly to voltage detection with correlated electron switch devices.  
WO/2018/063093A1
According to embodiments of the present invention, a memory device is provided. The memory device includes an electrochemical metallization memory (ECM) cell and a valence change memory (VCM) cell arranged one over the other. According t...  
WO/2018/063209A1
Substrates, assemblies, and techniques for enabling a resistive random access memory cell are disclosed herein. For example, in some embodiments, a device may include a source, where the source includes a source junction, a gate, and a d...  
WO/2018/063370A1
An apparatus is described. The apparatus includes a semiconductor chip that includes logic circuitry, embedded dynamic random access memory (DRAM) cells and embedded resistive random access memory (RRAM) cells.  
WO/2018/060656A1
The invention relates to a supercapacitor comprising: an electrolyte having a first end and a second end opposite the first end; a first electrode (E1) in contact with the first end of the electrolyte; and a second electrode (E2) in cont...  
WO/2018/063322A1
Spacer-based patterning for tight-pitch and low-variability random access memory (RAM) bit cells, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate having a top layer. An array of ...  
WO/2018/063164A1
Embodiments include a resistive random access memory (RRAM) memory cell which is the same as a RRAM storage cell. The RRAM storage cell has a resistive material layer and a semiconductor layer between two electrodes, where the semiconduc...  
WO/2018/063207A1
Substrates, assemblies, and techniques for enabling a resistive random access memory cell are disclosed herein. For example, in some embodiments, a device may include a source junction, a gate, a drain junction, a semiconductor located b...  
WO/2018/057022A1
Disclosed herein are metal filament memory devices (MFMDs), and related devices a techniques. In some embodiments, an MFMD may include: an electrode including an electrochemically active metal; an electrolyte; and a barrier material disp...  
WO/2018/057021A1
Disclosed herein are metal filament memory cells, and related devices and techniques. In some embodiments, a memory cell may include: a transistor having a source/drain region; and a metal filament memory device including an active metal...  
WO/2018/055346A1
The presently disclosed techniques relate to devices and methods of their manufacture, comprising either a first metal layer Mn, a substrate formed thereon with a cavity exposing a portion of the metal layer, and a correlated electron ma...  
WO/2018/057012A1
Embodiments include a threshold switching selector. The threshold switching selector may include a threshold switching layer and a semiconductor layer between two electrodes. A memory cell may include the threshold switching selector cou...  
WO/2018/054683A1
The present invention is notably directed to display device (1, 1a d), comprising a set of pixels, each having a layer structure (2, 2c, 2d) that includes: a bi-stable, phase change material (10), or bi-stable PCM, having at least two re...  
WO/2018/056963A1
Conductive bridge random access memory (CBRAM) devices with graded conductivity electrolyte layers are described. In an example, a conductive bridge random access memory (CBRAM) device includes a conductive interconnect disposed in an in...  

Matches 51 - 100 out of 6,078