| Document |
Document Title |
|
WO/2016/162053A1 |
A memristor function based on an orthogonal electrode is disclosed. One example is a memristor device with a plurality of electrodes (108, 110, 112, 114), including a first group of electrodes (108, 110), a second group of electrodes (11...
|
|
WO/2016/163120A1 |
In the cases of performing programming by forming a two-terminal-type variable resistance element on a semiconductor device, it has been difficult to control the programming, and malfunctions have often occurred. This switching element i...
|
|
WO/2016/158430A1 |
A switch element according to one embodiment of the present technique is provided with: a first electrode; a second electrode that is arranged to face the first electrode; and a switch layer that is arranged between the first electrode a...
|
|
WO/2016/160223A1 |
Phase change memory cells, structures, and devices having a phase change material and an electrode forming an ohmic contact therewith are disclosed and described. Such electrodes can have a resistivity of from 10 to 100 mOhm•cm.
|
|
WO/2016/157820A1 |
Provided is a switching element in which it is made possible to improve ON-state retention performance and reduce OFF-state leak current. This switching element has a first electrode, a second electrode, and a resistance change layer pro...
|
|
WO/2016/157334A1 |
In this semiconductor storage device, which is formed by film-forming a phase changing material layer on a channel semiconductor layer of a transistor, and which needs to flow a current between the channel semiconductor layer and the pha...
|
|
WO/2016/160277A1 |
Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucle...
|
|
WO/2016/158429A1 |
A switch element according to one embodiment of the present technique is provided with: a first electrode; a second electrode that is arranged to face the first electrode; and a switch layer that is arranged between the first electrode a...
|
|
WO/2016/153461A1 |
In the examples provided herein, a memristive device is disclosed that has a first electrode, a second electrode, and a doped sol-gel switching layer sandwiched between the first electrode and the second electrode. The doped sol-gel swit...
|
|
WO/2016/144960A1 |
A process for forming a resistive random-access memory device, the process comprising the steps of: depositing a first electrode on a substrate; forming a porous resistive memory material layer on the first electrode, wherein the porous ...
|
|
WO/2016/129306A1 |
This selective element is provided with: a first electrode and a second electrode that is arranged so as to face the first electrode; a switch element that is provided between the first electrode and the second electrode; and a nonlinear...
|
|
WO/2016/123881A1 |
A nonvolatile resistive memory, comprising an inert metal electrode (15), a resistive functional layer (14), and an easily oxidizable metal electrode (12), and characterized in that: inserted between the easily oxidizable metal electrode...
|
|
WO/2016/126834A1 |
Providing for a two-terminal memory cell having intrinsic current limiting characteristic is described herein. By way of example, the two-terminal memory cell can comprise a particle donor layer having a moderate resistivity, comprised o...
|
|
WO/2016/123882A1 |
A nonvolatile resistive memory, comprising an inert metal electrode (12), a resistive functional layer (14), and an easily oxidizable metal electrode (15), and characterized in that: inserted between the inert metal electrode (12) and th...
|
|
WO/2016/126307A1 |
A memory device, such as a ReRAM device includes plural interdigitated word lines (112, 116) and a single select transistor (110a) controlling plural vertical local bit lines (122a). The interdigitated word lines may be word line combs c...
|
|
WO/2016/124969A3 |
All-printed paper-based substrate memory devices are described which can be prepared by a process that includes coating, using a screen printer, one or more areas of a paper substrate (102) with a conductor material (104), such as a carb...
|
|
WO/2016/122406A1 |
Embodiments provide a selector device for selecting a memory cell. The selector device includes a first electrode; a second electrode; and a switching layer sandwiched between the first electrode and the second electrode. The switching l...
|
|
WO/2016/123088A1 |
A sensing apparatus includes a light source to transmit a light beam, an input switch, a first sensing element, a second sensing element, and a detector. The input switch receives the light beam and includes a phase change material havin...
|
|
WO/2016/122445A1 |
A resistive memory array includes a plurality of resistive memory devices. A sneak path current in the resistive memory array is reduced when a negative temperature coefficient of resistance material is incorporated in series with a nega...
|
|
WO/2016/117225A1 |
A memory cell is provided with: an antifuse inserted into each of a plurality of paths, said paths being connected to each other at one end thereof; a resistive element that is inserted into at least one of the plurality of paths; and a ...
|
|
WO/2016/114311A1 |
The forming voltage of a resistance change element used in a non-volatile memory and the like is decreased, and repetition characteristics are improved. In an element structure in which a metal oxide film 12 is sandwiched between a lower...
|
|
WO/2016/111306A1 |
This semiconductor device comprises an active layer that is formed of an oxide magnetic material and a porous dielectric body that contains water and is provided on the active layer. By using hydrogen and oxygen which are formed by elect...
|
|
WO/2016/105673A1 |
A memory device (and method of making and using the memory device) includes a first electrode of conductive material, a second electrode of conductive material, and a layer transition metal oxide material that includes first and second e...
|
|
WO/2016/101246A1 |
A self-gating resistance random access memory unit and a manufacturing method therefor, which relate to the technical field of memories. The self-gating resistance random access memory unit comprises: a stack structure, comprising multip...
|
|
WO/2016/101247A1 |
Disclosed a three-terminal atom switch device and a manufacturing method therefor. The three-terminal atom switch device comprises a stacking structure comprising a source end (301) and a drain end (302), a vertical groove formed by etch...
|
|
WO/2016/105750A1 |
Embodiments of the present disclosure describe phase-change memory cell implant for dummy array leakage reduction. In an embodiment, an apparatus includes a plurality of phase-change memory (PCM) elements, wherein individual PCM elements...
|
|
WO/2016/097252A1 |
A resistive switching memory cell (100) comprises a stack of a first electrode (110), a first inner region (120), a second inner region (130), and a second electrode (140). The first inner region (120) comprises one or more metal oxide l...
|
|
WO/2016/099580A3 |
An integrated circuit which enables lower cost yet provides superior performance compared to standard silicon integrated circuits by utilizing thin film transistors (TFTs) fabricated in BEOL. Improved memory circuits are enabled by utili...
|
|
WO/2016/094223A1 |
Provided are resistive random access memory (ReRAM) cells with embedded resistors and methods of fabricating these cells. An embedded resistor may include a metal silicon nitride of a first metal and may be doped with a second metal, whi...
|
|
WO/2016/094233A1 |
Provided are memory cells, such as resistive random access memory (ReRAM) cells, and methods of fabricating such cells. A cell includes an embedded resistor and resistive switching layer connected in series within the embedded resistor. ...
|
|
WO/2016/092374A1 |
All-printed paper-based substrate memory devices are described which can be prepared by a process that includes coating, using a screen printer, one or more areas of a paper substrate (102) with a conductor material (104), such as a carb...
|
|
WO/2016/094010A1 |
A resistive switching memory comprising a first electrode and a second electrode; an active resistive switching region between the first electrode and the second electrode, the resistive switching region comprising a transition metal oxi...
|
|
WO/2016/089542A1 |
Embodiments of the present disclosure describe barrier film techniques and configurations for phase-change memory elements. In an embodiment, an apparatus includes a plurality of phase-change memory (PCM) elements, wherein individual PCM...
|
|
WO/2016/086179A1 |
The proposed method of forming a resistive memory cell, preferably for CBRAM or ReRAM arrays, includes forming a conductive layer, oxidizing an exposed area and removing a region of the conductive layer proximate the oxidized region (110...
|
|
WO/2016/085590A1 |
Embodiments of the present disclosure describe electrode configurations to increase electro-thermal isolation of phase-change memory elements and associated techniques. In an embodiment, an apparatus includes a plurality of phase-change ...
|
|
WO/2016/084349A1 |
The objective of the present invention is to make it possible to manufacture, with a high yield, a metal deposition type variable-resistance element with which variability in a leakage current under a program voltage and a high resistanc...
|
|
WO/2016/080146A1 |
This semiconductor device is provided with: a flip flop circuit which has an annular structure wherein a first inverter circuit, a first connection line comprising a first node, a second inverter circuit, and a second connection line com...
|
|
WO/2016/073152A1 |
A cross-point memory array includes a plurality of variable resistance memory cell pillars. Adjacent memory cell pillars are separated by a partially filled gap that includes a buried void. In addition, adjacent memory cell pillars inclu...
|
|
WO/2016/062613A1 |
The invention relates to a method for manufacturing a resistive device, comprising the following steps: depositing a first electrically conductive layer on a substrate; forming an engraving mask on the first conductive layer; engraving t...
|
|
WO/2016/060973A1 |
The present disclosure includes select devices and methods of using select device for memory cell applications. An example select device includes a first electrode having a particular geometry, a semiconductor material formed on the firs...
|
|
WO/2016/059941A1 |
This electronic device is provided with a substrate, a channel section, a first electrode, a second electrode, and a shape change generating section. The channel section is provided on the substrate, and contains a phase transition mater...
|
|
WO/2016/057508A1 |
A memory element can include a first electrode; at least one switching layer formed over the first electrode; a second electrode layer; and at least one conductive cap layer formed over the second electrode layer having substantially no ...
|
|
WO/2016/056352A1 |
The present invention is a niobium oxide sintered compact characterized by having the composition NbOx (2 < x < 2.5). The present invention provides a niobium oxide sintered compact which can be applied as a sputtering target for forming...
|
|
WO/2016/052097A1 |
This switch element is provided with a first electrode, a second electrode disposed opposite the first electrode, and a switch layer provided between the first electrode and the second electrode, the switch layer comprising an amorpho...
|
|
WO/2016/048701A1 |
Devices and systems having a diffusion barrier (408) for limiting diffusion of a phase change material including an electrode (402, 404), a phase change material (406) electrically coupled to the electrode, and a carbon and TiN (C:TiN) d...
|
|
WO/2016/048681A1 |
Methods and apparatuses, wherein the method includes providing a logic device. The method substantially surrounds a metal gate with a transition metal oxide on at least one side, wherein the transition metal oxide is comprised of hafnium...
|
|
WO/2016/047254A1 |
In the memory cell unit array according to the present invention, memory cell units 10, composed of first wiring 31, second wiring and a non-volatile memory cell, are arranged in the form of a two-dimensional matrix in a first direction ...
|
|
WO/2016/042750A1 |
A purpose of the invention is to provide a crossbar switch for reducing the layout areas of a crossbar switch and peripheral circuits thereof. A crossbar switch of the invention comprises: a plurality of first wires extending in a first ...
|
|
WO/2016/043657A1 |
According to various embodiments, there is provided a memory structure including a conductive core; and a switching material layer at least partially surrounding the conductive core, wherein the switching material layer includes a plural...
|
|
WO/2016/039694A1 |
Various embodiments provide a memory cell including a memory layer having a first surface and a second surface opposite to the first surface. The memory layer includes a material configured to provide variable resistances. The memory cel...
|
