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WO/2017/181417A1 |
Disclosed are a manufacturing method of a Cu-based resistive random access memory, and a memory. The manufacturing method comprises: forming a copper wire in a groove by means of a damascene process for forming a copper interconnection, ...
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WO/2017/182826A1 |
The present invention relates to novel memristive devices, uses thereof, and processes for their preparation. In a first aspect the invention provides a quantum memristor, comprising a first quantum dot (QD1 ) which is capacitively coupl...
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WO/2017/181418A1 |
Provided are a manufacturing method of a Cu-based resistive random access memory, and a memory. The manufacturing method comprises: chemically reacting a pattern of a lower copper electrode (10) to form a compound buffer layer (40), the ...
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WO/2017/171820A1 |
An embodiment includes an apparatus comprising: first and second electrodes; first and second insulation layers between the first and second electrodes; and a middle layer between the first and second insulation layers; wherein (a) the m...
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WO/2017/172071A1 |
A method is provided that includes forming a vertical bit line disposed in a first direction above a substrate, forming a multi-layer word line disposed in a second direction above the substrate, the second direction perpendicular to the...
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WO/2017/171819A1 |
An embodiment includes a memory comprising: a top electrode and a bottom electrode; an oxygen exchange layer (OEL) between the top and bottom electrodes; and an oxide layer between the OEL and the bottom electrode; wherein the oxide laye...
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WO/2017/170149A1 |
To stabilize programming operation and to reduce leakage current. A variable resistance element according to the present invention is provided with: an interlayer insulating film; a first electrode that is formed within the interlayer in...
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WO/2017/171780A1 |
One embodiment provides an apparatus. The apparatus includes a first memory cell and a second memory cell. The first memory cell includes a first resistive element. The first resistive element includes a first top electrode, a common bot...
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WO/2017/171821A1 |
An embodiment includes a programmable metallization cell (PMC) memory comprising: a top electrode and a bottom electrode; a metal layer between the top and bottom electrodes; and a solid electrolyte (SE) layer between the metal layer and...
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WO/2017/164487A1 |
A memory device according to the present invention comprises: a substrate; a coupling layer having electrical conductivity and located on the substrate; a meta-atomic layer located above or below the coupling layer; a memory layer locate...
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WO/2017/164689A2 |
The present invention relates to a technology wherein a memristor element that joins a memory and a resistor is laminated on a predetermined metal compound layer so as to manufacture the same as a characteristic element capable of contro...
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WO/2017/160233A1 |
Embodiments provide a memory device, including a plurality of insulating layers and a plurality of lateral layer arrangements. The lateral layer arrangements and the insulating layers are arranged alternately on each other such that each...
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WO/2017/157074A1 |
Disclosed are a selector for use in a bipolar resistive memory and a manufacturing method for the selector. The method comprises: providing a substrate (20) (S101); forming a lower substrate (21) on the substrate (20) (S102); forming a f...
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WO/2017/155668A1 |
A method is provided that includes forming a vertical bit line (LBL11) disposed in a first direction above a substrate (502), forming a word line (WL10) disposed in a second direction above the substrate, the second direction perpendicul...
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WO/2017/149285A1 |
Subject matter disclosed herein relates to correlated electron switch devices, and relates more particularly to one or more barrier layers (615, 625) having various characteristics formed under and/or over and/or around correlated electr...
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WO/2017/151296A1 |
A memory device and method comprising a metal oxide material disposed between and in electrical contact with first and second conductive electrodes, and a voltage source configured to apply a plurality of voltage pulses spaced apart in t...
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WO/2017/150617A1 |
Provided is a thin film in which the semiconductor characteristics of an In-Ga-Zn-O-based oxide are reversible, and a method of manufacturing the same. A semiconductor/insulator reversible-change thin film comprising an In-Ga-Zn-O-based ...
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WO/2017/146927A1 |
The present invention provides a method for creating patterns, with features down to the nanometer scale, in phase change materials using a heated probe. The heated probe contacts the phase change material thereby inducing a local phase ...
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WO/2017/141042A1 |
A method for forming a thin film (302) comprising a metal, metal compound, or metal oxide on a substrate, which method comprises forming one or more thin film layers (303, 304, 305) of a metal or metal oxide by a deposition process emplo...
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WO/2017/140647A1 |
The disclosed composition, particularly suitable for resistance switching memories based on metal ion transport, comprises a matrix material of a metal oxide/sulphide/selenide of at least two metals M1 and M2, and a metal M3 which is mob...
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WO/2017/142790A1 |
Systems and methods for improving performance of a non-volatile memory that utilizes a Vacancy Modulated Conductive Oxide (VMCO) structure are described. The VMCO structure may include a layer of amorphous silicon (e.g., a Si barrier lay...
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WO/2017/140646A1 |
The disclosed resistive switching memory cell comprises a switchable solid electrolyte matrix comprising a metal oxide/sulphide/selenide comprising at least two metals M1 and M2, and a metal M3 which is mobile in the matrix, wherein - th...
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WO/2017/141031A1 |
The present techniques generally relate to the fabrication of correlated electron materials used, for example, to perform a switching function. In embodiments, precursors, in a gaseous form, may be utilized in a chamber to build a film o...
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WO/2017/141043A1 |
The present techniques generally relate to fabrication of correlated electron materials used, for example, to perform a switching function. In embodiments, precursors, in a gaseous form, may be utilized in a chamber to build a film of co...
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WO/2017/138886A1 |
Various embodiments may provide a device for controlling an electromagnetic wave according to various embodiments. The device may include a medium. The device may further include an array of elements in contact with the medium and may be...
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WO/2017/131897A1 |
A vacancy-modulated conductive oxide (VMCO) resistive random access memory (ReRAM) device includes at least one interfacial layer between a semiconductor portion and a titanium oxide portion of a resistive memory element. The at least on...
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WO/2017/131642A1 |
A resistive memory cell is integrated with a selector. The device structure includes a stack of a first electrode, one of a selector or a resistive switching layer, and a second electrode formed in a device layer of a multilayer structur...
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WO/2017/129970A1 |
The present techniques generally relate to fabrication of correlated electron materials used, for example, to perform a switching function. In embodiments, precursors, in a gaseous form, may be utilized in a chamber to build a film of co...
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WO/2017/129972A1 |
The present techniques generally relate to fabrication of correlated electron materials used, for example, to perform a switching function. In embodiments, a correlated electron material may comprise a dominant ligand and a substitutiona...
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WO/2017/131643A1 |
A stable threshold switching material for selectors employed in resistive memories is provided. The material is amorphous and has a composition given by (V, Nb)1-x(Si, Hf, W)xOy, where 0 < x < 1 and y is within a range of 1.5 to 3.
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WO/2017/126664A1 |
A microswitch configured from a first electrode, a second electrode, and a porous polymer metal complex conductor, wherein the microswitch is characterized in that the porous polymer metal complex conductor is expressed by formula (1) be...
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WO/2017/124443A1 |
Provided are a multi-layer boron nitride-based RRAM device and a preparation method therefor. The RRAM device comprises a dielectric layer, a lower electrode and an upper electrode, wherein the dielectric layer is a multi-layer boron nit...
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WO/2017/121975A1 |
A solid state plasma monolithic microwave integrated circuit having single or multiple elemental devices with at least three terminals operating within the microwave, millimetre wave or terahertz bands, that can be configured within a pa...
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WO/2017/123498A1 |
A method is provided for forming a monolithic three-dimensional memory array. The method includes forming a first vertically-oriented polysilicon pillar above a substrate, the first vertically-oriented polysilicon pillar surrounded by a ...
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WO/2017/119752A1 |
Provided is a non-volatile memory device according to an embodiment of the present invention. The non-volatile memory device comprises: a boron-doped silicon layer having a first surface and a second surface opposite thereto; a boron-dop...
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WO/2017/111776A1 |
A non-volatile memory device is disclosed, in which a ballast resistor layer is disposed between the selector element and memory element of a given memory cell of the device. The material composition of the ballast resistor can be custom...
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WO/2017/107504A1 |
A thermal effect estimation and thermal crosstalk reduction method for a three-dimensional integrated resistive random access memory (3D RRAM) array, comprising the following steps: step 1, calculating temperature distribution in an arra...
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WO/2017/112439A1 |
Methods and apparatus for processing a substrate are disclosed herein. In some embodiments, a process chamber includes: a chamber body defining an interior volume; a substrate support to support a substrate within the interior volume; a ...
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WO/2017/111813A1 |
An embodiment includes a resistive random access memory (RRAM) comprising: top and bottom electrodes; first and second oxygen exchange layers (OELs) between the top and bottom electrodes; an oxide layer between the first and second OELs;...
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WO/2017/111812A1 |
An embodiment includes a resistive random access memory (RRAM) system comprising: a bi-polar complimentary resistive switch (CRS) comprising a top electrode, a bottom electrode, and an oxide layer between the top and bottom electrodes; w...
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WO/2017/107505A1 |
A method for improving endurance of a three-dimensional resistive random access memory (3D RRAM), comprising: step 1, calculating temperature distribution in an array by means of a 3D Fourier heat conduction equation; step 2, selecting a...
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WO/2017/109471A1 |
Subject matter disclosed herein may relate to programmable fabrics including correlated electron switch devices.
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WO/2017/106317A1 |
Resistive RAM (RRAM) devices having increased reliability and related manufacturing methods are described. Greater reliability of RRAM cells over time can be achieved by avoiding direct contact of metal electrodes with the device switchi...
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WO/2017/106515A1 |
A resistive random access memory device is formed in an integrated circuit between a first metal layer and a second metal layer and includes a first barrier layer disposed over the first metal layer, a tunneling dielectric layer disposed...
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WO/2017/104577A1 |
In order to obtain a phase-change material having a novel composition suitable for obtaining a highly practical phase-change type memory element, and a phase-change type memory element using the same, a phase-change material comprises Cr...
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WO/2017/093906A1 |
Propulsion apparatus (10) for space vehicles, comprising a solid state oxygen-rich source layer (11), means (12) for extracting oxygen from said solid state oxygen-rich source layer (11), means (16, 14, 17) for accelerating corresponding...
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WO/2017/091276A1 |
Embodiments of the present disclosure are directed towards techniques to provide structural integrity for a memory device comprising a memory array. In one embodiment, the device may comprise a memory array having at least a plurality of...
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WO/2017/091780A1 |
Three-dimensional cross-point array and process flows. In an exemplary embodiment, a method is provided that includes forming stacked layers, performing a first lithography operation on the stacked layers to form cell columns, and perfor...
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WO/2017/091151A1 |
Various embodiments may provide a pressure sensing electronic device. The electronic device may include a tactile sensor configured to determine an external pressure. The electronic device may also include a memory device electrically co...
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WO/2017/088016A1 |
A memristor device is disclosed comprising: a first electrode; a second electrode; a cathode metal layer disposed on a surface of the first electrode; and an active region disposed between and in electrical contact with the second electr...
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