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Matches 301 - 350 out of 6,156

Document Document Title
WO/2016/043657A1
According to various embodiments, there is provided a memory structure including a conductive core; and a switching material layer at least partially surrounding the conductive core, wherein the switching material layer includes a plural...  
WO/2016/039694A1
Various embodiments provide a memory cell including a memory layer having a first surface and a second surface opposite to the first surface. The memory layer includes a material configured to provide variable resistances. The memory cel...  
WO/2016/038991A1
According to an embodiment of the present invention, a memory device includes first to third layers. The first layer includes a plurality of first wiring lines, and a first insulating portion. The first wiring lines extend in a first dir...  
WO/2016/039974A1
The disclosure concerns a phase-change material switch (50). The switch includes a first terminal (52) that receives an input signal and a second terminal (54). The switch includes an actuation portion (60, 64, 66) that receives a contro...  
WO/2016/040792A1
Systems, methods, and apparatus are provided for tuning a memristive property of a device. The device (500) includes a layer of a dielectric material (507) disposed over and forming an interface with a layer of an electrically conductive...  
WO/2016/018313A1
According to an example, an apparatus may include an input line, an output line, and a memory cell connected between the input line and the output line. The memory cell may include a memristor connected in series with a selector. The app...  
WO/2016/010325A1
The present invention relates to a multi-magnetic card and a method for manufacturing a magnetic cell. The multi-magnetic card, according to one embodiment of the present invention, comprises: a plate; and a magnetic field-generating por...  
WO/2016/010324A1
The present invention relates to a multi-magnetic card. The multi-magnetic card, according to one embodiment of the present invention, comprises: a plate; a magnetic field-generating portion including a magnetic cell, which forms a magne...  
WO/2016/009472A1
The present invention addresses the problem of providing a phase change memory cell requiring little electric current and electric power to rewrite data. Additionally, the present invention addresses the problem of providing a phase chan...  
WO/2016/003865A1
The present disclosure includes memory cells and methods of forming the same. The memory cells disclosed herein can include a first selecting chalcogenide material, a second selecting chalcogenide material, and a storage material.  
WO/2015/198573A1
Provided are a semiconductor device and a method of manufacturing the semiconductor device which enable a hard copy of a reconstruction circuit, which employs a resistance change element, to be formed at low cost. The method of manufactu...  
WO/2015/196412A1
A metal doped Ge-Sb-Te-based multivalue storage phase-change material, represented by general formula MX(GeaSbbTec)1-X, wherein M is a doping metal element, M is at least one of Cu, Ag and Zn, x represents the atom number percentage of M...  
WO/2015/186164A1
A semiconductor storage device includes: a semiconductor substrate; a first storage unit; a second storage unit made up of a plurality of first storage units formed in a first direction parallel to the semiconductor substrate; a third st...  
WO/2015/182074A1
The semiconductor device according to the present invention has an upper electrode, a first lower layer wiring that also functions as a lower electrode, an electrical resistance-changing film interposed between the upper electrode and th...  
WO/2015/177972A1
Various embodiments of the present invention are directed to a method for passivating a metal line (300, 301, 302, 310), e.g. a memory cell and a source line of a CBRAM, prior to removing a masking layer (106) in order to prevent oxidati...  
WO/2015/177971A1
Exemplary embodiments of the present invention are directed towards a method for fabricating a semiconductor memory device comprising selectively depositing a material to form a cap (300) above a recessed cell structure (202) in order to...  
WO/2015/169142A1
A multi-valued phase change storage unit comprises phase change material layers (104, 105), heating electrodes (103, 106), a top electrode (101), a bottom electrode (107) and a thermal insulation material layer (102). The phase change ma...  
WO/2015/167357A1
A device is disclosed which comprises a first electrode (101), a second electrode (104) spaced from the first electrode, a switching region (102) positioned between the first electrode and the second electrode, and an intermediate region...  
WO/2015/165088A1
A phase change memory comprises a storage node. The storage node comprises: a lower electrode (1), used for being connected to a substrate; a first phase-change layer (2), located on the lower electrode; a second phase-change layer (2), ...  
WO/2015/167351A1
A device is disclosed which comprises a first electrode (101) and a second electrode (104) spaced from the first electrode, a switching region (102) positioned between the first electrode and the second electrode, and an intermediate reg...  
WO/2015/146311A1
An Al-Te-Cu-Zr alloy sputtering target characterized by comprising 20 to 40 at% of Te, 5 to 20 at% of Cu, 5 to 15 at% of Zr and a remainder made up by Al, wherein a Te phase, a Cu phase and a CuTe phase do not exist in the target structu...  
WO/2015/145746A1
 Provided are a method for vapor-phase growth of a phase-change thin film, and a device for vapor-phase growth of a phase-change thin film, with which a phase-change thin film is formed at low temperature while retained in an amorphous...  
WO/2015/137256A1
Provided is a transistor equipped with: a piezoresistor (10) through which a carrier is conducted; a source (14) which injects the carrier into the piezoresistor; a drain (16) which receives the carrier from the piezoresistor; a piezoele...  
WO/2015/139033A1
Systems, methods, and apparatus are provided for tuning a functional property of a device. The device (210) includes a layer of a dielectric material (214) disposed over and forming an interface (216) with a layer of an electrically cond...  
WO/2015/139033A8
Systems, methods, and apparatus are provided for tuning a functional property of a device. The device (210) includes a layer of a dielectric material (214) disposed over and forming an interface (216) with a layer of an electrically cond...  
WO/2015/133073A1
Provided is a nonvolatile switching element which has high retention ability even if programmed at a low current, while being suppressed in dielectric breakdown of a variable resistance layer during a reset operation. This switching elem...  
WO/2015/129413A1
 In this method of oxidizing treatment of a transition metal film for oxidizing a film containing a transition metal on the surface of an object to be treated, plasma of gas containing at least oxygen is generated, electrons are donate...  
WO/2015/129021A1
Provided are a structure and a manufacturing method for a storage device that allow resetting to be performed using a reset gate, and the cross-sectional areas of phase-change films and lower electrodes to be reduced in the direction of ...  
WO/2015/130455A1
The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same, in one aspect, a method of fabricating cross-point memory arrays comprises for...  
WO/2015/126906A1
A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM cell, may include forming a plurality of bottom electrode connections (302), depositing a bottom electrode layer (310) over the bottom electrode connections, performing ...  
WO/2015/125291A1
This storage device is characterized in that: the storage device has disposed therein two or more columns and two or more rows of storage elements, which respectively have columnar phase change layers (176a-176d), reset gate insulating f...  
WO/2015/126875A1
A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM cell, may include: forming a plurality of bottom electrode connections, depositing a bottom electrode layer over the bottom electrode connections, performing a first etc...  
WO/2015/126870A1
A method of forming a resistive memory cell (140), e.g., a CBRAM or ReRAM, includes forming a bottom electrode layer (102A), forming an oxide region (110) of an exposed area of the bottom electrode, removing a region of the bottom electr...  
WO/2015/126861A1
A method of forming a resistive memory cell (140), e.g., a CBRAM or ReRAM, may include forming a bottom electrode layer (102), oxidizing an exposed region of the bottom electrode layer to form an oxide region (110), removing a region of ...  
WO/2015/125449A1
[Problem] To provide a low-cost variable-resistance element and a method for producing same. [Solution] The variable-resistance element (1) in one embodiment of the present invention is equipped with a bottom electrode layer (3), a top e...  
WO/2015/122159A1
[Problem] To provide a method for forming a carbon electrode film, the method being capable of reducing surface roughness and resistivity to or below specified values. [Solution] The method for forming a carbon electrode film according t...  
WO/2015/107945A1
In one embodiment of the present invention, a switch element is provided with a first electrode, a second electrode disposed so as to face the first electrode, and a switch layer which is provided between the first electrode and second e...  
WO/2015/096644A1
Provided in embodiments of the present invention is a metal-doped germanium telluride-based resistive switching memory material, which has a molecular formula of MxGeyTez, where 0 < x ≤ 20, 35 ≤ y ≤ 55, z = 100 − x − y, and M i...  
WO/2015/100066A1
Provided are resistive random access memory (ReRAM) cells having Schottky barriers and methods of fabricating such ReRAM cells. Specifically, a ReRAM cell includes two Schottky barriers, one barrier limiting an electrical current through...  
WO/2015/078120A1
Disclosed is a resistive memory, the structure thereof from bottom to top comprising: a substrate, an insulating layer, a bottom electrode, a thin film of resistive material and a top electrode. The resistive memory is characterized in t...  
WO/2015/072228A1
[Solution] A spin electronic memory of the present invention is characterized by being formed by laminating at least a pair of electrodes (1, 2), a first alloy layer (5) that is mainly composed of SbTe, Sb2Te3, BiTe, Bi2Te3, BiSe or Bi2S...  
WO/2015/071982A1
This storage device has: a columnar insulating material layer (180); a film (189), which is formed around an upper portion of the columnar insulating material layer, and in which resistance changes; a lower electrode (184), which is form...  
WO/2015/068651A1
Provided is a nonvolatile three-terminal element operated by controlling the band gap of the electron state of a graphene material. A hydrogen ion-conducting or oxygen ion-conducting ion conductor (5) is disposed between graphene oxide o...  
WO/2015/069524A1
Vertical 1 T-l R memory cells, memory arrays of vertical 1 T-1 R memory calls, and methods of forming such memory cells and memory arrays are described. The memory cells each include a vertical transistor (T) and a resistivity-switching ...  
WO/2015/059819A1
Provided is a small-area nonvolatile semiconductor storage device that constitutes one transistor/cell type memory using surrounding gate transistors (SGTs), i.e., vertical transistors. Disclosed is memory having data stored therein by c...  
WO/2015/049347A1
This circuit (40) comprises a random network (30), said random network, comprising: nodes, each node being constituted by a pad forming an electrical contact carried on a face of a substrate (10); and links between nodes, each link being...  
WO/2015/049772A1
This storage device has films (189, 190, 191, 192) that are formed around top sections of columnar insulator layers (180, 181, 182, 183) and change in resistance and bottom electrodes (184, 185, 186, 187) that are formed around bottom se...  
WO/2015/040927A1
 Provided is a non-volatile memory device provided with: a first conductive layer (12a); a second conductive layer (14a); a ferroelectric film (16a) provided between the first conductive layer and the second conductive layer; and a p...  
WO/2015/034756A1
Methods for reducing location-based variations in the switching characteristics of memory cells within a memory array are described. In some cases, the resistance of an embedded resistor within each memory cell may be set to reduce the o...  
WO/2015/016861A3
Provided herein are embodiments relating to metal-insulator-metal diodes and their method of manufacture. In some embodiments, the metal-insulator-metal diodes can be made, in part, via the use of an evanescent wave on a photo resist. In...  

Matches 301 - 350 out of 6,156