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Matches 351 - 400 out of 6,246

Document Document Title
WO/2015/182074A1
The semiconductor device according to the present invention has an upper electrode, a first lower layer wiring that also functions as a lower electrode, an electrical resistance-changing film interposed between the upper electrode and th...  
WO/2015/177972A1
Various embodiments of the present invention are directed to a method for passivating a metal line (300, 301, 302, 310), e.g. a memory cell and a source line of a CBRAM, prior to removing a masking layer (106) in order to prevent oxidati...  
WO/2015/177971A1
Exemplary embodiments of the present invention are directed towards a method for fabricating a semiconductor memory device comprising selectively depositing a material to form a cap (300) above a recessed cell structure (202) in order to...  
WO/2015/169142A1
A multi-valued phase change storage unit comprises phase change material layers (104, 105), heating electrodes (103, 106), a top electrode (101), a bottom electrode (107) and a thermal insulation material layer (102). The phase change ma...  
WO/2015/167357A1
A device is disclosed which comprises a first electrode (101), a second electrode (104) spaced from the first electrode, a switching region (102) positioned between the first electrode and the second electrode, and an intermediate region...  
WO/2015/165088A1
A phase change memory comprises a storage node. The storage node comprises: a lower electrode (1), used for being connected to a substrate; a first phase-change layer (2), located on the lower electrode; a second phase-change layer (2), ...  
WO/2015/167351A1
A device is disclosed which comprises a first electrode (101) and a second electrode (104) spaced from the first electrode, a switching region (102) positioned between the first electrode and the second electrode, and an intermediate reg...  
WO/2015/146311A1
An Al-Te-Cu-Zr alloy sputtering target characterized by comprising 20 to 40 at% of Te, 5 to 20 at% of Cu, 5 to 15 at% of Zr and a remainder made up by Al, wherein a Te phase, a Cu phase and a CuTe phase do not exist in the target structu...  
WO/2015/145746A1
 Provided are a method for vapor-phase growth of a phase-change thin film, and a device for vapor-phase growth of a phase-change thin film, with which a phase-change thin film is formed at low temperature while retained in an amorphous...  
WO/2015/137256A1
Provided is a transistor equipped with: a piezoresistor (10) through which a carrier is conducted; a source (14) which injects the carrier into the piezoresistor; a drain (16) which receives the carrier from the piezoresistor; a piezoele...  
WO/2015/139033A1
Systems, methods, and apparatus are provided for tuning a functional property of a device. The device (210) includes a layer of a dielectric material (214) disposed over and forming an interface (216) with a layer of an electrically cond...  
WO/2015/133073A1
Provided is a nonvolatile switching element which has high retention ability even if programmed at a low current, while being suppressed in dielectric breakdown of a variable resistance layer during a reset operation. This switching elem...  
WO/2015/129413A1
 In this method of oxidizing treatment of a transition metal film for oxidizing a film containing a transition metal on the surface of an object to be treated, plasma of gas containing at least oxygen is generated, electrons are donate...  
WO/2015/129021A1
Provided are a structure and a manufacturing method for a storage device that allow resetting to be performed using a reset gate, and the cross-sectional areas of phase-change films and lower electrodes to be reduced in the direction of ...  
WO/2015/130455A1
The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same, in one aspect, a method of fabricating cross-point memory arrays comprises for...  
WO/2015/126906A1
A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM cell, may include forming a plurality of bottom electrode connections (302), depositing a bottom electrode layer (310) over the bottom electrode connections, performing ...  
WO/2015/125291A1
This storage device is characterized in that: the storage device has disposed therein two or more columns and two or more rows of storage elements, which respectively have columnar phase change layers (176a-176d), reset gate insulating f...  
WO/2015/126875A1
A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM cell, may include: forming a plurality of bottom electrode connections, depositing a bottom electrode layer over the bottom electrode connections, performing a first etc...  
WO/2015/126870A1
A method of forming a resistive memory cell (140), e.g., a CBRAM or ReRAM, includes forming a bottom electrode layer (102A), forming an oxide region (110) of an exposed area of the bottom electrode, removing a region of the bottom electr...  
WO/2015/126861A1
A method of forming a resistive memory cell (140), e.g., a CBRAM or ReRAM, may include forming a bottom electrode layer (102), oxidizing an exposed region of the bottom electrode layer to form an oxide region (110), removing a region of ...  
WO/2015/125449A1
[Problem] To provide a low-cost variable-resistance element and a method for producing same. [Solution] The variable-resistance element (1) in one embodiment of the present invention is equipped with a bottom electrode layer (3), a top e...  
WO/2015/122159A1
[Problem] To provide a method for forming a carbon electrode film, the method being capable of reducing surface roughness and resistivity to or below specified values. [Solution] The method for forming a carbon electrode film according t...  
WO/2011/085054A3
A nonvolatile memory cell including a storage element in series with a diode steering element. At least one interface of the diode steering element is passivated.  
WO/2015/107945A1
In one embodiment of the present invention, a switch element is provided with a first electrode, a second electrode disposed so as to face the first electrode, and a switch layer which is provided between the first electrode and second e...  
WO/2015/016861A3
Provided herein are embodiments relating to metal-insulator-metal diodes and their method of manufacture. In some embodiments, the metal-insulator-metal diodes can be made, in part, via the use of an evanescent wave on a photo resist. In...  
WO/2015/096644A1
Provided in embodiments of the present invention is a metal-doped germanium telluride-based resistive switching memory material, which has a molecular formula of MxGeyTez, where 0 < x ≤ 20, 35 ≤ y ≤ 55, z = 100 − x − y, and M i...  
WO/2015/100066A1
Provided are resistive random access memory (ReRAM) cells having Schottky barriers and methods of fabricating such ReRAM cells. Specifically, a ReRAM cell includes two Schottky barriers, one barrier limiting an electrical current through...  
WO/2015/078120A1
Disclosed is a resistive memory, the structure thereof from bottom to top comprising: a substrate, an insulating layer, a bottom electrode, a thin film of resistive material and a top electrode. The resistive memory is characterized in t...  
WO/2015/072228A1
[Solution] A spin electronic memory of the present invention is characterized by being formed by laminating at least a pair of electrodes (1, 2), a first alloy layer (5) that is mainly composed of SbTe, Sb2Te3, BiTe, Bi2Te3, BiSe or Bi2S...  
WO/2015/071982A1
This storage device has: a columnar insulating material layer (180); a film (189), which is formed around an upper portion of the columnar insulating material layer, and in which resistance changes; a lower electrode (184), which is form...  
WO/2015/068651A1
Provided is a nonvolatile three-terminal element operated by controlling the band gap of the electron state of a graphene material. A hydrogen ion-conducting or oxygen ion-conducting ion conductor (5) is disposed between graphene oxide o...  
WO/2015/069524A1
Vertical 1 T-l R memory cells, memory arrays of vertical 1 T-1 R memory calls, and methods of forming such memory cells and memory arrays are described. The memory cells each include a vertical transistor (T) and a resistivity-switching ...  
WO/2015/059819A1
Provided is a small-area nonvolatile semiconductor storage device that constitutes one transistor/cell type memory using surrounding gate transistors (SGTs), i.e., vertical transistors. Disclosed is memory having data stored therein by c...  
WO/2015/049347A1
This circuit (40) comprises a random network (30), said random network, comprising: nodes, each node being constituted by a pad forming an electrical contact carried on a face of a substrate (10); and links between nodes, each link being...  
WO/2015/049772A1
This storage device has films (189, 190, 191, 192) that are formed around top sections of columnar insulator layers (180, 181, 182, 183) and change in resistance and bottom electrodes (184, 185, 186, 187) that are formed around bottom se...  
WO/2015/040927A1
 Provided is a non-volatile memory device provided with: a first conductive layer (12a); a second conductive layer (14a); a ferroelectric film (16a) provided between the first conductive layer and the second conductive layer; and a p...  
WO/2015/034756A1
Methods for reducing location-based variations in the switching characteristics of memory cells within a memory array are described. In some cases, the resistance of an embedded resistor within each memory cell may be set to reduce the o...  
WO/2015/007108A1
Provided are a phase change memory unit and a preparation method therefor. A phase change material layer with the thickness equivalent to the size of a single unit cell is used, so that a phase change material basically reflects an inter...  
WO/2015/002206A1
A semiconductor device of an embodiment of the present invention is provided with the following: a first electrically conductive layer; a second electrically conductive layer; and a ferrodielectric film or ferridielectric film of hafnium...  
WO/2014/208050A1
In order to provide a switching element having excellent operational stability and a high production yield, and a semiconductor device using the switching element, this switching element has: a non-volatile variable resistance element, w...  
WO/2014/193561A1
A nonvolatile resistive memory element includes a novel switching layer and methods of forming the same. The switching layer includes a material having bistable resistance properties and formed by bonding silicon to oxygen or nitrogen. T...  
WO/2014/190892A1
An Al-W-O stack structure applicable to a resistive random access memory according to an embodiment of the invention comprises a tungsten top electrode, a tungsten oxide layer formed on the tungsten lower electrode, an aluminum oxide lay...  
WO/2014/137652A3
A 3D memory array having a vertically oriented thin film transistor (TFT) selection device that has a channel extension, otherwise referred to as a gate/junction offset, is disclosed. The vertically oriented TFT selection device with cha...  
WO/2014/181492A1
The present invention applies to a semiconductor device having a plurality of cells arranged in a two-dimensional array. In the present invention, each cell (10) is provided with one or more transistors (101, 111), one or more resistance...  
WO/2014/170023A1
The resistive-switching memory element of the present invention comprises a first electrode, a resistive-switching element; and a second electrode wherein the resistive-switching element is arranged between the first electrode and the se...  
WO/2014/164015A1
A sidewall-type memory cell (e.g., a CBRAM, ReRAM, or PCM cell) may include a bottom electrode (120), a top electrode (132) layer defining a sidewall, and an electrolyte layer (130) arranged between the bottom and top electrode layers, s...  
WO/2014/164268A1
A voltage-controlled resistor is provided. The resistor structure includes first and second resistive elements each including a phase change material that changes resistance in response to a change in temperature of the phase change mate...  
WO/2014/164378A1
A resistive memory cell of CBRAM or ReRAM type includes a top electrode (222) and a trench-shaped bottom electrode structure defining a bottom electrode connection (200) and a sidewall (210) extending from a first sidewall region (214) a...  
WO/2014/163994A1
In some aspects, a memory cell is provided that includes a first conducting layer (18), a reversible resistance switching element (12) above the first conducting layer, a second conducting layer (16) above the reversible resistance switc...  
WO/2014/159629A1
Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. A stack including a defect source layer, a defect blocking layer, and a defect acceptor layer disposed between the defect source layer and the ...  

Matches 351 - 400 out of 6,246