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WO/2019/009296A1 |
[Problem] To stabilize the transition of a resistance variable element from a low resistance state to a high resistance state. [Solution] This switch element includes a resistance variable element, a first transistor, and a second transi...
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WO/2019/009877A1 |
A phase change memory structure (100) can include a memory cell, a dielectric material (130) adjacent to the memory cell, and a bit line. The memory cell can include a phase change material layer (110) and a top electrode layer (120) abo...
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WO/2019/009876A1 |
A phase change memory structure (100) includes a phase change material layer (110), a top electrode layer (120) above the phase change material layer, a metal silicon nitride layer (130) in contact with the top electrode layer opposite f...
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WO/2019/005113A1 |
Techniques are disclosed for forming resistive random-access memory (RRAM) including a tunnel source access transistor, such as a tunnel source MOSFET. The use of a tunnel source access transistor includes integrating a tunnel diode on t...
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WO/2019/005468A1 |
The present disclosure includes memory cells having resistors, and methods of forming the same. An example method includes forming a first conductive line, forming a second conductive line, and forming a memory element between the first ...
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WO/2019/005167A1 |
An approach for integrating a resistive random access memory (RRAM) device on a dual bottom electrode layer is described. In an example, a resistive random access memory (RRAM) device includes a dual bottom electrode disposed above a sub...
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WO/2019/005168A1 |
A memory device includes a wordline disposed above a substrate and a selector element disposed above the wordline, where the selector element includes a phase change material. The memory device further includes a bipolar memory element d...
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WO/2018/236360A1 |
Phase field effect transistors (Phase FETs) having ferroelectric gate dielectrics are described. In an example, an integrated circuit structure includes a channel layer above a substrate. The channel layer is composed of a material havin...
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WO/2018/236432A1 |
A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first directi...
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WO/2018/236356A1 |
Ferroelectric field effect transistors (FeFETs) having compound semiconductor channels are described. In an example, an integrated circuit structure includes a semiconductor channel layer above a substrate. The semiconductor channel laye...
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WO/2018/231210A1 |
Described herein are two approaches for providing thin film ferroelectric materials. The first approach is based on using a templating layer in contact with a ferroelectric layer, the material of the templating layer being such that it i...
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WO/2018/231296A1 |
A method is provided that includes forming a word line above a substrate, forming a bit line above the substrate, forming a nonvolatile memory material between the word line and the bit line, the nonvolatile memory material including a s...
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WO/2018/223801A1 |
Disclosed are a resistive device and a manufacturing method therefor, a manufacturing method for a display substrate, and a display apparatus, wherein same belong to the field of electronic manufacturing. The manufacturing method for a r...
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WO/2018/225993A1 |
According to an embodiment, a phase-change memory device comprises: an upper electrode and a lower electrode; a phase-change layer in which a crystal state thereof is changed by heat supplied by the upper electrode and the lower electrod...
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WO/2018/220356A1 |
The present techniques generally relate to fabrication of correlated electron materials (CEMs) devices used, for example, to read from a resistive memory element or to write to a resistive memory element. In embodiments, by limiting curr...
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WO/2018/222237A1 |
A method is provided that includes forming a word line above a substrate, forming a bit line above the substrate, forming a nonvolatile memory material between the word line and the bit line, and forming a memory cell including the nonvo...
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WO/2018/221114A1 |
A memory device according to an embodiment of the present disclosure comprises a logic circuit in which a plurality of wiring layers including layers that have different wiring pitches are laminated, and a memory element provided between...
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WO/2018/214142A1 |
A resistive memory device, and manufacturing method thereof. The resistive memory device comprises: a lower electrode (101); an oxide layer (102) containing the metal of the lower electrode and located on the lower electrode (101); a res...
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WO/2018/213208A1 |
A semiconductor power conversion device includes a plurality of device cells in different portions of the active area, each including a respective gate electrode. The device includes a gate pad having a plurality of integrated resistors,...
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WO/2018/207831A1 |
In order to output two potential values of a power supply voltage and a ground voltage and provide a reconfigurable logic integrated circuit having a small circuit area, this programmable logic circuit is provided with: a first switch; a...
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WO/2018/205915A1 |
Disclosed by the present invention is a VOx gating tube-based phase change storage unit, comprising a lower electrode layer, a VOx gating layer, a phase change function layer and an upper electrode layer. The present invention uses VOx t...
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WO/2018/207972A1 |
The present invention relates to a transparent and flexible resistive switching memory to which a transparent electrode having an OMO structure is applied, and a method for manufacturing the same. In addition, the present invention may c...
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WO/2018/203459A1 |
A selective element according to one embodiment of the present disclosure is provided with: a first electrode; a second electrode disposed opposite to the first electrode; a semiconductor layer that is provided between the first electrod...
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WO/2018/193759A1 |
[Problem] To produce a variable resistance element having excellent electrical characteristics at low cost. [Solution] A method for producing a variable resistance element according to the present invention comprises the formation of a f...
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WO/2018/190241A1 |
A crossbar switch using a variable-resistance element corresponding to multiple fan-out, wherein in order to enable switch operation at high speed with high reliability, a switch circuit is used having: a plurality of four-terminal switc...
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WO/2018/190071A1 |
A storage device according to one embodiment of the present disclosure is provided with: a plurality of first wiring layers which extend in one direction; a plurality of second wiring layers which extend in another direction; and a plura...
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WO/2018/186166A1 |
Memory structures with a plurality of memory cells that each include a memory device in combination with a switch device are provided. The memory device and switch device of each cell are connected in series, and include at least first a...
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WO/2018/186940A1 |
First electrically conductive lines (134) are formed over a substrate (10). A two-dimensional array of vertical stacks (180) is formed, each of which includes a first electrode (212), an in-process resistive memory material portion (214)...
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WO/2018/186997A1 |
The present disclosure includes three dimensional memory arrays, and methods of processing the same. A number of embodiments include a plurality of conductive lines separated from one other by an insulation material, a plurality of condu...
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WO/2018/182649A1 |
A resistive random access memory (RRAM) device includes a bottom electrode disposed above a substrate, a top electrode disposed above the bottom electrode, an oxygen exchange layer disposed between the bottom electrode and the top electr...
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WO/2018/182742A1 |
An apparatus is described. The apparatus includes a computation unit. The computation unit includes stacked, resistive elements. Each of the resistive elements is coupled to its own respective input node. Each of the resistive elements i...
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WO/2018/182799A1 |
A method is provided that includes forming a bit line above a substrate; forming a word line above the substrate, and forming a non-volatile memory cell between the bit line and the word line. The non-volatile memory cell includes a non-...
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WO/2018/181019A1 |
The present invention provides a resistance change element that improves set voltage variation between elements. Provided is a semiconductor device that includes at least two resistance change elements, a first terminal, and a second ter...
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WO/2018/181921A1 |
The present invention enables improvement of a set-forming yield while preventing insulation breakdown of a rectifying element when being set. In a plurality of switching cells, terminals on one side of two variable resistance elements a...
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WO/2018/180536A1 |
The purpose of the present invention is to provide a circuit capable of reducing leakage power in a programmable logic circuit using resistance change elements. To this end, the present invention is a programmable logic integrated circui...
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WO/2018/180759A1 |
This time change element includes a time change phase transition material for which the phase transition between solids progresses with the passage of time after manufacturing, irrespective of whether there is stimulus from outside, the ...
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WO/2018/182678A1 |
Resistive switch devices including a thermal layer and processes for forming the devices are provided. The thermal layer can be thermally resistive layer and electrically insulating. As such, the thermal layer can be arranged to cap or o...
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WO/2018/180228A1 |
A memory device according to an embodiment of the present disclosure comprises a memory cell array which is configured such that, when, of a plurality of memory cells, a plurality of first memory cells of which corresponding fourth wires...
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WO/2018/178720A1 |
A switching resistor has a low resistance state and a high resistance state. The switching resistor comprises a dielectric layer disposed between a first electrode and a second electrode. The switching resistor further comprises a textur...
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WO/2018/182680A1 |
Resistive switch devices including a thermal layer and processes for forming the devices are provided. The thermal layer can be thermally resistive layer and electrically conductive. As such, the thermal layer can be intercalated between...
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WO/2018/174514A1 |
Provided is a nonvolatile memory element characterized by having multilevel resistance and capacitance values. The nonvolatile memory element comprises: a substrate; a first electrode positioned on the substrate; a dielectric material la...
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WO/2018/169269A1 |
An oxide-based resistive switching memory element using a single nanopore structure and a manufacturing method therefor are disclosed. The resistive switching memory element manufacturing method comprises: a lower electrode layer forming...
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WO/2018/164856A1 |
Switches for electromagnetic radiation, including radiofrequency switches and optical switches, are provided. Also provided are methods of using the switches. The switches incorporate layers of high quality VO2 that are composed of a plu...
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WO/2018/164745A1 |
A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first directi...
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WO/2018/160732A1 |
Systems, devices, and related methods are disclosed for electromechanical transfer printing of 2D materials disposed on one substrate to another. The printing device can be configured to transfer a 2D material from a source substrate to ...
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WO/2018/152697A1 |
A preparation method for a selector based on a transition metal oxide and a selector prepared by the method. The preparation method comprises: S1, forming a tungsten plug on a transistor; S2, using the tungsten plug as a lower electrode,...
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WO/2018/151987A1 |
Methods, systems, and apparatus that support efficient utilization of die area for crosspoint memory architecture are described. A memory array may include active memory cells overlying each portion of the substrate that includes certain...
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WO/2018/144457A1 |
Methods for scaling dimensions of resistive change elements, resistive change element arrays of scalable resistive change elements, and sealed resistive change elements are disclosed. According to some aspects of the present disclosure t...
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WO/2018/143611A1 |
The present invention relates to a method for manufacturing a large-area metal chalcogenide thin film and a device comprising the large-area metal chalcogenide thin film manufactured thereby, the method comprising the steps of: preparing...
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WO/2018/138482A1 |
The present techniques generally relate to fabrication of correlated electron materials used, for example, to perform specified application performance parameters 277-283. In embodiments, CEM devices fabricated at a first stage of a wafe...
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