| Document |
Document Title |
|
WO/2019/146268A1 |
A storage element according to an embodiment of the present disclosure is provided with: a first electrode; a second electrode disposed opposite the first electrode; and a storage layer which is disposed between the first electrode and t...
|
|
WO/2019/146534A1 |
In order to provide a logic integrated circuit having a reduced chip area, the present invention provides a logic integrated circuit comprising a switch cell array that has: a plurality of first wirings extending in a first direction; a ...
|
|
WO/2019/132997A1 |
Described herein are systems, methods, and apparatuses for using negative differential resistance (NDR) materials in circuits to store memory states for memory devices. In an embodiment, such NDR materials can have a voltage dependent vo...
|
|
WO/2019/132888A1 |
Provided herein are structures, including memory structures, and methods of forming structures. The memory structures may include selectors and memory elements. The memory elements may include a material that can change resistance. The s...
|
|
WO/2019/132994A1 |
In an embodiment, described herein are systems, methods, and apparatuses directed towards segmentation of a large cross-point memory a memory array (or tile) into two or more memory arrays (sub-tiles) of smaller size for use as an embedd...
|
|
WO/2019/132995A1 |
Disclosed herein are systems, methods, and apparatuses that are directed to a selector for use in connection with memory devices. In an embodiment, the selector can comprise a device that has current-voltage characteristics that are symm...
|
|
WO/2019/133117A1 |
A semiconductor device assembly is provided. The assembly comprises a package substrate, a first stack of semiconductor dies having a first set of planform dimensions disposed over a first location on the substrate, a second stack of sem...
|
|
WO/2019/125392A1 |
Integrated circuit structures are provided that may include a first insulating-to-metallic transition material, a second insulating-to-metallic transition material, and a third layer. The third layer may have an electron affinity that is...
|
|
WO/2019/125994A1 |
One aspect of the invention relates to a multi-terminal memtransistor. The memtransistor includes a substrate having a first surface and an opposite, second surface, a polycrystalline monolayer film formed of an atomically thin material ...
|
|
WO/2019/121796A1 |
An aspect of the invention is a memory according to the preceding claim (CO) comprising a plurality of first electrodes (EP), referred to as flat electrodes (EP), each flat electrode (EP) of the plurality of flat electrodes (EP) defining...
|
|
WO/2019/118931A1 |
Three-dimensional vertical memory array cell structures and processes. In an exemplary embodiment, a 3D vertical memory array structure is formed by performing operations that include forming an array stack having alternating metal layer...
|
|
WO/2019/097341A1 |
A method is presented for forming a semiconductor device. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form a plurality of trenches for receiving a first conducting ma...
|
|
WO/2019/087050A1 |
A liner is deposited conformally to a pore within a first dielectric material of a semiconductor device. The pore extends through the first dielectric material to a top surface of a first metal electrode. The liner is etched such that th...
|
|
WO/2019/078367A1 |
Provided is a memristor which can be manufactured at low temperature and does not include metals that could potentially dry up as a resource. The memristor 1 is provided with: a first electrode 2; a second electrode 3; and an oxide memri...
|
|
WO/2019/066829A1 |
An integrated circuit structure includes a stack of alternating first conductive layers and insulator layers. A plurality of etch pits are through the first conductive layers. A plurality of selectors are in the etch pits adjacent to the...
|
|
WO/2019/062198A1 |
A gate tube device and a preparation method therefor, applied to the technical field of gate tube devices. The gate tube device comprises a first metal electrode layer (1, 9), a second metal electrode layer (4, 12), and a switch layer. T...
|
|
WO/2019/008328A3 |
The present techniques relate to a method for the manufacture of a CEM device comprising forming a thin film of a correlated electron material having a predetermined electrical impedance when the CEM device in its relatively conductive (...
|
|
WO/2019/066894A1 |
Embedded non-volatile memory structures having an independently sized selector element and memory element are described. In an example, a memory device includes a metal layer. A selector element is above the metal layer. A memory element...
|
|
WO/2019/066898A1 |
An integrated circuit comprising a self-aligned embedded phase change memory cell is described. In an example, the integrated circuit includes a bottom electrode. A conductive line is above the bottom electrode along a first direction ab...
|
|
WO/2019/066826A1 |
Embedded non-volatile memory structures having asymmetric selector elements are described. In an example, a memory device includes a word line. An asymmetric selector element is above the word line. The asymmetric selector element includ...
|
|
WO/2019/068094A1 |
A self-aligned memory device includes a conductive bottom plug disposed within an insulating layer and having a coplanar top surface, a self-aligned planar bottom electrode disposed upon the coplanar top surface and having a thickness wi...
|
|
WO/2019/066851A1 |
An apparatus, includes an interconnect, including a conductive material, above a substrate and a resistive random access memory (RRAM) device coupled to the interconnect. The RRAM device includes an electrode structure above the intercon...
|
|
WO/2019/066996A1 |
A memory device includes a first electrode, a non-volatile memory element having a first terminal and a second terminal, where the first terminal is coupled to the first electrode. The memory device further includes a selector having a f...
|
|
WO/2019/063926A1 |
Proposed is a method of producing a recurrent neural network computer, which method comprises consecutive steps of providing a substrate comprising a first electrode; structuring the first electrode by etching using a first mask made of ...
|
|
WO/2019/066828A1 |
Embedded non-volatile memory structures having double selector elements are described. In an example, a memory device includes a word line. A double selector element is above the word line. The double selector element includes a first se...
|
|
WO/2019/066769A1 |
Disclosed herein are selector devices, and related devices and techniques. In some embodiments, a selector device may include a first electrode, a second electrode, a selector material between the first electrode and the second electrode...
|
|
WO/2019/066849A1 |
A memory device includes a bottom electrode above a substrate, a first switching layer on the bottom electrode, a second switching layer including aluminum on the first switching layer, an oxygen exchange layer on the second switching la...
|
|
WO/2019/059892A1 |
Disclosed are electronic devices, memory devices, and computing devices including a metallic glass barrier material for an electrode or a contact. An electronic device (100) includes a semiconductor substrate (110), an electrical compone...
|
|
WO/2019/059894A1 |
Multi-channel vertical transistors for embedded non-volatile memory are described. In an example, a memory array includes a plurality of non-volatile random access memory (RAM) elements. The memory array also includes a plurality of tran...
|
|
WO/2019/059118A1 |
The present invention provides a programmable logic integrated circuit with which it is possible to reduce leakage current while inhibiting increase in the number of connection wires and a consequent increase in occupied area. This logic...
|
|
WO/2019/055008A1 |
Disclosed herein are selector devices and related devices and techniques. In some embodiments, a selector device may include a first electrode, a second electrode, and a selector material between the first electrode and the second electr...
|
|
WO/2019/055003A1 |
Embedded non-volatile memory structures having selector elements with ballast are described. In an example, a memory device includes a word line. A selector element is above the word line. The selector element includes a selector materia...
|
|
WO/2019/055052A1 |
Approaches for fabricating RRAM stacks with reduced forming voltage, and the resulting structures and devices, are described. In an example, a resistive random access memory (RRAM) device includes a conductive interconnect in an inter-la...
|
|
WO/2019/049980A1 |
In order to achieve both high-density implementation of applications in the form a reconfiguration circuit without a redundancy bit and the capability to continuously run applications with redundancy, the present invention is a reconfigu...
|
|
WO/2019/050579A1 |
A method of forming a resistive memory device includes forming an alternating stack of insulating layers and sacrificial material layers that extend along a first horizontal direction over a substrate, forming a laterally alternating seq...
|
|
WO/2019/046030A1 |
In an example, a memory array may include a plurality of first dielectric materials and a plurality of stacks, where each respective first dielectric material and each respective stack alternate, and where each respective stack comprises...
|
|
WO/2019/045808A1 |
An alternating stack of insulating layers and electrically conductive layers is formed over a substrate. Sidewalls of the electrically conductive layers are laterally recessed to form laterally recessed regions. After formation of a conf...
|
|
WO/2019/043206A1 |
The disclosed device comprises a thin film layer (4) of a phase transition material disposed over a substrate (2), and a confinement layer (3) adjacent to the thin film layer. The thin film layer has first and second in-plane lattice par...
|
|
WO/2019/032166A1 |
The disclosed two-dimensional array of vertical field effect transistors (200A) includes a one-dimensional array of ladder-shaped gate electrode lines (52), each including a pair of rail portions (522) that extend laterally along a first...
|
|
WO/2019/022860A1 |
A vanadium dioxide (VO2)-based threshold switch device exhibiting current-controlled negative differential resistance (S-type NDR), an electrical oscillator circuit based on the threshold switch device, a wafer including a plurality of s...
|
|
WO/2019/016539A1 |
A switching resistor comprises a dielectric layer disposed between a first electrode layer and a second electrode layer, the switching resistor having a high resistance state and a low resistance state. The switching resistor is responsi...
|
|
WO/2019/008339A3 |
Subject matter disclosed herein may relate to construction of a correlated electron material (CEM) device. In particular embodiments, after formation of a film comprising layers of a transition metal oxide (TMO) material and a dopant, at...
|
|
WO/2019/009296A1 |
[Problem] To stabilize the transition of a resistance variable element from a low resistance state to a high resistance state. [Solution] This switch element includes a resistance variable element, a first transistor, and a second transi...
|
|
WO/2019/009877A1 |
A phase change memory structure (100) can include a memory cell, a dielectric material (130) adjacent to the memory cell, and a bit line. The memory cell can include a phase change material layer (110) and a top electrode layer (120) abo...
|
|
WO/2019/009876A1 |
A phase change memory structure (100) includes a phase change material layer (110), a top electrode layer (120) above the phase change material layer, a metal silicon nitride layer (130) in contact with the top electrode layer opposite f...
|
|
WO/2019/005113A1 |
Techniques are disclosed for forming resistive random-access memory (RRAM) including a tunnel source access transistor, such as a tunnel source MOSFET. The use of a tunnel source access transistor includes integrating a tunnel diode on t...
|
|
WO/2019/005468A1 |
The present disclosure includes memory cells having resistors, and methods of forming the same. An example method includes forming a first conductive line, forming a second conductive line, and forming a memory element between the first ...
|
|
WO/2019/005167A1 |
An approach for integrating a resistive random access memory (RRAM) device on a dual bottom electrode layer is described. In an example, a resistive random access memory (RRAM) device includes a dual bottom electrode disposed above a sub...
|
|
WO/2019/005168A1 |
A memory device includes a wordline disposed above a substrate and a selector element disposed above the wordline, where the selector element includes a phase change material. The memory device further includes a bipolar memory element d...
|
|
WO/2018/236360A1 |
Phase field effect transistors (Phase FETs) having ferroelectric gate dielectrics are described. In an example, an integrated circuit structure includes a channel layer above a substrate. The channel layer is composed of a material havin...
|
