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WO/2018/066320A1 |
A switch element according to one embodiment of the present disclosure is provided with a first electrode, a second electrode that is arranged to face the first electrode, and a switch layer that is disposed between the first electrode a...
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WO/2018/063287A1 |
Substrates, assemblies, and techniques for enabling a resistive random access memory cell are disclosed herein. For example, in some embodiments, a device may include a top electrode, a modulated interfacial region, and a bottom electrod...
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WO/2018/063265A1 |
Substrates, assemblies, and techniques for enabling a dual pedestal for resistive random access memory are disclosed herein. For example, in some embodiments, a device may include a substrate, wherein the substrate includes a fill metal,...
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WO/2018/063320A1 |
Conductive bridge random access memory (CBRAM) devices with low thermal conductivity electrolyte sublayers are described. In an example, a conductive bridge random access memory (CBRAM) device includes a conductive interconnect disposed ...
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WO/2018/060692A1 |
The present techniques generally relate to correlated electron switch devices, and may relate more particularly to voltage detection with correlated electron switch devices.
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WO/2018/063093A1 |
According to embodiments of the present invention, a memory device is provided. The memory device includes an electrochemical metallization memory (ECM) cell and a valence change memory (VCM) cell arranged one over the other. According t...
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WO/2018/063209A1 |
Substrates, assemblies, and techniques for enabling a resistive random access memory cell are disclosed herein. For example, in some embodiments, a device may include a source, where the source includes a source junction, a gate, and a d...
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WO/2018/063370A1 |
An apparatus is described. The apparatus includes a semiconductor chip that includes logic circuitry, embedded dynamic random access memory (DRAM) cells and embedded resistive random access memory (RRAM) cells.
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WO/2018/060656A1 |
The invention relates to a supercapacitor comprising: an electrolyte having a first end and a second end opposite the first end; a first electrode (E1) in contact with the first end of the electrolyte; and a second electrode (E2) in cont...
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WO/2018/063322A1 |
Spacer-based patterning for tight-pitch and low-variability random access memory (RAM) bit cells, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate having a top layer. An array of ...
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WO/2018/063164A1 |
Embodiments include a resistive random access memory (RRAM) memory cell which is the same as a RRAM storage cell. The RRAM storage cell has a resistive material layer and a semiconductor layer between two electrodes, where the semiconduc...
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WO/2018/063207A1 |
Substrates, assemblies, and techniques for enabling a resistive random access memory cell are disclosed herein. For example, in some embodiments, a device may include a source junction, a gate, a drain junction, a semiconductor located b...
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WO/2018/057022A1 |
Disclosed herein are metal filament memory devices (MFMDs), and related devices a techniques. In some embodiments, an MFMD may include: an electrode including an electrochemically active metal; an electrolyte; and a barrier material disp...
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WO/2018/057021A1 |
Disclosed herein are metal filament memory cells, and related devices and techniques. In some embodiments, a memory cell may include: a transistor having a source/drain region; and a metal filament memory device including an active metal...
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WO/2018/055346A1 |
The presently disclosed techniques relate to devices and methods of their manufacture, comprising either a first metal layer Mn, a substrate formed thereon with a cavity exposing a portion of the metal layer, and a correlated electron ma...
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WO/2018/057012A1 |
Embodiments include a threshold switching selector. The threshold switching selector may include a threshold switching layer and a semiconductor layer between two electrodes. A memory cell may include the threshold switching selector cou...
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WO/2018/054683A1 |
The present invention is notably directed to display device (1, 1a d), comprising a set of pixels, each having a layer structure (2, 2c, 2d) that includes: a bi-stable, phase change material (10), or bi-stable PCM, having at least two re...
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WO/2018/056963A1 |
Conductive bridge random access memory (CBRAM) devices with graded conductivity electrolyte layers are described. In an example, a conductive bridge random access memory (CBRAM) device includes a conductive interconnect disposed in an in...
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WO/2018/051062A2 |
The present techniques relate to a method for the manufacture of a switching device comprising a silicon-containing correlated electron material. In embodiments, processes are described for forming the silicon-containing correlated elect...
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WO/2018/046884A1 |
The present techniques generally relate to a method for the manufacture of a CEM switching device providing that the CEM layer comprises a doped metal compound substantially free from metal wherein ions of the same metal element are pres...
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WO/2018/046683A1 |
The present invention relates to a resistive non-volatile memory cell (100) comprising a first electrode (1), a second electrode (2) and an oxide layer (3) disposed between the first electrode and the second electrode, the memory cell be...
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WO/2018/044256A1 |
Disclosed herein are resistive random access memory (RRAM) devices, and related memory cells and electronic devices. In some embodiments, an RRAM device may include a bottom electrode, an oxygen exchange layer (OEL), and an oxide layer. ...
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WO/2018/043894A1 |
The present application relates to a metal-GO core-shell composite nanostructure, a nonvolatile variable resistance memory device comprising the metal-GO core-shell composite nanostructure, and a method for manufacturing the memory device.
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WO/2018/044330A1 |
Embodiments include a resistive random access memory (RRAM) storage cell, having a resistive switching material layer and a semiconductor layer between two electrodes, where the semiconductor layer serves as an OEL. In addition, the RRAM...
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WO/2018/044257A1 |
Disclosed herein are resistive random access memory (RRAM) devices, and related memory cells and electronic devices. In some embodiments, an RRAM device may include a bottom electrode, an oxygen exchange layer (OEL), and an oxide layer. ...
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WO/2018/044255A1 |
Disclosed herein are resistive random access memory (RRAM) devices, and related memory cells and electronic devices. In some embodiments, an RRAM device may include a bottom electrode, an oxygen exchange layer (OEL), and an oxide layer. ...
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WO/2018/043425A1 |
A semiconductor device having a plurality of memory cells (MC1, MC2), the semiconductor device being such that each of the plurality of memory cells (MC1, MC2) respectively has: a memory transistor (10M) having an oxide semiconductor lay...
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WO/2018/037204A1 |
Subject matter herein disclosed relates to a method for the manufacture of a switching device (350) comprising a correlated electron material (360, 370, 380). In embodiments, processes are described which may be useful for avoiding a res...
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WO/2018/039349A1 |
Provided are a nonvolatile memory device and a method of fabricating the same. The nonvolatile memory device includes a semiconductor substrate, a first and a second diffusion regions formed under a surface of the semiconductor substrate...
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WO/2018/033707A1 |
Subject matter disclosed herein may relate to fabrication of correlated electron materials used, for example, to perform a switching function. In embodiments, processes are described, in which an ultraviolet light source is utilized duri...
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WO/2018/029481A1 |
The present techniques generally relate to fabrication of layered correlated electron materials (CEMs) in which a first group of one or more layers may comprise a first concentrationof a dopant species, and wherein a second group of one ...
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WO/2018/025691A1 |
Provided is a rectifier element for preventing incorrect writing and incorrect operation, and for replacing a select transistor. A semiconductor device on which the rectifier element is mounted, which has excellent reliability, and which...
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WO/2018/026815A1 |
A random access memory (RAM) includes a bit-line, a source-line, a memory cell connected to the bit-line and the source-line, and a read/write circuit connected to the bit-line and the source-line and including a negative differential re...
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WO/2018/022027A1 |
In an embodiment, a resistive random access memory cell includes a plurality of conductive interconnects disposed in a first dielectric layer above a substrate. A plurality of RRAM devices is disposed in a second dielectric layer and eac...
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WO/2018/022174A1 |
A memory device includes a metal oxide material disposed between and in electrical contact with first and second conductive electrodes, and an electrical current source configured to apply one or more electrical current pulses through th...
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WO/2018/011547A1 |
The present techniques generally relate to fabrication of correlated electron materials used, for example, to perform a switching function. In embodiments, processes are described, which may be useful in avoiding formation of a potential...
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WO/2018/012868A1 |
Disclosed are a switching atomic transistor having a diffusion barrier layer and a method for operating same. As a result of introducing a diffusion barrier layer onto an intermediate layer having a variable resistance characteristic, a ...
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WO/2018/009154A1 |
Approaches for integrating a switching layer that is continuous across an array of RRAM (RRAM) cells and the resulting structures, are described. In an example, a RRAM (RRAM) cell includes an RRAM device coupled to a conductive interconn...
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WO/2018/007807A1 |
The present techniques generally relate to fabrication of correlated electron materials used, for example, to perform a switching function. In embodiments, a correlated electron material (220) may be doped using dopant species (205, 206)...
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WO/2018/009182A1 |
A resistive RAM memory cell and array are described that include an electroforming functionally. One example includes a first resistive memory material, a first electrode on one side of the first resistive memory material, a second resis...
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WO/2018/009156A1 |
Embodiments of the present invention include RRAM devices and their methods of fabrication. In an embodiment, a resistive random access memory (RRAM) cell includes a conductive interconnect disposed in a dielectric layer above a substrat...
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WO/2018/009155A1 |
Resistive random access memory (RRAM) devices having a bottom oxygen exchange layer and their methods of fabrication are described. In an example, an RRAM cell includes a conductive interconnect disposed in a first dielectric layer above...
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WO/2018/006131A1 |
A memristor device is provided, comprising a first electrode; a second electrode; a cathode metal layer disposed on a surface of the first electrode; and an active region disposed between and in electrical contact with the second electro...
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WO/2018/009157A1 |
A memory including a top electrode and a bottom electrode; and an oxide layer including a plurality of intimately mixed oxides throughout the oxide layer. A memory including a top electrode and a bottom electrode; an oxygen exchange laye...
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WO/2018/004697A1 |
Approaches for integrating a dual layer stack for a resistive random access memory cell and the resulting structures, are described. In an example, a resistive random access memory (RRAM) cell includes a conductive interconnect disposed ...
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WO/2018/004670A1 |
Approaches for integrating resistive random access memory (RRAM) memory arrays into a logic processor, and the resulting structures, are described. In an example, a logic processor includes a logic region including a first portion of an ...
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WO/2018/004650A1 |
Techniques are disclosed for forming a one transistor, one resistor (1T-1R) resistive random-access memory (RRAM) cell including a group III-N access transistor, such as a gallium nitride (GaN) access transistor. Use of a group III-N acc...
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WO/2018/004587A1 |
Approaches for fabricating RRAM stacks with two-dimensional (2D) barrier layers, and the resulting structures and devices, are described. In an example, a resistive random access memory (RRAM) device includes a conductive interconnect di...
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WO/2018/004562A1 |
Approaches for fabricating self-aligned pedestals for resistive random access memory (RRAM) elements and devices, and the resulting structures, are described. In an example, a resistive random access memory (RRAM) device includes a condu...
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WO/2018/003864A1 |
Provided are: a semiconductor device in which a non-volatile switch on which a rectifier is mounted and a non-volatile element on which a rectifier is not mounted are formed in the same wiring; and a method for producing a semiconductor ...
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