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WO/2021/003904A1 |
The present invention provides a phase change memory and a manufacturing method thereof. The phase change memory comprises a substrate, multiple phase change memory cells, and an isolation material layer. The multiple phase change memory...
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WO/2021/003683A1 |
Disclosed are a silicon oxide-based memristor based on a solution method, and a preparation method and application thereof, said method comprising: (1) preparing a lower electrode on a substrate, or providing or directly preparing a lowe...
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WO/2021/003028A1 |
Methods, systems, and devices for memory device with a split pillar architecture are described. A memory device may include a substrate arranged with conductive contacts in a pattern and openings through alternative layers of conductive ...
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WO/2021/002992A1 |
Methods, systems, and devices for split pillar architectures for memory devices are described. A memory device may include a substrate arranged with conductive contacts in a pattern and openings through alternative layers of conductive a...
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WO/2020/263360A1 |
A phase change memory cell includes a first electrode, a second electrode located over the first electrode, a vertical pillar structure located between the first and second electrodes, the pillar structure containing a first phase change...
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WO/2020/261736A1 |
In the present invention, with regard to a selection element that is provided with a plurality of switch layers and that performs selection control in accordance with an applied voltage, the usage-possible period of the selection element...
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WO/2020/256785A1 |
A memory device includes a plurality of memory cells, and an isolation material portion located between the memory cells. The isolation material portion includes at least one ovonic threshold switch material portion.
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WO/2020/256777A1 |
A perpendicular spin transfer torque MRAM memory cell includes a magnetic tunnel junction stack comprising a pinned layer having a fixed direction of magnetization, a free layer having a direction of magnetization that can be switched, a...
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WO/2020/249697A1 |
The invention relates to a method for determining at least one value (tTE_opt, tOX_opt, Xopt) of at least one production parameter (tTE, tOX, x) for a resistive memory cell, the resistive memory cell comprising a thin-film stack, said me...
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WO/2020/251621A1 |
The switching device includes three terminals including an inner surface, an oxide layer on the inner surface of the third terminal, and a chalcogenide pillar extending through the oxide layer and the third terminal, the pillar being in ...
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WO/2020/251636A1 |
First elongated loop-shaped conductive material portions are formed over a substrate. A two-dimensional array of memory pillar structures is formed over the first elongated loop-shaped conductive material portions. Second elongated loop-...
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WO/2020/251747A1 |
Exemplary semiconductor structures for neuromorphic applications may include a first layer overlying a substrate material. The first layer may be or include a first oxide material. The structures may include a second layer disposed adjac...
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WO/2020/249699A1 |
The invention concerns a method for manufacturing an OxRAM resistive memory cell comprising a layer of silicon oxide, said method comprising the following steps: - determining values of manufacturing parameters enabling the resistive mem...
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WO/2020/251637A1 |
A phase change memory material and a vertical bit line are formed within each of the memory openings that extend through an alternating stack of insulating layers and sacrificial material layers. The phase change memory material can be f...
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WO/2020/247038A1 |
A phase change memory device includes a phase change material portion located between a first electrode and a second electrode, and a crystallization template material portion located between the first electrode and the second electrode ...
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WO/2020/240603A1 |
The present invention refers to a quantum diode for transforming an alternating current, in particular a high frequency alternating current, into a direct current, comprising: a first conductive metal layer (1) behaving as a first electr...
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WO/2020/243417A1 |
A method of controlling the forming voltage of a dielectric film in a resistive random access memory (ReRAM) device. The method includes depositing a dielectric film contains intrinsic defects on a substrate, forming a plasma-excited tre...
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WO/2020/235591A1 |
The purpose of the present invention is to provide a novel variable resistance device, the resistance state of which is variable.　Consequently, one of typical variable resistance devices according to the present invention is provided w...
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WO/2020/231581A1 |
Some embodiments include a method of forming an arrangement. A first tier is formed to include CMOS circuitry. A second tier is formed to include an assembly which has first and second sets of memory cells on opposing sides of a coupling...
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WO/2020/231531A1 |
A semiconductor device includes a first level having a plurality of transistor devices, and a first wiring level positioned over the first level. The first wiring level includes a plurality of conductive lines extending parallel to the f...
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WO/2020/231533A1 |
A semiconductor device includes a first level having a plurality of transistor devices, and a first wiring level positioned over the first level. The first wiring level includes a plurality of conductive lines extending parallel to the f...
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WO/2020/229752A1 |
The present description relates to a selector (33) for a memory cell (3), which selector is intended to switch from a resistive state to a conducting state so as to respectively prevent or allow access to the memory cell, characterized i...
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WO/2020/231494A1 |
First electrically conductive lines, first pillar structures, second electrically conductive lines, second pillar structures, third electrically conductive lines, third pillar structures, fourth electrically conductive lines, and fourth ...
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WO/2020/225521A1 |
Various implementations described herein are directed to a device having a multi-layered structure formed on a substrate. The multi- layered structure has a switching layer (112), and the switching layer is formed with correlated electro...
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WO/2020/227001A1 |
Exemplary methods of forming a memory structure may include forming a layer of a transition-metal-and-oxygen-containing material overlying a substrate. The substrate may include a first electrode material. The methods may include anneali...
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WO/2020/226797A1 |
Architectures of 3D memory arrays, systems, and methods regarding the same are described. An array may include a substrate arranged with conductive contacts in a geometric pattern and openings through alternative layers of conductive and...
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WO/2020/223032A1 |
A transistor comprises a channel region between a source region and a drain region, a dielectric material adjacent to the channel region, an electrode adjacent to the dielectric material, and an electrolyte between the dielectric materia...
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WO/2020/222992A1 |
Some embodiments include an arrangement having a memory tier with memory cells on opposing sides of a coupling region. First sense/access lines are under the memory cells, and are electrically connected with the memory cells. A conductiv...
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WO/2020/222455A1 |
The present invention provides a synaptic mechanics transistor. More specifically, provided is a synaptic mechanics transistor comprising an ionic active layer forming a channel according to movement of ions, thereby being capable of imp...
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WO/2020/215423A1 |
Provided in the present invention are a phase change material, a phase change storage unit, and a preparation method therefor; the phase change material comprises the element tantalum, the element antimony, and the element tellurium, and...
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WO/2020/172499A8 |
Resistive switching devices that contain lithium, including resistive switching devices containing a lithium titanate, and associated systems and methods are generally described. In some cases, the resistive switching device contains a l...
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WO/2020/213240A1 |
In order to improve memory access parallelism without sacrificing the operation margin, a storage unit is provided with a plurality of first wires extending in a first direction, a plurality of second wires extending in a second directio...
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WO/2020/212981A1 |
The invention provides process for preparing tin or germanium monochalcogenides of cubic crystalline structure, the process comprises combining a source of tin or germanium and a source of chalcogenide in a reaction vessel in the presenc...
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WO/2020/213968A1 |
A memory device is disclosed. According to an embodiment, the memory device may be implemented as a bidirectional two-terminal phase-change memory device which adaptively determines a depletion layer, or may be implemented as a crosspoin...
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WO/2020/213321A1 |
Provided are a sputtering target capable of forming a film of a chalcogenide material with improved heat resistance, a method for manufacturing the same, and a method for manufacturing a memory device. The sputtering target comprises an ...
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WO/2020/206858A1 |
Disclosed is a gate tube device preprocessing method. The method comprises: (1) carrying out first voltage scanning on a gate tube by selecting a voltage scanning range and setting a first limit current Icc1, so as to acquire a resistanc...
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WO/2020/205675A1 |
A memristive multi-terminal spiking neuron apparatus, comprising a non-volatile memristor, wherein the non- volatile memristor has a resistance ratio between the high-resistance and low-resistance states exceeding (4) decades of magnitud...
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WO/2020/203220A1 |
Provided is a logic integrated circuit wherein a read/write control line is connected to a first circuit and a second circuit, a switch cell array is connected to the first circuit, and a logic element is connected to the second circuit,...
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WO/2020/195918A1 |
The present invention provides a non-linear resistance element provided with a first electrode made of a metal nitride, a first intermediate layer made of a metal, a non-linear resistance layer made of an amorphous chalcogenide thin film...
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WO/2020/185248A1 |
A single-event-upset (SEU) stabilized memory cell includes a latch portion including a cross-coupled latch, and at least one cross coupling circuit path in the latch portion including a first series-connected pair of vertical resistors.
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WO/2020/183738A1 |
An exclusive NOR (XNOR) gate includes an inverter, a first resistive switch whose first terminal is connected to an input terminal of the inverter, and a second resistive switch whose first terminal is connected to an output terminal of ...
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WO/2020/180247A1 |
Biocompatible transient switching memory devices and methods for their fabrication are provided. In accordance with one aspect, a memory device is provided. The memory device includes a layer comprising tungsten, a lower electrode compri...
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WO/2020/179199A1 |
In this non-volatile memory device (100), inside a storage area (60), a first lower layer metal wiring (20), a bottom plug (30), a variable resistance element (40), a top plug (32), and a first upper layer metal wiring (23) are formed in...
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WO/2020/180248A1 |
Biodegradable threshold switching devices and methods for their fabrication are provided. In accordance with one aspect, a biodegradable threshold switching device includes a bottom electrode, a top electrode, and a switching layer sandw...
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WO/2020/179006A1 |
A nonvolatile semiconductor storage device according to an embodiment of the present invention is provided with: a plurality of first wiring layers that extend in a first direction and that are aligned along a second direction intersecti...
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WO/2020/131054A9 |
A high-voltage switch, whose operation leverages the speed of electrons to generate the "on" time of the pulse in combination with the speed of light to generate the "off" time of the pulse, is described. In one example, the high-voltage...
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WO/2020/172499A1 |
Resistive switching devices that contain lithium, including resistive switching devices containing a lithium titanate, and associated systems and methods are generally described. In some cases, the resistive switching device contains a l...
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WO/2020/166073A1 |
According to an embodiment, a nonvolatile semiconductor storage device is provided with: a plurality of first wiring layers extending in a first direction; a plurality of second wiring layers extending over the plurality of first wiring ...
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WO/2020/161562A1 |
A resistive memory structure is provided. The resistive memory structure includes a vertical fin on a substrate, wherein the sidewalls of the vertical fin each have a {100} crystal face. The resistive memory structure further includes a ...
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WO/2020/161454A1 |
Disclosed is a method for the fabrication of a correlated electron material (CEM) device to an comprising: forming a layer of a conductive substrate on a substrate; forming a layer of a correlated electron material on the layer of conduc...
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