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Matches 1 - 50 out of 4,770

Document Document Title
WO/2024/007381A1
A semiconductor structure and a method for forming same, and a memory. The semiconductor structure comprises: a substrate (210); and phase change storage units (300), located on the substrate (210). Each phase change storage unit (300) c...  
WO/2023/140879A1
A memory device includes a memory material portion, and an ovonic threshold switch selector element. The ovonic threshold switch selector element includes a first carbon-containing electrode comprising carbon and a metal, a second carbon...  
WO/2023/115723A1
The present invention belongs to the technical field of artificial intelligence, and particularly relates to a method for preparing a reservoir element. The method comprises the following steps: a) sequentially arranging, on a substrate,...  
WO/2023/116046A1
A memory and a preparation method therefor. The memory comprises: a bottom circuit layer (1); a bottom electrode (2) provided on the upper surface of the bottom circuit layer (1); an oxide layer (3) provided around the bottom electrode (...  
WO/2023/116023A1
A semiconductor device and a manufacturing method therefor. The manufacturing method comprises: depositing a first dielectric layer material on a semiconductor substrate (10), and etching the first dielectric layer material, such that a ...  
WO/2023/115357A1
The present disclosure relates to a resistive random access memory and a manufacturing method therefor. The resistive random access memory comprises a first electrode layer, a second electrode layer and a resistive dielectric layer locat...  
WO/2023/103443A1
Disclosed in the present application are a semiconductor integrated circuit device and a manufacturing method therefor. The structure used by the semiconductor integrated circuit device involves first electrodes being connected to resist...  
WO/2023/087749A1
Disclosed in the embodiments of the present application are a linear resistance variation element and a preparation method therefor. The linear resistance variation element comprises a substrate unit, a functional unit and an electrode u...  
WO/2023/087750A1
Disclosed in the present application are a semiconductor integrated circuit device and a manufacturing method therefor. By means of the semiconductor integrated circuit device, a resistance variation layer covers an outer side of a bump ...  
WO/2023/070986A1
Provided in the embodiments of the present application are a ferroelectric tunnel junction device and a manufacturing method therefor. The ferroelectric tunnel junction device comprises a first electrode, a dielectric layer, a ferroelect...  
WO/2023/065195A1
The present application provides a ferroelectric device, a storage apparatus and an electronic device, which relate to the field of storage and can improve the endurance of a ferroelectric device. The ferroelectric device comprises a top...  
WO/2023/050664A1
The present invention relates to the technical field of microelectronics. Specifically disclosed is a phase change memory cell. A dielectric layer is formed by means of growing an amorphous dielectric material capable of high electrother...  
WO/2023/046363A1
An apparatus (106) includes a heater (210, 212), a phase change material region (218), and a top metal layer (226). The phase change material region includes a doped GST layer (222) and a first GST layer (220, 224). The first GST layer i...  
WO/2023/040385A1
A three-dimensional phase-change memory structure, a preparation method therefor, a phase-change memory, and an electronic device. The three-dimensional phase-change memory structure comprises: a substrate (110), a stack structure (120) ...  
WO/2023/039847A1
A resistance random access memory unit 300, a resistance random access memory, and an electronic device. The resistance random access memory unit 300 comprises a bottom electrode 301, a top electrode 304, and a resistance random material...  
WO/2023/041296A1
Insulated phase change memory devices are provided that include a first electrode (210a), a second electrode (210b), a phase change material (250) between the first electrode and the second electrode, and a porous dielectric (310) config...  
WO/2023/036307A1
The present application provides a phase change memory unit and a phase change memory. The phase change storage unit comprises a first electrode, a second electrode, and a phase change material layer; the phase change material layer is l...  
WO/2023/036508A1
A semiconductor structure includes a heater located (20, 22, 24) in a first layer of a device, wherein the heater is surrounded by a dielectric, a phase change memory (PCM) liner (132) in direct contact with a top surface of the heater i...  
WO/2023/035408A1
Provided in the present disclosure are a phase change memory and a manufacturing method for a phase change memory. The phase change memory comprises: a substrate; a stacked structure, the stacked structure being arranged on the substrate...  
WO/2023/036718A1
A semiconductor structure (100) is disclosed which includes a plurality of conductive lines (18) formed within a dielectric (12), each conductive line electrically communicating with a respective contact (14, 16), a metal layer (24) disp...  
WO/2023/038870A1
A layer of a chalcogenide material can be etched by providing a wafer having a layer of the chalcogenide material to a processing chamber, heating the wafer to a first temperature, modifying a surface of the layer of chalcogenide materia...  
WO/2023/028722A1
Embodiments of the present application disclose a phase change memory and a method for manufacturing the phase change memory. The phase change memory comprises: one or more phase change memory cells, each of said phase change memory cell...  
WO/2023/021178A1
A phase change memory (PCM) cell (100) includes a bottom electrode (104), a heater (108) electrically connected to the bottom electrode, a PCM material (114) electrically connected to the heater, a top electrode (122) electrically connec...  
WO/2023/004609A1
In certain aspects, a memory device includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells. Each one of the plurality of memory cells is disposed at an intersection of a respective one of the plural...  
WO/2023/273542A1
The present application is applicable to the technical field of semiconductors, and provides a memory array, a preparation method for the memory array, a phase change memory, and a memory chip. The memory array comprises a substrate mate...  
WO/2022/262836A1
The present invention provides a gate, comprising a bottom electrode, a resistive layer, and a top electrode. The resistive layer of the gate is fixed on the bottom electrode, the top electrode is fixed on the resistive layer, the bottom...  
WO/2022/265845A1
Circuits and methods that enable stacking of phase change material (PCM) switches and that accommodate variations in the resistance of the resistive heater(s) of such switches. Stacking is enabled by providing isolation switches for the ...  
WO/2022/262414A1
The present application relates to the technical field of data storage, and provides a phase change memory, an electronic device, and a preparation method for a phase change memory, to solve the problems of low reliability, short cycle l...  
WO/2022/263659A1
The present disclosure relates to an electronic transistor comprising a body comprising at least an electrolyte structure, a channel provided in contact with the electrolyte structure, a gate provided in contact with the electrolyte stru...  
WO/2022/263165A1
A resistive RAM module comprises a source electrode and an intermediate electrode that is formed on the source electrode. The intermediate electrode has a closed-curve profile. The resistive RAM module also comprises a memristor element ...  
WO/2022/262651A1
Provided in the present invention is a preparation method for a 1S1R-type memory integrated structure. The method comprises: preparing a gating device and a resistive random access memory; and connecting the gating device to the resistiv...  
WO/2022/257280A1
Provided are a method for preparing a bipolar gating memristor, and a bipolar gating memristor. The method comprises: preparing a lower electrode; depositing a resistive switching material layer on the lower electrode; and depositing an ...  
WO/2022/257764A1
A phase change memory (PCM) cell comprises: a first electrode located on a substrate; a phase change material layer located adjacent to the first electrode, wherein a first side of the phase change material layer is in direct contact wit...  
WO/2022/260701A1
Carbon nanotube (CNT) memory cell elements and methods of forming CNT memory cell elements are provided. A CNT memory cell may comprise a CNT memory cell element, e.g., in combination with a transistor. A CNT memory cell element (202) in...  
WO/2022/257935A1
The present application belongs to the technical field of semiconductor storage. Disclosed are a phase-change memory cell, a phase-change memory, an electronic device and a preparation method. The phase-change memory cell comprises: a ph...  
WO/2022/260700A1
Resistive random access memory (RRAM) cells, for example conductive bridging random access memory (CBRAM) cells and oxygen vacancy-based RRAM (OxRRAM) cells are provided. An RRAM cell may include a metal-insulator-metal (MIM) structure f...  
WO/2022/252219A1
Provided in the embodiments of the present application are a phase change memory and an electronic device, the phase change memory comprising a first electrode, a second electrode, and a phase change memory unit positioned between the fi...  
WO/2022/256790A1
Memristors are provided, which, in embodiments, comprise a bottom electrode; a top electrode in electrical communication with the bottom electrode, wherein one or both of the bottom and top electrodes is a Schottky electrode; and a diele...  
WO/2022/251791A1
Methods, systems, and devices for techniques that support sidewall structures for memory cells in vertical structures are described. A memory cell may include a first electrode, a second electrode, and a self-selecting storage element be...  
WO/2022/251778A1
Methods, systems, and devices for techniques for memory cells with sidewall and bulk regions in vertical structures are described. A memory cell may include a first electrode, a second electrode, and a self-selecting storage element betw...  
WO/2022/241637A1
The present disclosure relates to a phase change memory (PCM) and a manufacturing method therefor. The PCM may comprise a plurality of phase change memory cells, wherein each phase change memory cell comprises an upper electrode, a lower...  
WO/2022/241635A1
A three-dimensional (3D) memory device includes a stack structure including interleaved a plurality of word line layers and a plurality of dielectric layers; and a plurality of phase-change memory (PCM) strings. Each of the PCM strings e...  
WO/2022/241660A1
A three-dimensional (3D) memory device includes a plurality of bit lines extending laterally, a common plate extending laterally, a plurality of word lines extending laterally and being disposed between the plurality of bit lines and the...  
WO/2022/241970A1
The present invention provides a memristor and a preparation method therefor. The memristor comprises, from top to bottom, an upper electrode, a first vacancy concentration resistance change layer, a second vacancy concentration resistan...  
WO/2022/242673A1
Provided in the present disclosure are a semiconductor integrated circuit device and a manufacturing method therefor. In the semiconductor integrated circuit device, an electrode in a resistance random access memory cell is directly conn...  
WO/2022/241139A1
The present disclosure relates to resistive random-access memory (RRAM) devices. A method for fabricating resistive random-access memory (RRAM) device may include fabricating, on a first electrode of the RRAM device, a first interface la...  
WO/2022/236707A1
The embodiments of the present application relate to the technical field of memories. Provided are a phase change memory and a manufacturing method therefor, and an electronic device, which can solve the problem of increased power consum...  
WO/2022/240138A1
The present invention relates to a neuromorphic device, which is an electronic device that mimics the structure and functions of the human nervous system which performs high-order functions such as cognition, memory, learning, calculatio...  
WO/2022/240426A1
The present disclosure relates to resistive random-access memory (RRAM) devices. In some embodiments, a RRAM device may include a first electrode, a second electrode, and a switching oxide layer positioned between the first electrode and...  
WO/2022/227882A1
A single-channel memristor and a preparation method therefor. The single-channel memristor comprises a functional layer, which is formed by first functional layers (1) and second functional layers (2) in a stacked manner, wherein there i...  

Matches 1 - 50 out of 4,770