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WO/2018/186166A1 |
Memory structures with a plurality of memory cells that each include a memory device in combination with a switch device are provided. The memory device and switch device of each cell are connected in series, and include at least first a...
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WO/2018/186940A1 |
First electrically conductive lines (134) are formed over a substrate (10). A two-dimensional array of vertical stacks (180) is formed, each of which includes a first electrode (212), an in-process resistive memory material portion (214)...
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WO/2018/186997A1 |
The present disclosure includes three dimensional memory arrays, and methods of processing the same. A number of embodiments include a plurality of conductive lines separated from one other by an insulation material, a plurality of condu...
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WO/2018/182649A1 |
A resistive random access memory (RRAM) device includes a bottom electrode disposed above a substrate, a top electrode disposed above the bottom electrode, an oxygen exchange layer disposed between the bottom electrode and the top electr...
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WO/2018/182742A1 |
An apparatus is described. The apparatus includes a computation unit. The computation unit includes stacked, resistive elements. Each of the resistive elements is coupled to its own respective input node. Each of the resistive elements i...
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WO/2018/182799A1 |
A method is provided that includes forming a bit line above a substrate; forming a word line above the substrate, and forming a non-volatile memory cell between the bit line and the word line. The non-volatile memory cell includes a non-...
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WO/2018/181019A1 |
The present invention provides a resistance change element that improves set voltage variation between elements. Provided is a semiconductor device that includes at least two resistance change elements, a first terminal, and a second ter...
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WO/2018/181921A1 |
The present invention enables improvement of a set-forming yield while preventing insulation breakdown of a rectifying element when being set. In a plurality of switching cells, terminals on one side of two variable resistance elements a...
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WO/2018/180536A1 |
The purpose of the present invention is to provide a circuit capable of reducing leakage power in a programmable logic circuit using resistance change elements. To this end, the present invention is a programmable logic integrated circui...
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WO/2018/180759A1 |
This time change element includes a time change phase transition material for which the phase transition between solids progresses with the passage of time after manufacturing, irrespective of whether there is stimulus from outside, the ...
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WO/2018/182678A1 |
Resistive switch devices including a thermal layer and processes for forming the devices are provided. The thermal layer can be thermally resistive layer and electrically insulating. As such, the thermal layer can be arranged to cap or o...
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WO/2018/180228A1 |
A memory device according to an embodiment of the present disclosure comprises a memory cell array which is configured such that, when, of a plurality of memory cells, a plurality of first memory cells of which corresponding fourth wires...
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WO/2018/178720A1 |
A switching resistor has a low resistance state and a high resistance state. The switching resistor comprises a dielectric layer disposed between a first electrode and a second electrode. The switching resistor further comprises a textur...
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WO/2018/182680A1 |
Resistive switch devices including a thermal layer and processes for forming the devices are provided. The thermal layer can be thermally resistive layer and electrically conductive. As such, the thermal layer can be intercalated between...
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WO/2018/174514A1 |
Provided is a nonvolatile memory element characterized by having multilevel resistance and capacitance values. The nonvolatile memory element comprises: a substrate; a first electrode positioned on the substrate; a dielectric material la...
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WO/2018/169269A1 |
An oxide-based resistive switching memory element using a single nanopore structure and a manufacturing method therefor are disclosed. The resistive switching memory element manufacturing method comprises: a lower electrode layer forming...
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WO/2018/164856A1 |
Switches for electromagnetic radiation, including radiofrequency switches and optical switches, are provided. Also provided are methods of using the switches. The switches incorporate layers of high quality VO2 that are composed of a plu...
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WO/2018/164745A1 |
A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first directi...
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WO/2018/160732A1 |
Systems, devices, and related methods are disclosed for electromechanical transfer printing of 2D materials disposed on one substrate to another. The printing device can be configured to transfer a 2D material from a source substrate to ...
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WO/2018/152697A1 |
A preparation method for a selector based on a transition metal oxide and a selector prepared by the method. The preparation method comprises: S1, forming a tungsten plug on a transistor; S2, using the tungsten plug as a lower electrode,...
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WO/2018/151987A1 |
Methods, systems, and apparatus that support efficient utilization of die area for crosspoint memory architecture are described. A memory array may include active memory cells overlying each portion of the substrate that includes certain...
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WO/2018/144457A1 |
Methods for scaling dimensions of resistive change elements, resistive change element arrays of scalable resistive change elements, and sealed resistive change elements are disclosed. According to some aspects of the present disclosure t...
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WO/2018/143611A1 |
The present invention relates to a method for manufacturing a large-area metal chalcogenide thin film and a device comprising the large-area metal chalcogenide thin film manufactured thereby, the method comprising the steps of: preparing...
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WO/2018/138482A1 |
The present techniques generally relate to fabrication of correlated electron materials used, for example, to perform specified application performance parameters 277-283. In embodiments, CEM devices fabricated at a first stage of a wafe...
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WO/2018/138275A1 |
The invention relates to a metal-insulator-graphene diode, comprising a metal electrode (34) having an electrode surface, comprising an insulator layer (28), which is in planar contact with the electrode surface via a first main surface ...
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WO/2018/134561A1 |
An electronicfilter circuit comprising resistive and capacitive elements, wherein a resistive element of the filter circuit is provided by a correlated electron material device. The electronic filter circuit may form part of a tuneable a...
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WO/2018/136140A1 |
Resistive memory cells containing nanoparticles are formed between two electrodes. The nanoparticles may be embedded in a matrix or sintered together without a matrix. The memory cells may be projected memory cells or barrier modulated c...
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WO/2018/134699A1 |
A phase change memory array and method for fabricating the same. The phase change memory array includes a plurality of bottom electrodes, top electrodes, and memory pillars. Each of the memory pillars includes phase change material surro...
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WO/2018/130914A1 |
A memristive device includes a first conductive material layer. An oxide material layer is arranged on the first conductive layer. A second conductive material layer is arranged on the oxide material layer, where in the second conductive...
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WO/2018/123678A1 |
Provided is a metal-bridged-type resistance variable element in which a switching voltage and variations thereof are decreased, and which is suitable for high-density integration. The resistance variable element comprises: a metal precip...
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WO/2018/125174A1 |
Substrates, assemblies, and techniques for a transmission gate that includes an n-type back end transistor and a p-type back end transistor in parallel with the n-type back end transistor. The transmission gate can be on a non-silicon su...
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WO/2018/125238A1 |
In various embodiments, low-density dielectrics (for example, interlayer dielectrics, ILDs) can be used as the active layer in conduction bridging random access memory (CBRAM) devices. Further, such low-density dielectrics may permit a p...
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WO/2018/125386A1 |
Doping a storage element, a selector element, or both, of a memory cell with a dopant including one or more of aluminum (Al), zirconium (Zr), hafnium (Hf), and silicon (Si), can minimize volume or density changes in a phase change memory...
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WO/2018/122156A1 |
The invention relates to a solution for using elementary electrochemical components, manufactured from the same arrangement of materials and incorporated in a single electronic circuit, for information storage or for energy storage. Elec...
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WO/2018/125237A1 |
In one embodiment, systems, methods, and apparatus are described that can reduce the peak current through semiconductor memory devices such as RRAM devices. In one embodiment, transition metal dichalcogenide (TMD) materials can be used t...
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WO/2018/113142A1 |
A porphyrin memristor device and a method of fabrication of the device are described that include a three-tier structure as anode, switching layer and cathode, the switching layer is interposed between the anode and cathode, also include...
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WO/2018/117358A1 |
Provided is a soft electronic system having an integrated memory and logic device, comprising: a substrate (100); a first electrode (110) provided in the form of a plurality of bars stacked on the substrate; a resistance-variable substan...
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WO/2018/115831A1 |
The present techniques generally relate to forming a nucleation layer in connection with fabrication of correlated electron materials used, for example, to perform, for example, a switching function. In embodiments, processes are describ...
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WO/2018/104733A1 |
The present techniques generally relate to fabrication of correlated electron materials used, for example, to perform a switching function. In embodiments, processes are described in which a correlated electron material film may be forme...
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WO/2018/104727A1 |
The present techniques generally relate to fabrication of a correlated electron material (CEM) device (300). In embodiments, after formation of the one or more CEM traces (330, 331), a spacer (335) is deposited in contact with the one or...
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WO/2018/106450A1 |
A resistive random access memory cell includes three resistive random access memory devices (102, 104, 106), each resistive random access memory device having an ion source layer (156, 166, 186) and a solid electrolyte layer (154, 164, 1...
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WO/2018/100372A1 |
The present techniques generally relate to correlated electron switch devices, and may relate more particularly to digital to analog conversion using correlated electron switch devices.
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WO/2018/100380A1 |
The present techniques generally relate to fabrication of a correlated electron material (CEM) switch. In embodiments, processes are described in which conductive traces (222) may be formed on or over an insulating material (210). Respon...
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WO/2018/101573A1 |
A light-emitting element display device and a manufacturing method therefor are disclosed. According to the present invention, the light-emitting element display device comprises a light-emitting element array including a plurality of li...
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WO/2018/101956A1 |
Self-aligned electrode nano-contacts for non-volatile random access memory (RAM) bit cells, and methods of fabricating electrode nano-contacts for non-volatile random access memory (RAM) bit cells, are described. In an example, semicondu...
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WO/2018/100341A1 |
The present techniques generally relate to an improved CEM switching device (350) and methods for its manufacture. In this device, a conductive substrate (370) and/or conductive overlay (380) each comprises a primary layer (370a, 380a) o...
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WO/2018/095368A1 |
A phase change electronic device (100), comprising: a first conductive layer (120); a second conductive layer (140) spaced apart from and disposed oppositely to the first conductive layer (120); and a phase change material layer (150) di...
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WO/2018/095367A1 |
A regulation and control method of a phase change of a hydrogen-containing transition metal oxide, the method comprising the following steps: S100, providing a hydrogen-containing transition metal oxide having a structural formula ABOxHy...
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WO/2018/097911A1 |
A method of forming a memory device includes forming a first layer of conductive material having opposing upper and lower surfaces, forming a layer of amorphous silicon on the upper surface of the first layer of conductive material, stri...
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WO/2018/091828A1 |
The invention relates to a process for manufacturing a resistive random-access memory, comprising the following steps: depositing a layer (410) made of an active material of variable electrical resistance on a substrate (300) containing ...
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