| Document |
Document Title |
|
WO/2019/087050A1 |
A liner is deposited conformally to a pore within a first dielectric material of a semiconductor device. The pore extends through the first dielectric material to a top surface of a first metal electrode. The liner is etched such that th...
|
|
WO/2019/078367A1 |
Provided is a memristor which can be manufactured at low temperature and does not include metals that could potentially dry up as a resource. The memristor 1 is provided with: a first electrode 2; a second electrode 3; and an oxide memri...
|
|
WO/2019/066829A1 |
An integrated circuit structure includes a stack of alternating first conductive layers and insulator layers. A plurality of etch pits are through the first conductive layers. A plurality of selectors are in the etch pits adjacent to the...
|
|
WO/2019/062198A1 |
A gate tube device and a preparation method therefor, applied to the technical field of gate tube devices. The gate tube device comprises a first metal electrode layer (1, 9), a second metal electrode layer (4, 12), and a switch layer. T...
|
|
WO/2019/008328A3 |
The present techniques relate to a method for the manufacture of a CEM device comprising forming a thin film of a correlated electron material having a predetermined electrical impedance when the CEM device in its relatively conductive (...
|
|
WO/2019/066894A1 |
Embedded non-volatile memory structures having an independently sized selector element and memory element are described. In an example, a memory device includes a metal layer. A selector element is above the metal layer. A memory element...
|
|
WO/2019/066898A1 |
An integrated circuit comprising a self-aligned embedded phase change memory cell is described. In an example, the integrated circuit includes a bottom electrode. A conductive line is above the bottom electrode along a first direction ab...
|
|
WO/2019/066826A1 |
Embedded non-volatile memory structures having asymmetric selector elements are described. In an example, a memory device includes a word line. An asymmetric selector element is above the word line. The asymmetric selector element includ...
|
|
WO/2019/068094A1 |
A self-aligned memory device includes a conductive bottom plug disposed within an insulating layer and having a coplanar top surface, a self-aligned planar bottom electrode disposed upon the coplanar top surface and having a thickness wi...
|
|
WO/2019/066851A1 |
An apparatus, includes an interconnect, including a conductive material, above a substrate and a resistive random access memory (RRAM) device coupled to the interconnect. The RRAM device includes an electrode structure above the intercon...
|
|
WO/2019/066996A1 |
A memory device includes a first electrode, a non-volatile memory element having a first terminal and a second terminal, where the first terminal is coupled to the first electrode. The memory device further includes a selector having a f...
|
|
WO/2019/063926A1 |
Proposed is a method of producing a recurrent neural network computer, which method comprises consecutive steps of providing a substrate comprising a first electrode; structuring the first electrode by etching using a first mask made of ...
|
|
WO/2019/066828A1 |
Embedded non-volatile memory structures having double selector elements are described. In an example, a memory device includes a word line. A double selector element is above the word line. The double selector element includes a first se...
|
|
WO/2019/066769A1 |
Disclosed herein are selector devices, and related devices and techniques. In some embodiments, a selector device may include a first electrode, a second electrode, a selector material between the first electrode and the second electrode...
|
|
WO/2019/066849A1 |
A memory device includes a bottom electrode above a substrate, a first switching layer on the bottom electrode, a second switching layer including aluminum on the first switching layer, an oxygen exchange layer on the second switching la...
|
|
WO/2019/059892A1 |
Disclosed are electronic devices, memory devices, and computing devices including a metallic glass barrier material for an electrode or a contact. An electronic device (100) includes a semiconductor substrate (110), an electrical compone...
|
|
WO/2019/059894A1 |
Multi-channel vertical transistors for embedded non-volatile memory are described. In an example, a memory array includes a plurality of non-volatile random access memory (RAM) elements. The memory array also includes a plurality of tran...
|
|
WO/2019/059118A1 |
The present invention provides a programmable logic integrated circuit with which it is possible to reduce leakage current while inhibiting increase in the number of connection wires and a consequent increase in occupied area. This logic...
|
|
WO/2019/055008A1 |
Disclosed herein are selector devices and related devices and techniques. In some embodiments, a selector device may include a first electrode, a second electrode, and a selector material between the first electrode and the second electr...
|
|
WO/2019/055003A1 |
Embedded non-volatile memory structures having selector elements with ballast are described. In an example, a memory device includes a word line. A selector element is above the word line. The selector element includes a selector materia...
|
|
WO/2019/055052A1 |
Approaches for fabricating RRAM stacks with reduced forming voltage, and the resulting structures and devices, are described. In an example, a resistive random access memory (RRAM) device includes a conductive interconnect in an inter-la...
|
|
WO/2019/049980A1 |
In order to achieve both high-density implementation of applications in the form a reconfiguration circuit without a redundancy bit and the capability to continuously run applications with redundancy, the present invention is a reconfigu...
|
|
WO/2019/050579A1 |
A method of forming a resistive memory device includes forming an alternating stack of insulating layers and sacrificial material layers that extend along a first horizontal direction over a substrate, forming a laterally alternating seq...
|
|
WO/2019/046030A1 |
In an example, a memory array may include a plurality of first dielectric materials and a plurality of stacks, where each respective first dielectric material and each respective stack alternate, and where each respective stack comprises...
|
|
WO/2019/045808A1 |
An alternating stack of insulating layers and electrically conductive layers is formed over a substrate. Sidewalls of the electrically conductive layers are laterally recessed to form laterally recessed regions. After formation of a conf...
|
|
WO/2019/043206A1 |
The disclosed device comprises a thin film layer (4) of a phase transition material disposed over a substrate (2), and a confinement layer (3) adjacent to the thin film layer. The thin film layer has first and second in-plane lattice par...
|
|
WO/2019/032166A1 |
The disclosed two-dimensional array of vertical field effect transistors (200A) includes a one-dimensional array of ladder-shaped gate electrode lines (52), each including a pair of rail portions (522) that extend laterally along a first...
|
|
WO/2019/022860A1 |
A vanadium dioxide (VO2)-based threshold switch device exhibiting current-controlled negative differential resistance (S-type NDR), an electrical oscillator circuit based on the threshold switch device, a wafer including a plurality of s...
|
|
WO/2019/016539A1 |
A switching resistor comprises a dielectric layer disposed between a first electrode layer and a second electrode layer, the switching resistor having a high resistance state and a low resistance state. The switching resistor is responsi...
|
|
WO/2019/008339A3 |
Subject matter disclosed herein may relate to construction of a correlated electron material (CEM) device. In particular embodiments, after formation of a film comprising layers of a transition metal oxide (TMO) material and a dopant, at...
|
|
WO/2019/009296A1 |
[Problem] To stabilize the transition of a resistance variable element from a low resistance state to a high resistance state. [Solution] This switch element includes a resistance variable element, a first transistor, and a second transi...
|
|
WO/2019/009877A1 |
A phase change memory structure (100) can include a memory cell, a dielectric material (130) adjacent to the memory cell, and a bit line. The memory cell can include a phase change material layer (110) and a top electrode layer (120) abo...
|
|
WO/2019/009876A1 |
A phase change memory structure (100) includes a phase change material layer (110), a top electrode layer (120) above the phase change material layer, a metal silicon nitride layer (130) in contact with the top electrode layer opposite f...
|
|
WO/2019/005113A1 |
Techniques are disclosed for forming resistive random-access memory (RRAM) including a tunnel source access transistor, such as a tunnel source MOSFET. The use of a tunnel source access transistor includes integrating a tunnel diode on t...
|
|
WO/2019/005468A1 |
The present disclosure includes memory cells having resistors, and methods of forming the same. An example method includes forming a first conductive line, forming a second conductive line, and forming a memory element between the first ...
|
|
WO/2019/005167A1 |
An approach for integrating a resistive random access memory (RRAM) device on a dual bottom electrode layer is described. In an example, a resistive random access memory (RRAM) device includes a dual bottom electrode disposed above a sub...
|
|
WO/2019/005168A1 |
A memory device includes a wordline disposed above a substrate and a selector element disposed above the wordline, where the selector element includes a phase change material. The memory device further includes a bipolar memory element d...
|
|
WO/2018/236360A1 |
Phase field effect transistors (Phase FETs) having ferroelectric gate dielectrics are described. In an example, an integrated circuit structure includes a channel layer above a substrate. The channel layer is composed of a material havin...
|
|
WO/2018/236432A1 |
A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first directi...
|
|
WO/2018/236356A1 |
Ferroelectric field effect transistors (FeFETs) having compound semiconductor channels are described. In an example, an integrated circuit structure includes a semiconductor channel layer above a substrate. The semiconductor channel laye...
|
|
WO/2018/231210A1 |
Described herein are two approaches for providing thin film ferroelectric materials. The first approach is based on using a templating layer in contact with a ferroelectric layer, the material of the templating layer being such that it i...
|
|
WO/2018/231296A1 |
A method is provided that includes forming a word line above a substrate, forming a bit line above the substrate, forming a nonvolatile memory material between the word line and the bit line, the nonvolatile memory material including a s...
|
|
WO/2018/223801A1 |
Disclosed are a resistive device and a manufacturing method therefor, a manufacturing method for a display substrate, and a display apparatus, wherein same belong to the field of electronic manufacturing. The manufacturing method for a r...
|
|
WO/2018/225993A1 |
According to an embodiment, a phase-change memory device comprises: an upper electrode and a lower electrode; a phase-change layer in which a crystal state thereof is changed by heat supplied by the upper electrode and the lower electrod...
|
|
WO/2018/220356A1 |
The present techniques generally relate to fabrication of correlated electron materials (CEMs) devices used, for example, to read from a resistive memory element or to write to a resistive memory element. In embodiments, by limiting curr...
|
|
WO/2018/222237A1 |
A method is provided that includes forming a word line above a substrate, forming a bit line above the substrate, forming a nonvolatile memory material between the word line and the bit line, and forming a memory cell including the nonvo...
|
|
WO/2018/221114A1 |
A memory device according to an embodiment of the present disclosure comprises a logic circuit in which a plurality of wiring layers including layers that have different wiring pitches are laminated, and a memory element provided between...
|
|
WO/2018/214142A1 |
A resistive memory device, and manufacturing method thereof. The resistive memory device comprises: a lower electrode (101); an oxide layer (102) containing the metal of the lower electrode and located on the lower electrode (101); a res...
|
|
WO/2018/213208A1 |
A semiconductor power conversion device includes a plurality of device cells in different portions of the active area, each including a respective gate electrode. The device includes a gate pad having a plurality of integrated resistors,...
|
|
WO/2018/207831A1 |
In order to output two potential values of a power supply voltage and a ground voltage and provide a reconfigurable logic integrated circuit having a small circuit area, this programmable logic circuit is provided with: a first switch; a...
|
