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Matches 51 - 100 out of 8,434

Document Document Title
WO/2019/066765A1
A method for forming non-planar capacitors of desired dimensions is disclosed. The method is based on providing a three-dimensional structure of a first material over a substrate, enclosing the structure with a second material that is su...  
WO/2019/066468A1
The present invention relates to a method for manufacturing a laminated chip inductor having a fine-pitch line width and, more particularly, to a method for manufacturing a laminated chip inductor having a plurality of electrode patterns...  
WO/2019/060085A1
A process-invariant RC circuit is formed by patterning a metal layer using the same mask pattern to form a metal layer resistor and a metal layer capacitor. The same mask pattern results in the metal layer resistor and the metal layer ca...  
WO/2019/059118A1
The present invention provides a programmable logic integrated circuit with which it is possible to reduce leakage current while inhibiting increase in the number of connection wires and a consequent increase in occupied area. This logic...  
WO/2019/049980A1
In order to achieve both high-density implementation of applications in the form a reconfiguration circuit without a redundancy bit and the capability to continuously run applications with redundancy, the present invention is a reconfigu...  
WO/2019/046019A1
Several embodiments of the present technology are directed to semiconductor devices, systems including semiconductor devices, and methods of making and operating semiconductor devices. In some embodiments, a semiconductor device comprise...  
WO/2019/043206A1
The disclosed device comprises a thin film layer (4) of a phase transition material disposed over a substrate (2), and a confinement layer (3) adjacent to the thin film layer. The thin film layer has first and second in-plane lattice par...  
WO/2019/032789A1
Methods of processing a substrate include providing a substrate having a polymer dielectric layer and a metal layer formed atop the polymer dielectric layer; depositing a plurality of polymer layers atop the substrate; patterning the plu...  
WO/2019/032700A1
A method of forming a magnetic core on a substrate having a stacked inductor coil includes etching a plurality of polymer layers to form at least one feature through the plurality of polymer layers, wherein the at least one feature is di...  
WO/2019/023171A1
A method is provided for forming an integrated thin film resistor (TFR) in a semiconductor integrated circuit device. A first dielectric layer is deposited on an integrated circuit (IC) structure including conductive contacts, a resistiv...  
WO/2019/020494A1
A method for producing a porous metallic structure comprising a metal element from a metal salt comprising a cation part and an anion part, comprising the steps of: providing a volume of metal salt; exposing the volume of metal salt in a...  
WO/2019/016587A1
An integrated resistor-capacitor (RC) structure (400) is disclosed. The integrated RC structure includes a vertical capacitor (302, 402, 306) and a resistive element (308, 310) disposed above the capacitor. The integrated RC structure us...  
WO/2019/016627A1
A semiconductor device includes a substrate, a gate arranged on the substrate, a dielectric arranged on the gate, a channel arranged on the dielectric, a source electrically coupled to the channel, and a drain electrically coupled to the...  
WO/2019/009296A1
[Problem] To stabilize the transition of a resistance variable element from a low resistance state to a high resistance state. [Solution] This switch element includes a resistance variable element, a first transistor, and a second transi...  
WO/2019/009005A1
Provided is a technique that enables a secondary battery to have a desired size. A secondary battery (10) according to one embodiment of the present disclosure is provided with: a base material (11); a charge layer (14) which is formed o...  
WO/2019/005002A1
There is disclosed in one example a level shifter, including: a first ferroelectric capacitor; an input voltage signal applied to a first node of the first ferroelectric capacitor; a second capacitor; and an output voltage signal at a sh...  
WO/2019/005143A1
Described is an apparatus which comprises: a first metal layer; a second metal layer; and two or more layers coupled between the first and second metal layers, wherein the two or more layers include a first layer comprising a conductive ...  
WO/2019/005174A1
An apparatus is provided which comprises: a source to provide a sinusoidal signal; a capacitor comprising ferroelectric material, the capacitor coupled to the source; and a device coupled in series with the capacitor. An apparatus is als...  
WO/2019/005020A1
Embodiments of the invention include a microelectronic device that includes a plurality of organic dielectric layers and a piezoelectrically actuated tunable capacitor having a variable capacitance formed in-situ with at least one organi...  
WO/2019/002931A1
A distributed LC filter structure is disclosed. The distributed LC filter structure provides simultaneously a distributed inductance and a distributed capacitance in the same structure. Accordingly, discrete passive elements are eliminat...  
WO/2019/005089A1
There is disclosed in one example a charge pump, including: a clock signal; an inverse clock signal; a first ferroelectric capacitor; a second capacitor; and a charge pump circuit electrically located between the first ferroelectric capa...  
WO/2019/005133A1
Embodiments of the invention include a microelectronic device that includes a plurality of organic dielectric layers and a tunable ferroelectric capacitor formed in-situ with at least one organic dielectric layer of the plurality of orga...  
WO/2019/005124A1
The present disclosure is directed to systems and methods for fabricating a semiconductor inductor that includes a coil deposited on a stop layer that is deposited on a sacrificial substrate. The semiconductor inductor may be fabricated ...  
WO/2018/235494A1
The sheet-form rechargeable battery according to this embodiment comprises: a base material (11) having a base part (32) and an opening (31); a dividing line (33) that surrounds the opening (31); an inside charging layer (14b) formed on ...  
WO/2018/235493A1
This method for producing rechargeable battery comprises: a production step in which a laminate divided into a plurality of blocks (32) is formed by means of a laminating step in which a charging layer (13) having an n-type metal oxide m...  
WO/2018/231581A1
Methods of processing a substrate include: providing a substrate with a first polymer dielectric layer; forming a first RDL on the first polymer dielectric layer; constructing a 3D MIM capacitive stack on the first RDL in at least one op...  
WO/2018/222342A1
A planar differential inductor reduces an effect of parasitics on common mode inductance of a voltage controlled oscillator (VCO) -based inductor to properly ground a common mode alternating current (AC) ground. In one instance, the plan...  
WO/2018/221114A1
A memory device according to an embodiment of the present disclosure comprises a logic circuit in which a plurality of wiring layers including layers that have different wiring pitches are laminated, and a memory element provided between...  
WO/2018/213208A1
A semiconductor power conversion device includes a plurality of device cells in different portions of the active area, each including a respective gate electrode. The device includes a gate pad having a plurality of integrated resistors,...  
WO/2018/207831A1
In order to output two potential values of a power supply voltage and a ground voltage and provide a reconfigurable logic integrated circuit having a small circuit area, this programmable logic circuit is provided with: a first switch; a...  
WO/2018/204017A1
A semiconductor device having a first die and a second die is provided. The first die of the device includes a first surface and a through-substrate via (TSV) extending at least substantially through the first die, the TSV having a porti...  
WO/2018/204015A1
A semiconductor device comprising first and second dies is provided. The first die includes a first through-substrate via (TSV) extending at least substantially through the first die and a first substantially helical conductor disposed a...  
WO/2018/204014A1
A semiconductor device comprising a substrate is provided. The device further comprises a through-substrate via (TSV) extending into the substrate, and a substantially helical conductor disposed around the TSV. The substantially helical ...  
WO/2018/203459A1
A selective element according to one embodiment of the present disclosure is provided with: a first electrode; a second electrode disposed opposite to the first electrode; a semiconductor layer that is provided between the first electrod...  
WO/2018/203887A1
Disclosed herein are vertical capacitors for integrated circuits (ICs), as well as related methods and devices. In some embodiments, a vertical capacitor may include at least two conductive plates on a support, with the conductive plates...  
WO/2018/193759A1
[Problem] To produce a variable resistance element having excellent electrical characteristics at low cost. [Solution] A method for producing a variable resistance element according to the present invention comprises the formation of a f...  
WO/2018/190241A1
A crossbar switch using a variable-resistance element corresponding to multiple fan-out, wherein in order to enable switch operation at high speed with high reliability, a switch circuit is used having: a plurality of four-terminal switc...  
WO/2018/190071A1
A storage device according to one embodiment of the present disclosure is provided with: a plurality of first wiring layers which extend in one direction; a plurality of second wiring layers which extend in another direction; and a plura...  
WO/2018/190951A1
A metal-insulator-metal (MIM) capacitor includes a compound semiconductor substrate. The MIM capacitor includes a collector contact layer on the compound semiconductor substrate, a first dielectric layer on the collector contact layer, a...  
WO/2018/187742A1
Disclosed are systems and methods for a quantum-analogue computing bit array consisting of a single qubit analogue, a serial two qubit analogue coupling, or parallel N qubit analogues. The quantum-analogue computing bit array comprises a...  
WO/2018/185115A1
The present application relates to a capacitor comprising a layer of semiconducting material between the electrode layers. Further, the present application relates to the use of such capacitors, for example in advanced electronic and sem...  
WO/2018/187258A1
A method (200A) and structure for improving high voltage breakdown reliability of a microelectronic device, such as a galvanic digital isolator, involves providing (214) an abatement structure around metal plate corners of a high voltage...  
WO/2018/183790A1
A system and method for fabricating metal insulator metal capacitors while managing semiconductor processing yield and increasing capacitance per area are described. A semiconductor device fabrication process places an oxide layer on top...  
WO/2018/181019A1
The present invention provides a resistance change element that improves set voltage variation between elements. Provided is a semiconductor device that includes at least two resistance change elements, a first terminal, and a second ter...  
WO/2018/181921A1
The present invention enables improvement of a set-forming yield while preventing insulation breakdown of a rectifying element when being set. In a plurality of switching cells, terminals on one side of two variable resistance elements a...  
WO/2018/180536A1
The purpose of the present invention is to provide a circuit capable of reducing leakage power in a programmable logic circuit using resistance change elements. To this end, the present invention is a programmable logic integrated circui...  
WO/2018/180228A1
A memory device according to an embodiment of the present disclosure comprises a memory cell array which is configured such that, when, of a plurality of memory cells, a plurality of first memory cells of which corresponding fourth wires...  
WO/2018/175754A1
A system and method for fabricating metal insulator metal capacitors while managing semiconductor processing yield and increasing capacitance per area are described. A semiconductor device fabrication process places a polysilicon layer o...  
WO/2018/174872A1
A switch capacitor bank structure, an integrated circuit die, and a method of fabricating the switch capacitor bank are disclosed. The switch capacitor bank structure includes a plurality of gallium nitride (GaN) transistors on a semicon...  
WO/2018/168494A1
An electricity storage device (30) is provided with: a first oxide semiconductor layer (14) of first conductivity type; a solid electrolyte layer (18K) which is disposed on the first oxide semiconductor layer (14) and which includes a so...  

Matches 51 - 100 out of 8,434