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WO/2018/181921A1 |
The present invention enables improvement of a set-forming yield while preventing insulation breakdown of a rectifying element when being set. In a plurality of switching cells, terminals on one side of two variable resistance elements a...
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WO/2018/180536A1 |
The purpose of the present invention is to provide a circuit capable of reducing leakage power in a programmable logic circuit using resistance change elements. To this end, the present invention is a programmable logic integrated circui...
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WO/2018/180228A1 |
A memory device according to an embodiment of the present disclosure comprises a memory cell array which is configured such that, when, of a plurality of memory cells, a plurality of first memory cells of which corresponding fourth wires...
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WO/2018/175754A1 |
A system and method for fabricating metal insulator metal capacitors while managing semiconductor processing yield and increasing capacitance per area are described. A semiconductor device fabrication process places a polysilicon layer o...
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WO/2018/174872A1 |
A switch capacitor bank structure, an integrated circuit die, and a method of fabricating the switch capacitor bank are disclosed. The switch capacitor bank structure includes a plurality of gallium nitride (GaN) transistors on a semicon...
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WO/2018/168494A1 |
An electricity storage device (30) is provided with: a first oxide semiconductor layer (14) of first conductivity type; a solid electrolyte layer (18K) which is disposed on the first oxide semiconductor layer (14) and which includes a so...
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WO/2018/148241A1 |
A capacitor structure may include a lower conducting layer (e.g., poly 1 layer) and an upper conducting layer (e.g., overlying poly 2 layer), which define an anode and cathode, and a dielectric layer (e.g., an ONO layer stack) located be...
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WO/2018/143986A1 |
Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a plurality of pillars, wherein individual pillars include a quantum well lay...
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WO/2018/134251A1 |
An electrolyte composition containing (i) at least one aprotic organic solvent; (ii) at least one conducting salt; (iii) at least one compound of formula (I); and (iv) optionally one or more additives.
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WO/2018/132252A1 |
A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first cap...
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WO/2018/132257A1 |
A method of forming an array of capacitors and access transistors there-above comprises forming access transistor trenches partially into insulative material. The trenches individually comprise longitudinally-spaced masked portions and l...
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WO/2018/126318A1 |
A process for purifying semiconducting single-walled carbon nanotubes (sc- SWCNTs) extracted with a conjugated polymer, the process comprising exchanging the conjugated polymer with an s-tetrazine based polymer in a processed sc-SWCNT di...
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WO/2018/123678A1 |
Provided is a metal-bridged-type resistance variable element in which a switching voltage and variations thereof are decreased, and which is suitable for high-density integration. The resistance variable element comprises: a metal precip...
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WO/2018/125110A1 |
In an example, there is disclosed a configurable impedance element, having: a first impedance network including a plurality of series impedance elements and providing an initial impedance; a trim impedance network parallel to the first i...
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WO/2018/124660A1 |
The present invention relates to a novel compound semiconductor, and the use thereof, wherein the novel compound semiconductor comprises: a Co-Sb skutterudite compound; Sn and S that are included in internal pores of the Co-Sb skutterudi...
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WO/2018/125060A1 |
An apparatus comprises one or more logic circuit blocks coupled between a supply voltage and ground and a decoupling capacitor coupled between the supply voltage and ground in parallel to the one or more logic circuit blocks, comprising ...
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WO/2018/126052A1 |
In various embodiments, a bonded structure is disclosed. The bonded structure can include an element and a passive electronic component having a first surface bonded to the element and a second surface opposite the first surface. The pas...
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WO/2018/123353A1 |
A laminated battery (1) relating to the present invention is a secondary battery wherein a first sheet-like battery (110a), a second sheet-like battery (110b), a third sheet-like battery (210a), and a fourth sheet-like battery (210b) are...
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WO/2018/125154A1 |
A transistor including a channel; a source and a drain formed; a gate electrode on the channel; and a spacer between the gate electrode and each of the source and the drain, wherein the sidewall spacer includes a concentration of a halog...
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WO/2018/117235A1 |
This semiconductor solid battery is characterized in that a first insulating layer is provided between an N-type semiconductor and a P-type semiconductor. Preferably, the first insulating layer has a film thickness of not less than 3 nm ...
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WO/2018/100790A1 |
A neuron circuit comprising: an input terminal to which spike signals are input in chronological order; a first switch element with one end connected to the input terminal and the other end connected to an intermediate node, the first sw...
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WO/2018/097924A1 |
A device and method of utilizing spiral interconnects for voltage and power regulation are shown. Examples of spiral interconnects include air core inductors. An integrated circuit package attached to a motherboard using spiral interconn...
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WO/2018/095824A1 |
An integrated electronic component (10) suitable for broadband biasing comprises a monolithic substrate (1), a capacitor structure arranged in a trench (3) network which extends into the substrate, and a continuous track (8) of an electr...
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WO/2018/085016A2 |
A method of forming an array comprising pairs of vertically opposed capacitors comprises forming an upwardly-open conductive lining in individual capacitor openings in insulative-comprising material. An elevational mid- portion of indivi...
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WO/2018/085022A1 |
A method of forming an array comprising pairs of vertically opposed capacitors comprises forming a conductive lining in individual capacitor openings in insulative-comprising material. An elevational mid-portion of individual of the cond...
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WO/2018/066320A1 |
A switch element according to one embodiment of the present disclosure is provided with a first electrode, a second electrode that is arranged to face the first electrode, and a switch layer that is disposed between the first electrode a...
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WO/2018/063687A1 |
Embodiments are generally directed to non-planar on-package via capacitor. An embodiment of an embedded capacitor includes a first plate that is formed in a package via; a dielectric layer that is applied on the first plate; and a second...
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WO/2018/057227A1 |
An inductor is disclosed, including a first wire, a non-conductive material, and a shell. The non-conductive material may cover the first wire, with a portion of each end of the first wire uncovered. The shell may include a top portion a...
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WO/2018/057132A1 |
Apparatuses including compensation capacitors are described. An example apparatus includes: first, second and third capacitors arranged such that the second capacitor is sandwiched between the first and third capacitors, each of the firs...
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WO/2018/054828A1 |
A 3D-capacitor structure is based on a trench network which is etched from a top face (S100) of a substrate (100), and forms a regular array of separated pillars (10). The 3D-capacitor structure comprises a double capacitor layer stack w...
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WO/2018/052651A1 |
A capacitor may include a first capacitor plate having a first length. The capacitor may also include an inorganic capacitor dielectric layer on sidewalls and a surface of the first capacitor plate and a second capacitor plate on the ino...
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WO/2018/048480A1 |
Group 4 transition metal-containing film forming compositions comprising Group 4 transition metal atrane precursors are disclosed. Also disclosed are methods of synthesizing and using the disclosed precursors to deposit Group 4 transitio...
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WO/2018/043425A1 |
A semiconductor device having a plurality of memory cells (MC1, MC2), the semiconductor device being such that each of the plurality of memory cells (MC1, MC2) respectively has: a memory transistor (10M) having an oxide semiconductor lay...
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WO/2018/038598A1 |
A monolithic on-chip fine tune spiral inductor device comprises a semiconductor substrate including a plurality of metal layers; a plurality of peripheral metal grounds being formed in one of the metal layers and disposed at peripheral o...
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WO/2018/034770A1 |
An integrated circuit (IC) device (300) may include a first substrate (310) having an inductor ground plane (320) in a conductive layer of the first substrate. The integrated circuit may also include a first inductor (340) in a passive d...
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WO/2018/025691A1 |
Provided is a rectifier element for preventing incorrect writing and incorrect operation, and for replacing a select transistor. A semiconductor device on which the rectifier element is mounted, which has excellent reliability, and which...
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WO/2018/025654A1 |
This secondary battery is provided with: a first electrode (11); a second electrode (17); a charging layer (14) which is arranged between the first electrode (11) and the second electrode (17), and contains a mixture of an insulating mat...
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WO/2018/022098A1 |
The present subject matter relates to display control in display devices. In an example implementation, a display control layer for a display device comprises a first set of channels filled with a first electrochromic material to control...
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WO/2018/022247A1 |
A stepped-width, co-spiral inductor structure includes a first exterior layer having a first exterior width. The stepped-width, co-spiral inductor structure also includes a first interior layer coupled to the first exterior layer. The fi...
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WO/2018/004851A1 |
Integrated circuit (IC) chip "on-die" inductor structures (systems and methods for their manufacture) may improve signaling from a data signal circuit to a surface contact of the chip. Such inductor structures may include a first data si...
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WO/2018/004563A1 |
An integrated circuit (IC) comprises one or more intra-metal finger to finger capacitors having a closed loop and one or more inter-metal plate to plate capacitors integrated with the one or more intra-metal finger to finger capacitors.
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WO/2018/004651A1 |
Techniques are disclosed for forming an integrated circuit including a capacitor having a multilayer dielectric stack. For example, the capacitor may be a metal-insulator-metal capacitor (MIMcap), where the stack of dielectric layers is ...
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WO/2018/003864A1 |
Provided are: a semiconductor device in which a non-volatile switch on which a rectifier is mounted and a non-volatile element on which a rectifier is not mounted are formed in the same wiring; and a method for producing a semiconductor ...
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WO/2017/221708A1 |
[Problem] To enable formation of a plurality of batteries having an arbitrarily defined shape from a sheet-shaped battery in which a charge layer is sandwiched between a positive pole layer and a negative pole layer, to be performed easi...
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WO/2017/218135A1 |
Capacitive interconnects and processes for fabricating the capacitive interconnects are provided. In some embodiments, the capacitive interconnect includes first metal layers, second metal layers; and dielectric layers including a dielec...
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WO/2017/217119A1 |
[Problem] To provide a circuit element, a storage device, an electronic instrument, a method for writing information to the circuit element, and a method for reading information from the circuit element. [Solution] A circuit element prov...
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WO/2017/217316A1 |
The present invention provides a technique of forming a device pattern at an accurate position on both surfaces of a sheet-shaped secondary battery or a sheet-shaped device. This method for manufacturing a sheet-shaped secondary battery ...
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WO/2017/204863A1 |
Some embodiments include a ferroelectric device comprising ferroelectric material adjacent an electrode. The device includes a semiconductor material-containing region along a surface of the ferroelectric material nearest the electrode. ...
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WO/2017/199618A1 |
[Problem] To provide a secondary battery manufacturing method with which an increase in discharge capacity can be achieved. [Solution] The secondary battery manufacturing method according to the present invention comprises stacking, in t...
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WO/2017/170149A1 |
To stabilize programming operation and to reduce leakage current. A variable resistance element according to the present invention is provided with: an interlayer insulating film; a first electrode that is formed within the interlayer in...
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