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Patent Searching and Data


Matches 1 - 50 out of 8,420

Document Document Title
WO/2019/215284A1
A porous region structure and a method of fabrication thereof are disclosed. The porous region structure is characterized by having a hard mask interface region with non-uniform pores sealed and thereby excluded functionally from the str...  
WO/2019/207354A1
An electronic product comprising a component having a first electrode comprising a first surface (103) and a pillar (104) extending from the first surface in a first direction, the pillar comprising three protrusions (106, 107, 108), the...  
WO/2019/208414A1
In order to provide a logic integrated circuit capable of writing and erasing data to and from a resistance change element requiring a high voltage without electrically destroying a micro-semiconductor element, the logic integrated circu...  
WO/2019/209440A1
A transistor comprises semiconductor material that is generally L-shaped or generally mirror L-shaped in at least one straight-line vertical cross-section thereby having an elevationally-extending stem and a base extending horizontally f...  
WO/2019/203169A1
To provide a switching element that has been miniaturized without an increase in manufacturing cost and for which switching voltage variation increase accompanying miniaturization has been suppressed, this semiconductor device comprises ...  
WO/2019/198410A1
A switch device according to an embodiment of the present disclosure is provided with: a first electrode; a second electrode disposed facing the first electrode; and a switch layer disposed between the first electrode and the second elec...  
WO/2019/188457A1
[Problem] To provide a semiconductor device and multiply-accumulate operation device with which higher-density integration can be achieved by further reducing the installation area for each synapse. [Solution] Provided is a semiconductor...  
WO/2019/187032A1
A variable resistance element (1) comprises: a variable resistance layer (3) which can store and emit at least one type of ion, and the resistance of which changes in accordance with the amount of the at least one type of ion; an ion sto...  
WO/2019/190697A1
Co-placement of resistor and other devices to improve area and performance is disclosed. In one implementation, a semiconductor circuit includes a resistor residing on a back end of line (BEOL) resistor layer, a plurality of interlevel m...  
WO/2019/181116A1
The titanium suboxide according to the present invention stores or dissipates heat through irradiation with light or an action of pressure or heat, and contains Ti3O5, which has a crystal structure that undergoes phase transition between...  
WO/2019/181314A1
The present invention provides a technique for improving the performance of a secondary battery. The secondary battery (100) of the present embodiment comprises: a first electrode (21); a second electrode (22); a first layer (11) that is...  
WO/2019/181273A1
A cross point element according to an embodiment of the present disclosure is provided with: a first electrode; a second electrode that is disposed oppositely to the first electrode; and a memory element, a selection element, and a resis...  
WO/2019/176833A1
In order to suppress moisture absorption in a variable resistance layer included in a variable resistance element and to reduce variations in set voltage, this semiconductor device is provided with: a first electrode; a first insulation ...  
WO/2019/167538A1
A switching element according to one embodiment of the present disclosure is provided with: a first electrode; a second electrode which is arranged so as to face the first electrode; and a switching layer which is arranged between the fi...  
WO/2019/168123A1
This nanogap electrode comprises: a first electrode which has a first electrode layer and a first metal particle that is arranged on one end of the first electrode layer; and a second electrode which has a second electrode layer and a se...  
WO/2019/155056A1
A power converter, such as a DC-DC converter or a power amplifier, embodied on a semiconductor substrate member (101), comprising: a first region (102) with a passive electrical component (104) with a first electrically conductive layer ...  
WO/2019/155083A1
The invention relates to a dielectric layer for interacting with two electrodes in order to form a capacitive device, the dielectric layer being a stack of superimposed sub-layers, each sub-layer having a thickness of less than 1 nanomet...  
WO/2019/146268A1
A storage element according to an embodiment of the present disclosure is provided with: a first electrode; a second electrode disposed opposite the first electrode; and a storage layer which is disposed between the first electrode and t...  
WO/2019/146534A1
In order to provide a logic integrated circuit having a reduced chip area, the present invention provides a logic integrated circuit comprising a switch cell array that has: a plurality of first wirings extending in a first direction; a ...  
WO/2019/140031A2
In a weak link of two s-wave superconductors (SCs) coupled via a time-reversal-invariant (TRI) topological superconducting (TSC) island, a Josephson current can flow due to Cooper pairs tunneling in and out of spatially separated Majoran...  
WO/2019/132939A1
Memory devices in which a memory cell includes a select transistor and a capacitor (1T-1C) include a 2D array of metal-insulator-metal (MIM) capacitors. A conductive shield may separate adjacent capacitors. The conductive shield may be h...  
WO/2019/132890A1
Ferroelectric memory devices with integrated capacitors and methods of manufacturing the same. An example memory device includes a semiconductor fin, and a transistor associated with a first portion of the semiconductor fin. The memory d...  
WO/2019/132876A1
This disclosure illustrates a FinFET based dual electronic component that may be used as a capacitor or a resistor and methods to manufacture said component. A FinFET based dual electronic component comprises a fin, source and drain regi...  
WO/2019/133275A1
A method used in forming at least a portion of at least one conductive capacitor electrode of a capacitor that comprises a pair of conductive capacitor electrodes having a capacitor insulator there-between comprises forming an insulative...  
WO/2019/132879A1
An apparatus is provided which includes: a first line and a second line, the first line and the second line separated by a space therebetween. In an example, a dielectric material and a third line is in the space between the first and se...  
WO/2019/132897A1
An apparatus is provided, which includes a stack of a first plurality of layers interleaved with a second plurality of layers. In an example, the first plurality of layers includes conductive material, and the second plurality of layers ...  
WO/2019/119127A1
Methods and techniques for fabricating layered structures, such as capacitive micromachined ultrasound transducers, as well as the structures themselves. The layered structure has a membrane that includes a polymer-based layer and a top ...  
WO/2019/125385A1
Capacitors are disclosed. A capacitor includes a plate-to-plate capacitor and a finger-to-finger capacitor. The plate-to-plate capacitor includes at least a first plate and a second plate. The second plate is in proximity to the first pl...  
WO/2019/118064A1
An integrated circuit (IC) includes a capacitor array in at least one first back-end-of-line (BEOL) interconnect level. The capacitor array includes a pair of capacitor manifolds coupled to parallel capacitor routing traces and capacitor...  
WO/2019/118227A1
Some embodiments include ferroelectric assemblies. Some embodiments include a capacitor which has ferroelectric insulative material between a first electrode and a second electrode. The capacitor also has a metal oxide between the second...  
WO/2019/110384A1
A rectenna device (400) for converting incident light to electrical energy is disclosed. The rectenna device comprises a substrate (402), a first metallic layer (404) having a predefined thickness deposited on top of the substrate, a rec...  
WO/2019/112576A1
Multi-period thin-film structures exhibiting giant magnetoresistance (GMR) are described. Techniques are also described by which narrow spacing and/or feature size may be achieved for such structures and other thin-film structures having...  
WO/2019/108360A1
Some aspects pertain to an inductor apparatus that includes a first metal layer including a plurality of first interconnects, a second metal including a plurality of second interconnects, a first dielectric layer between the first metal ...  
WO/2019/099066A1
Some embodiments include a capacitor. The capacitor has a first electrode with a lower pillar portion, and with an upper container portion over the lower pillar portion. The lower pillar portion has an outer surface. The upper container ...  
WO/2019/093724A1
The present invention provides a capacitance-based multi-layer synapse device and a manufacturing method therefor, the device comprising: a unit horizontal stacked structure in which horizontal conductive lines extending in a first direc...  
WO/2019/089154A1
According to certain aspects of the present disclosure, a semiconductor die includes a decoupling capacitor between a first interconnect metal layer and a second interconnect metal layer of the die, a first supply rail formed from the se...  
WO/2019/089916A1
A method of fabricating a semiconductor device comprises forming, within a single process flow on a silicon on insulator (SOI) wafer, at least one of an n channel, digital VeSFET, a p channel, digital VeSFET, an n channel, analog VeSFET ...  
WO/2019/082421A1
The purpose of the present invention is to provide a power storage device structure in which the number of stacked layers is less than that of a conventional power storage device. The power storage device according to the present inventi...  
WO/2019/080255A1
Provided are a transparent OLED display and a manufacturing method therefor. The method for manufacturing a transparent OLED display comprises: forming an active layer (40) and a first storage capacitor electrode (41) in the same process...  
WO/2019/081352A1
The invention relates to a method for producing an inductive electrical component by depositing layers of different materials on a substrate material. The layers form a functional layer, by means of which the electrical function of the i...  
WO/2019/077783A1
A filter (300) includes a circuit (330) including a resistor (301), a positive capacitor (303), and a virtual inductor via a negative capacitor (302) including a ferroelectric layer. The filter also includes an input terminal (310) to ac...  
WO/2019/078367A1
Provided is a memristor which can be manufactured at low temperature and does not include metals that could potentially dry up as a resource. The memristor 1 is provided with: a first electrode 2; a second electrode 3; and an oxide memri...  
WO/2019/070551A1
A damascene thin-film resistor (TFR), e.g., a damascene thin-film resistor module formed within a poly-metal dielectric (PMD) layer using a single added mask layer, and a method for manufacturing such a device, are disclosed. A method fo...  
WO/2019/070451A1
A capacitor may include a first conductive layer forming a first capacitor plate, a second conductive layer forming a second capacitor plate, and a first insulating material on the first conductive layer. The first insulating material ma...  
WO/2019/066963A1
Described is an apparatus which comprises: a word line; a source line; a bit-line; and a memory bit-cell coupled to the source line, the bit-line, and the word line, wherein the memory bit-cell comprises a capacitor including ferroelectr...  
WO/2019/066881A1
Spin transfer torque memory (STTM) devices incorporating an Insulator-Metal-Transition (IMT) device or at least one layer of Insulator-Metal-Transition (IMT) material are disclosed. The Insulator-Metal-Transition (IMT) device or at least...  
WO/2019/066765A1
A method for forming non-planar capacitors of desired dimensions is disclosed. The method is based on providing a three-dimensional structure of a first material over a substrate, enclosing the structure with a second material that is su...  
WO/2019/066468A1
The present invention relates to a method for manufacturing a laminated chip inductor having a fine-pitch line width and, more particularly, to a method for manufacturing a laminated chip inductor having a plurality of electrode patterns...  
WO/2019/060085A1
A process-invariant RC circuit is formed by patterning a metal layer using the same mask pattern to form a metal layer resistor and a metal layer capacitor. The same mask pattern results in the metal layer resistor and the metal layer ca...  
WO/2019/059118A1
The present invention provides a programmable logic integrated circuit with which it is possible to reduce leakage current while inhibiting increase in the number of connection wires and a consequent increase in occupied area. This logic...  

Matches 1 - 50 out of 8,420