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WO/2023/206738A1 |
The present disclosure relates to the technical field of semiconductors. Disclosed are a capacitor manufacturing method, a capacitor and a memory. The capacitor manufacturing method comprises: providing a substrate; forming a first elect...
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WO/2023/163749A1 |
A metal-insulator-metal (MIM) capacitor includes a bottom electrode cup, an insulator cup, and a top electrode. The bottom electrode cup includes a laterally-extending bottom electrode cup base, and a bottom electrode cup sidewall extend...
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WO/2023/103182A1 |
Provided in the present disclosure are a memory cell, and a memory and a manufacturing method therefor. The memory cell comprises a transistor, a storage node contact and a capacitor, which are sequentially connected. The capacitor compr...
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WO/2023/080346A1 |
The capacitor for a semiconductor device may comprise: a lower electrode comprising a first electrode layer and a second electrode layer; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric l...
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WO/2023/049582A1 |
Disclosed are devices having a metal-insulator-metal (MIM) capacitor and methods for fabricating the devices. The MIM capacitor includes a plurality of trenches in a Silicon (Si) substrate; a porous Si surface formed in the plurality of ...
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WO/2023/035545A1 |
Disclosed are a metal-insulator-metal capacitor structure and a preparation method therefor. The metal-insulator-metal capacitor structure comprises: a substrate; a capacitor structure comprising a bottom metal layer, an interlayer diele...
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WO/2023/014446A1 |
Examples described in this disclosure relate to gating a semiconductor layer into a quantum spin Hall insulator state. Certain examples further relate to using quantum spin Hall insulators as topological quantum qubits. Quantum spin Hall...
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WO/2023/000472A1 |
The present disclosure relates to the technical field of semiconductors. A semiconductor structure and a manufacturing method of a semiconductor structure are provided. The semiconductor structure comprises: a substrate; multiple lower e...
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WO/2023/000373A1 |
Provided in the embodiments of the present application are a preparation method for a semiconductor structure, a semiconductor structure, and a capacitor structure. The preparation method comprises: providing a substrate having a plurali...
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WO/2023/003749A1 |
Some embodiments include an integrated assembly having a first bottom electrode adjacent to a second bottom electrode. An intervening region is directly between the first and second bottom electrodes. Capacitor-insulative-material is adj...
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WO/2023/003731A1 |
Some embodiments include an integrated assembly having first and second pillars of semiconductor material. The first pillar includes a first source/drain region, and the second pillar includes a second source/drain region. First and seco...
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WO/2023/287457A1 |
A damascene method for manufacturing a thin film resistor (TFR) module is provided. A pair of heads are formed spaced apart from each other. A dielectric region is deposited over the pair of heads, and an opening extending over both head...
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WO/2023/284049A1 |
The present disclosure provides a fabrication method for a semiconductor structure and a semiconductor structure. The fabrication method for a semiconductor structure comprises: providing an initial structure, the initial structure compr...
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WO/2022/262061A1 |
A polysilicon resistor and a manufacturing method therefor, and a successive approximation analog-to-digital converter. When a polysilicon resistor is formed, the features of silicon-on-insulator processing are used to divide an upper si...
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WO/2022/263003A1 |
The invention concerns an optoelectronic arrangement that includes an optoelectronic component comprising a layer stack with an active area arranged between a layer of a first conductive type and a layer of a second conductive type. The ...
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WO/2022/265729A1 |
A three dimensional (3D) inductor is described. The 3D inductor includes a first plurality of micro-through substrate vias (TSVs) within a first area of a substrate. The 3D inductor also includes a first trace on a first surface of the s...
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WO/2022/260705A1 |
Ferroelectric random access memory (FRAM) capacitors and methods of forming FRAM capacitors are provided. An FRAM capacitor may be formed between adjacent metal interconnect layers or between a silicided active layer (e.g., including MOS...
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WO/2022/250400A1 |
The present invention relates to a semiconductor thin film-forming metal precursor compound represented by chemical formula 1 and a metal-containing thin film formed using same.
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WO/2022/247013A1 |
The present application relates to the technical field of storage devices. Provided are a memory manufacturing method, and a memory, which are used for solving the technical problems of a first polar plate being easily damaged, and the y...
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WO/2022/246351A1 |
Deep trench capacitors (DTCs) in an inter-layer medium (ILM) on an interconnect layer of an integrated circuit (IC) die is disclosed. A method of fabricating an IC die comprising DTCs in the ILM is also disclosed. The DTCs are disposed o...
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WO/2022/243656A1 |
The disclosure relates to integrated circuits and methods of manufacture. A method involves forming a first set of one or more circuit layers (102a, 104) on a semiconductor substrate (101), placing at least one prefabricated layer portio...
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WO/2022/240814A1 |
A semiconductor-based capacitor can include a substrate including a semiconductor material, an oxide layer formed over the substrate, a conductive layer formed over at least a portion of the oxide layer, a plurality of distinct coplanar ...
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WO/2022/229159A1 |
Electroacoustic devices (502) with a capacitive element (504) and methods for fabricating such electroacoustic devices. An example method includes forming an acoustic device (502) above a first region (506b) of a substrate, and forming a...
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WO/2022/223195A1 |
The invention comprises a semiconductor die (2) comprising a base body (20) comprising a semiconductor material, a surface with two contact areas (4) provided with contact pads (6) at which the die (2) can be contacted electrically and t...
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WO/2022/226456A1 |
A metal oxide metal (MOM) capacitor and methods for fabricating the same are disclosed. The MOM capacitor includes a first metal layer having a first plurality of fingers, each of the first plurality of fingers configured to have alterna...
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WO/2022/220867A1 |
A metal-insulator-metal (MIM) capacitor includes (a) a bottom electrode including (i) a bottom electrode plate and (ii) a bottom electrode cup formed from a conformal fill metal, (b) an insulator cup formed on the bottom electrode cup, (...
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WO/2022/217169A1 |
Disclosed is apparatus including a vertical spiral inductor. The vertical spiral inductor may include a plurality of dielectric layers formed on a substrate, a plurality of conductive layers, each of the plurality of conductive layers di...
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WO/2022/204663A1 |
The disclosed technology generally relates to forming a thin film comprising titanium nitride (TiN), and more particularly to forming by a cyclical vapor deposition process the thin film comprising (TiN). In one aspect, a method of formi...
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WO/2022/203791A1 |
Stacks of electrically resistive materials and related apparatuses, electrical systems, and methods are disclosed. An apparatus includes one or more resistor devices including a substrate, first and second electrically resistive material...
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WO/2022/201744A1 |
This nonvolatile storage device comprises a first electrode, a switch layer, and a second electrode. The second electrode is arranged facing the first electrode. The switch layer is arranged between the first electrode and the second ele...
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WO/2022/195020A1 |
A device comprises a substrate and a heat source structure, which is connected to the substrate and is designed to provide an amount of heat. Furthermore, a porous body comprising interconnected particles is provided, wherein intermediat...
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WO/2022/197324A1 |
An integrated circuit structure includes a metal-insulator-metal (MIM) capacitor and a thin-film resistor (TFR) formed concurrently, using components of shared material layers. A first metal layer may be patterned to form lower component...
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WO/2022/191919A1 |
An inductor includes a first metallization layer multi-turn trace. The inductor also includes a second metallization layer multi-turn trace coupled to the first metallization layer multi-turn trace through at least one first via. The ind...
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WO/2022/187969A1 |
The disclosure is directed at a CMOS-like logic gate including a set of thin-film transistors (TFTs), the set of TFTs including a subset of pull down TFTs, a subset of diode-connected TFTs and an output pull-up transistor; and a capacito...
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WO/2022/188342A1 |
Embodiments of the present application provide a semiconductor structure and a manufacturing method therefor. The manufacturing method for a semiconductor structure comprises: providing a substrate; forming a lower electrode layer on the...
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WO/2022/185014A1 |
The invention relates to a capacitor (10) comprising a stack of layers (1) made of a semiconductor material having a band gap energy greater than 2.3 eV, the stack of layers (1) comprising: an electrically insulating intermediate layer (...
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WO/2022/186937A1 |
An inductor can be formed in a coreless electronic substrate from magnetic materials and/or fabrication processes that do not result in the magnetic materials leaching into plating and/or etching solutions/chemistries, and results in a u...
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WO/2022/187283A1 |
A magnetic and electrical circuit element including magnetic-flux-conducting posts, and a multi-layer structure formed with an electrically-conductive material. The multi- layer structure includes multiple layers forming a stack of layer...
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WO/2022/182381A1 |
A thin-film resistor (TFR) module is formed in an integrated circuit device. The TFR module includes a pair of metal TFR heads (e.g., copper damascene trench structures), a TFR element formed directly on the metal TFR heads to define a c...
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WO/2022/177971A1 |
An integrated circuit includes a GaN FET and a metal-insulator-metal capacitor. The capacitor is fully integrated with a lateral GaN process flow, i.e., the same gate metal layer, field plate metal layer and dielectric layer of the GaN F...
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WO/2022/175273A1 |
A method for the manufacture of an improved graphene substrate and applications therefor There is provided a method (100) for the manufacture of an electronic device precursor, the method comprising: (i) providing a silicon wafer (200) h...
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WO/2022/167111A1 |
The invention relates to a high-current capacitor comprising: - a first film made of metal (1a) having a first microstructured and nanostructured surface produced by laser methods, - a first electron storage layer (3), also known as nano...
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WO/2022/170306A1 |
Mobile phones and other mobile devices communicate wirelessly by transmitting and receiving RF signals. Transmitters and receivers in wireless devices process RF signals in certain frequency ranges or bands. Signals in other frequencies ...
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WO/2022/166075A1 |
The present application relates to the technical field of semiconductors, and in particular, to a capacitor structure and a preparation method therefor, which are used for solving the technical problem of poor performance of the capacito...
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WO/2022/160625A1 |
The present disclosure relates to the technical field of semiconductors and provides a semiconductor structure and a manufacturing method for a semiconductor structure. The semiconductor structure comprises a substrate; a capacitor struc...
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WO/2022/163782A1 |
The present invention takes advantage of an electric property newly found in a conduction path formed in an electrolyte. An information processing apparatus 1 according to an embodiment of the present disclosure comprises a conversion un...
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WO/2022/158149A1 |
Provided is a nonvolatile storage device that is capable of high performance. This nonvolatile storage device comprises a first electrode, a memory material layer, a second electrode, and a first buffer layer. The memory material layer i...
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WO/2022/151122A1 |
The present disclosure provides a novel solid oxygen ion conductor based field effect transistor and a manufacturing method therefor. The field effect transistor comprises: a substrate; a gate dielectric layer, located on the substrate, ...
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WO/2022/151711A1 |
Provided are a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises a substrate, the substrate being provided with a first face and a second face which are opposite each other; a magnetic cor...
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WO/2022/154878A1 |
A device includes a main capacitor (410) composed of a first plate (412) of a first back-end-of-line (BEOL) metallization layer, a main insulator layer on the first plate, and a second plate on the main insulator layer. The second plate ...
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