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Matches 1 - 50 out of 8,219

Document Document Title
WO/2018/222342A1
A planar differential inductor reduces an effect of parasitics on common mode inductance of a voltage controlled oscillator (VCO) -based inductor to properly ground a common mode alternating current (AC) ground. In one instance, the plan...  
WO/2018/221114A1
A memory device according to an embodiment of the present disclosure comprises a logic circuit in which a plurality of wiring layers including layers that have different wiring pitches are laminated, and a memory element provided between...  
WO/2018/213208A1
A semiconductor power conversion device includes a plurality of device cells in different portions of the active area, each including a respective gate electrode. The device includes a gate pad having a plurality of integrated resistors,...  
WO/2018/207831A1
In order to output two potential values of a power supply voltage and a ground voltage and provide a reconfigurable logic integrated circuit having a small circuit area, this programmable logic circuit is provided with: a first switch; a...  
WO/2018/204017A1
A semiconductor device having a first die and a second die is provided. The first die of the device includes a first surface and a through-substrate via (TSV) extending at least substantially through the first die, the TSV having a porti...  
WO/2018/204015A1
A semiconductor device comprising first and second dies is provided. The first die includes a first through-substrate via (TSV) extending at least substantially through the first die and a first substantially helical conductor disposed a...  
WO/2018/204014A1
A semiconductor device comprising a substrate is provided. The device further comprises a through-substrate via (TSV) extending into the substrate, and a substantially helical conductor disposed around the TSV. The substantially helical ...  
WO/2018/203459A1
A selective element according to one embodiment of the present disclosure is provided with: a first electrode; a second electrode disposed opposite to the first electrode; a semiconductor layer that is provided between the first electrod...  
WO/2018/203887A1
Disclosed herein are vertical capacitors for integrated circuits (ICs), as well as related methods and devices. In some embodiments, a vertical capacitor may include at least two conductive plates on a support, with the conductive plates...  
WO/2018/193759A1
[Problem] To produce a variable resistance element having excellent electrical characteristics at low cost. [Solution] A method for producing a variable resistance element according to the present invention comprises the formation of a f...  
WO/2018/190241A1
A crossbar switch using a variable-resistance element corresponding to multiple fan-out, wherein in order to enable switch operation at high speed with high reliability, a switch circuit is used having: a plurality of four-terminal switc...  
WO/2018/190071A1
A storage device according to one embodiment of the present disclosure is provided with: a plurality of first wiring layers which extend in one direction; a plurality of second wiring layers which extend in another direction; and a plura...  
WO/2018/190951A1
A metal-insulator-metal (MIM) capacitor includes a compound semiconductor substrate. The MIM capacitor includes a collector contact layer on the compound semiconductor substrate, a first dielectric layer on the collector contact layer, a...  
WO/2018/187742A1
Disclosed are systems and methods for a quantum-analogue computing bit array consisting of a single qubit analogue, a serial two qubit analogue coupling, or parallel N qubit analogues. The quantum-analogue computing bit array comprises a...  
WO/2018/185115A1
The present application relates to a capacitor comprising a layer of semiconducting material between the electrode layers. Further, the present application relates to the use of such capacitors, for example in advanced electronic and sem...  
WO/2018/187258A1
A method (200A) and structure for improving high voltage breakdown reliability of a microelectronic device, such as a galvanic digital isolator, involves providing (214) an abatement structure around metal plate corners of a high voltage...  
WO/2018/183790A1
A system and method for fabricating metal insulator metal capacitors while managing semiconductor processing yield and increasing capacitance per area are described. A semiconductor device fabrication process places an oxide layer on top...  
WO/2018/181019A1
The present invention provides a resistance change element that improves set voltage variation between elements. Provided is a semiconductor device that includes at least two resistance change elements, a first terminal, and a second ter...  
WO/2018/181921A1
The present invention enables improvement of a set-forming yield while preventing insulation breakdown of a rectifying element when being set. In a plurality of switching cells, terminals on one side of two variable resistance elements a...  
WO/2018/180536A1
The purpose of the present invention is to provide a circuit capable of reducing leakage power in a programmable logic circuit using resistance change elements. To this end, the present invention is a programmable logic integrated circui...  
WO/2018/180228A1
A memory device according to an embodiment of the present disclosure comprises a memory cell array which is configured such that, when, of a plurality of memory cells, a plurality of first memory cells of which corresponding fourth wires...  
WO/2018/175754A1
A system and method for fabricating metal insulator metal capacitors while managing semiconductor processing yield and increasing capacitance per area are described. A semiconductor device fabrication process places a polysilicon layer o...  
WO/2018/174872A1
A switch capacitor bank structure, an integrated circuit die, and a method of fabricating the switch capacitor bank are disclosed. The switch capacitor bank structure includes a plurality of gallium nitride (GaN) transistors on a semicon...  
WO/2018/168494A1
An electricity storage device (30) is provided with: a first oxide semiconductor layer (14) of first conductivity type; a solid electrolyte layer (18K) which is disposed on the first oxide semiconductor layer (14) and which includes a so...  
WO/2018/148241A1
A capacitor structure may include a lower conducting layer (e.g., poly 1 layer) and an upper conducting layer (e.g., overlying poly 2 layer), which define an anode and cathode, and a dielectric layer (e.g., an ONO layer stack) located be...  
WO/2018/143986A1
Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a plurality of pillars, wherein individual pillars include a quantum well lay...  
WO/2018/134251A1
An electrolyte composition containing (i) at least one aprotic organic solvent; (ii) at least one conducting salt; (iii) at least one compound of formula (I); and (iv) optionally one or more additives.  
WO/2018/132252A1
A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first cap...  
WO/2018/132257A1
A method of forming an array of capacitors and access transistors there-above comprises forming access transistor trenches partially into insulative material. The trenches individually comprise longitudinally-spaced masked portions and l...  
WO/2018/126318A1
A process for purifying semiconducting single-walled carbon nanotubes (sc- SWCNTs) extracted with a conjugated polymer, the process comprising exchanging the conjugated polymer with an s-tetrazine based polymer in a processed sc-SWCNT di...  
WO/2018/123678A1
Provided is a metal-bridged-type resistance variable element in which a switching voltage and variations thereof are decreased, and which is suitable for high-density integration. The resistance variable element comprises: a metal precip...  
WO/2018/125110A1
In an example, there is disclosed a configurable impedance element, having: a first impedance network including a plurality of series impedance elements and providing an initial impedance; a trim impedance network parallel to the first i...  
WO/2018/124660A1
The present invention relates to a novel compound semiconductor, and the use thereof, wherein the novel compound semiconductor comprises: a Co-Sb skutterudite compound; Sn and S that are included in internal pores of the Co-Sb skutterudi...  
WO/2018/125060A1
An apparatus comprises one or more logic circuit blocks coupled between a supply voltage and ground and a decoupling capacitor coupled between the supply voltage and ground in parallel to the one or more logic circuit blocks, comprising ...  
WO/2018/126052A1
In various embodiments, a bonded structure is disclosed. The bonded structure can include an element and a passive electronic component having a first surface bonded to the element and a second surface opposite the first surface. The pas...  
WO/2018/123353A1
A laminated battery (1) relating to the present invention is a secondary battery wherein a first sheet-like battery (110a), a second sheet-like battery (110b), a third sheet-like battery (210a), and a fourth sheet-like battery (210b) are...  
WO/2018/125154A1
A transistor including a channel; a source and a drain formed; a gate electrode on the channel; and a spacer between the gate electrode and each of the source and the drain, wherein the sidewall spacer includes a concentration of a halog...  
WO/2018/117235A1
This semiconductor solid battery is characterized in that a first insulating layer is provided between an N-type semiconductor and a P-type semiconductor. Preferably, the first insulating layer has a film thickness of not less than 3 nm ...  
WO/2018/100790A1
A neuron circuit comprising: an input terminal to which spike signals are input in chronological order; a first switch element with one end connected to the input terminal and the other end connected to an intermediate node, the first sw...  
WO/2018/097924A1
A device and method of utilizing spiral interconnects for voltage and power regulation are shown. Examples of spiral interconnects include air core inductors. An integrated circuit package attached to a motherboard using spiral interconn...  
WO/2018/095824A1
An integrated electronic component (10) suitable for broadband biasing comprises a monolithic substrate (1), a capacitor structure arranged in a trench (3) network which extends into the substrate, and a continuous track (8) of an electr...  
WO/2018/085016A2
A method of forming an array comprising pairs of vertically opposed capacitors comprises forming an upwardly-open conductive lining in individual capacitor openings in insulative-comprising material. An elevational mid- portion of indivi...  
WO/2018/085022A1
A method of forming an array comprising pairs of vertically opposed capacitors comprises forming a conductive lining in individual capacitor openings in insulative-comprising material. An elevational mid-portion of individual of the cond...  
WO/2018/085016A3
A method of forming an array comprising pairs of vertically opposed capacitors comprises forming an upwardly-open conductive lining in individual capacitor openings in insulative-comprising material. An elevational mid- portion of indivi...  
WO/2018/066320A1
A switch element according to one embodiment of the present disclosure is provided with a first electrode, a second electrode that is arranged to face the first electrode, and a switch layer that is disposed between the first electrode a...  
WO/2018/063687A1
Embodiments are generally directed to non-planar on-package via capacitor. An embodiment of an embedded capacitor includes a first plate that is formed in a package via; a dielectric layer that is applied on the first plate; and a second...  
WO/2018/057227A1
An inductor is disclosed, including a first wire, a non-conductive material, and a shell. The non-conductive material may cover the first wire, with a portion of each end of the first wire uncovered. The shell may include a top portion a...  
WO/2018/057132A1
Apparatuses including compensation capacitors are described. An example apparatus includes: first, second and third capacitors arranged such that the second capacitor is sandwiched between the first and third capacitors, each of the firs...  
WO/2018/054828A1
A 3D-capacitor structure is based on a trench network which is etched from a top face (S100) of a substrate (100), and forms a regular array of separated pillars (10). The 3D-capacitor structure comprises a double capacitor layer stack w...  
WO/2018/057778A3
Integrated circuit layouts are disclosed that include metal layers with metal tracks having separate metal sections along the metal tracks. The separate metal sections along a single track may be electrically isolated from each other. Th...  

Matches 1 - 50 out of 8,219