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Matches 1 - 50 out of 8,364

Document Document Title
WO/2019/155056A1
A power converter, such as a DC-DC converter or a power amplifier, embodied on a semiconductor substrate member (101), comprising: a first region (102) with a passive electrical component (104) with a first electrically conductive layer ...  
WO/2019/155083A1
The invention relates to a dielectric layer for interacting with two electrodes in order to form a capacitive device, the dielectric layer being a stack of superimposed sub-layers, each sub-layer having a thickness of less than 1 nanomet...  
WO/2019/146268A1
A storage element according to an embodiment of the present disclosure is provided with: a first electrode; a second electrode disposed opposite the first electrode; and a storage layer which is disposed between the first electrode and t...  
WO/2019/146534A1
In order to provide a logic integrated circuit having a reduced chip area, the present invention provides a logic integrated circuit comprising a switch cell array that has: a plurality of first wirings extending in a first direction; a ...  
WO/2019/140031A2
In a weak link of two s-wave superconductors (SCs) coupled via a time-reversal-invariant (TRI) topological superconducting (TSC) island, a Josephson current can flow due to Cooper pairs tunneling in and out of spatially separated Majoran...  
WO/2019/132939A1
Memory devices in which a memory cell includes a select transistor and a capacitor (1T-1C) include a 2D array of metal-insulator-metal (MIM) capacitors. A conductive shield may separate adjacent capacitors. The conductive shield may be h...  
WO/2019/132890A1
Ferroelectric memory devices with integrated capacitors and methods of manufacturing the same. An example memory device includes a semiconductor fin, and a transistor associated with a first portion of the semiconductor fin. The memory d...  
WO/2019/132876A1
This disclosure illustrates a FinFET based dual electronic component that may be used as a capacitor or a resistor and methods to manufacture said component. A FinFET based dual electronic component comprises a fin, source and drain regi...  
WO/2019/133275A1
A method used in forming at least a portion of at least one conductive capacitor electrode of a capacitor that comprises a pair of conductive capacitor electrodes having a capacitor insulator there-between comprises forming an insulative...  
WO/2019/132879A1
An apparatus is provided which includes: a first line and a second line, the first line and the second line separated by a space therebetween. In an example, a dielectric material and a third line is in the space between the first and se...  
WO/2019/132897A1
An apparatus is provided, which includes a stack of a first plurality of layers interleaved with a second plurality of layers. In an example, the first plurality of layers includes conductive material, and the second plurality of layers ...  
WO/2019/119127A1
Methods and techniques for fabricating layered structures, such as capacitive micromachined ultrasound transducers, as well as the structures themselves. The layered structure has a membrane that includes a polymer-based layer and a top ...  
WO/2019/125385A1
Capacitors are disclosed. A capacitor includes a plate-to-plate capacitor and a finger-to-finger capacitor. The plate-to-plate capacitor includes at least a first plate and a second plate. The second plate is in proximity to the first pl...  
WO/2019/118064A1
An integrated circuit (IC) includes a capacitor array in at least one first back-end-of-line (BEOL) interconnect level. The capacitor array includes a pair of capacitor manifolds coupled to parallel capacitor routing traces and capacitor...  
WO/2019/118227A1
Some embodiments include ferroelectric assemblies. Some embodiments include a capacitor which has ferroelectric insulative material between a first electrode and a second electrode. The capacitor also has a metal oxide between the second...  
WO/2019/110384A1
A rectenna device (400) for converting incident light to electrical energy is disclosed. The rectenna device comprises a substrate (402), a first metallic layer (404) having a predefined thickness deposited on top of the substrate, a rec...  
WO/2019/112576A1
Multi-period thin-film structures exhibiting giant magnetoresistance (GMR) are described. Techniques are also described by which narrow spacing and/or feature size may be achieved for such structures and other thin-film structures having...  
WO/2019/108360A1
Some aspects pertain to an inductor apparatus that includes a first metal layer including a plurality of first interconnects, a second metal including a plurality of second interconnects, a first dielectric layer between the first metal ...  
WO/2019/099066A1
Some embodiments include a capacitor. The capacitor has a first electrode with a lower pillar portion, and with an upper container portion over the lower pillar portion. The lower pillar portion has an outer surface. The upper container ...  
WO/2019/093724A1
The present invention provides a capacitance-based multi-layer synapse device and a manufacturing method therefor, the device comprising: a unit horizontal stacked structure in which horizontal conductive lines extending in a first direc...  
WO/2019/089154A1
According to certain aspects of the present disclosure, a semiconductor die includes a decoupling capacitor between a first interconnect metal layer and a second interconnect metal layer of the die, a first supply rail formed from the se...  
WO/2019/089916A1
A method of fabricating a semiconductor device comprises forming, within a single process flow on a silicon on insulator (SOI) wafer, at least one of an n channel, digital VeSFET, a p channel, digital VeSFET, an n channel, analog VeSFET ...  
WO/2019/082421A1
The purpose of the present invention is to provide a power storage device structure in which the number of stacked layers is less than that of a conventional power storage device. The power storage device according to the present inventi...  
WO/2019/080255A1
Provided are a transparent OLED display and a manufacturing method therefor. The method for manufacturing a transparent OLED display comprises: forming an active layer (40) and a first storage capacitor electrode (41) in the same process...  
WO/2019/081352A1
The invention relates to a method for producing an inductive electrical component by depositing layers of different materials on a substrate material. The layers form a functional layer, by means of which the electrical function of the i...  
WO/2019/077783A1
A filter (300) includes a circuit (330) including a resistor (301), a positive capacitor (303), and a virtual inductor via a negative capacitor (302) including a ferroelectric layer. The filter also includes an input terminal (310) to ac...  
WO/2019/078367A1
Provided is a memristor which can be manufactured at low temperature and does not include metals that could potentially dry up as a resource. The memristor 1 is provided with: a first electrode 2; a second electrode 3; and an oxide memri...  
WO/2019/070551A1
A damascene thin-film resistor (TFR), e.g., a damascene thin-film resistor module formed within a poly-metal dielectric (PMD) layer using a single added mask layer, and a method for manufacturing such a device, are disclosed. A method fo...  
WO/2019/070451A1
A capacitor may include a first conductive layer forming a first capacitor plate, a second conductive layer forming a second capacitor plate, and a first insulating material on the first conductive layer. The first insulating material ma...  
WO/2019/066963A1
Described is an apparatus which comprises: a word line; a source line; a bit-line; and a memory bit-cell coupled to the source line, the bit-line, and the word line, wherein the memory bit-cell comprises a capacitor including ferroelectr...  
WO/2019/066881A1
Spin transfer torque memory (STTM) devices incorporating an Insulator-Metal-Transition (IMT) device or at least one layer of Insulator-Metal-Transition (IMT) material are disclosed. The Insulator-Metal-Transition (IMT) device or at least...  
WO/2019/066765A1
A method for forming non-planar capacitors of desired dimensions is disclosed. The method is based on providing a three-dimensional structure of a first material over a substrate, enclosing the structure with a second material that is su...  
WO/2019/066468A1
The present invention relates to a method for manufacturing a laminated chip inductor having a fine-pitch line width and, more particularly, to a method for manufacturing a laminated chip inductor having a plurality of electrode patterns...  
WO/2019/060085A1
A process-invariant RC circuit is formed by patterning a metal layer using the same mask pattern to form a metal layer resistor and a metal layer capacitor. The same mask pattern results in the metal layer resistor and the metal layer ca...  
WO/2019/059118A1
The present invention provides a programmable logic integrated circuit with which it is possible to reduce leakage current while inhibiting increase in the number of connection wires and a consequent increase in occupied area. This logic...  
WO/2019/049980A1
In order to achieve both high-density implementation of applications in the form a reconfiguration circuit without a redundancy bit and the capability to continuously run applications with redundancy, the present invention is a reconfigu...  
WO/2019/046019A1
Several embodiments of the present technology are directed to semiconductor devices, systems including semiconductor devices, and methods of making and operating semiconductor devices. In some embodiments, a semiconductor device comprise...  
WO/2019/043206A1
The disclosed device comprises a thin film layer (4) of a phase transition material disposed over a substrate (2), and a confinement layer (3) adjacent to the thin film layer. The thin film layer has first and second in-plane lattice par...  
WO/2019/032789A1
Methods of processing a substrate include providing a substrate having a polymer dielectric layer and a metal layer formed atop the polymer dielectric layer; depositing a plurality of polymer layers atop the substrate; patterning the plu...  
WO/2019/032700A1
A method of forming a magnetic core on a substrate having a stacked inductor coil includes etching a plurality of polymer layers to form at least one feature through the plurality of polymer layers, wherein the at least one feature is di...  
WO/2019/023171A1
A method is provided for forming an integrated thin film resistor (TFR) in a semiconductor integrated circuit device. A first dielectric layer is deposited on an integrated circuit (IC) structure including conductive contacts, a resistiv...  
WO/2019/020494A1
A method for producing a porous metallic structure comprising a metal element from a metal salt comprising a cation part and an anion part, comprising the steps of: providing a volume of metal salt; exposing the volume of metal salt in a...  
WO/2019/016587A1
An integrated resistor-capacitor (RC) structure (400) is disclosed. The integrated RC structure includes a vertical capacitor (302, 402, 306) and a resistive element (308, 310) disposed above the capacitor. The integrated RC structure us...  
WO/2019/016627A1
A semiconductor device includes a substrate, a gate arranged on the substrate, a dielectric arranged on the gate, a channel arranged on the dielectric, a source electrically coupled to the channel, and a drain electrically coupled to the...  
WO/2019/009296A1
[Problem] To stabilize the transition of a resistance variable element from a low resistance state to a high resistance state. [Solution] This switch element includes a resistance variable element, a first transistor, and a second transi...  
WO/2019/009005A1
Provided is a technique that enables a secondary battery to have a desired size. A secondary battery (10) according to one embodiment of the present disclosure is provided with: a base material (11); a charge layer (14) which is formed o...  
WO/2019/005002A1
There is disclosed in one example a level shifter, including: a first ferroelectric capacitor; an input voltage signal applied to a first node of the first ferroelectric capacitor; a second capacitor; and an output voltage signal at a sh...  
WO/2019/005143A1
Described is an apparatus which comprises: a first metal layer; a second metal layer; and two or more layers coupled between the first and second metal layers, wherein the two or more layers include a first layer comprising a conductive ...  
WO/2019/005174A1
An apparatus is provided which comprises: a source to provide a sinusoidal signal; a capacitor comprising ferroelectric material, the capacitor coupled to the source; and a device coupled in series with the capacitor. An apparatus is als...  
WO/2019/005020A1
Embodiments of the invention include a microelectronic device that includes a plurality of organic dielectric layers and a piezoelectrically actuated tunable capacitor having a variable capacitance formed in-situ with at least one organi...  

Matches 1 - 50 out of 8,364