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Patent Searching and Data


Matches 451 - 500 out of 551,710

Document Document Title
WO/2018/087717A1
A method of decoding a polar coded signal includes determining channel reliabilities for a plurality of polar coded bit channels in a data communication system including a plurality of frozen bit channels and non-frozen bit channels, sel...  
WO/2018/089164A1
The present disclosure describes aspects of a fast settling peak detector. In some aspects, a peak detector circuit includes a first transistor having a gate coupled to an input of the circuit at which a signal is received and a drain co...  
WO/2018/087374A1
A semiconductor module (56) comprises reverse conducting IGBT (10, 10') connected in parallel with a wide bandgap MOSFET (32), wherein each of the reverse conducting IGBT (10, 10') and the wide bandgap MOSFET (32) comprises an internal a...  
WO/2018/089121A2
A frequency divider system and method includes a split-divisor frequency divider module. The split-divisor frequency divider module receives a clock signal and generates an output signal based on a first divisor and a second divisor. The...  
WO/2018/088923A1
A method for quasi-cyclic low-density parity-check (QC-LDPC) encoding and decoding of a data packet by a lifted matrix is provided, the method comprising: lifting the QC-LDPC code for maximal code length Nmax and maximal circulant size Z...  
WO/2018/087260A1
The invention relates to a power distributor (2), in particular for an on-board network (4) of a motor vehicle (6), having an intermediate tap (16), two power outputs (10), and one each switching unit (28) for each power output (10), and...  
WO/2018/088373A1
Provided are a bias circuit that can supply a bias voltage for suppressing the influence of process fluctuation on an amplification circuit, and an amplification apparatus that uses the bias circuit. A bias circuit 11 is provided with: a...  
WO/2018/086972A1
The present disclosure relates to apparatuses and a method for wireless health monitoring comprising dynamically adjusting sound data compression level and/or transmission bandwidth of transmission between a mobile transmitter and a rece...  
WO/2018/089150A3
A transmit driver is configured to operate under distinct supply voltage provided at output differential terminals. The transmit driver includes differential input transistors, first and second pairs of over-voltage protection differenti...  
WO/2018/087189A1
The invention concerns a circuit (100) able to perform a simultaneous impedance matching between a generator (G) and a load (CH) for a power supply signal having at least two distinct frequencies, comprising: - an impedance matching stag...  
WO/2018/084732A1
´╗┐Provided is a IR-HARQ scheme comprising determining a first low-density-parity-check, LDPC, matrix, wherein a second submatrix of the first LDPC matrix has a dual diagonal structure, determining a codeword based on a sequence of infor...  
WO/2018/082656A1
A resistance-segmented-type analog to digital converter comprises: a most significant bit (MSB) resistor string (104) comprising a high level resistor string, an intermediate level resistor string and a ground level resistor string; a de...  
WO/2018/082329A1
A check matrix generation method and device. The method comprises: initializing a rule check matrix, wherein each row of the rule check matrix accords to a same degree distribution (S101); adjusting the degree of columns of the rule chec...  
WO/2018/085032A1
Certain aspects of the present disclosure generally relate to methods and apparatus for layered decoding of low density parity check (LDPC) codes, and more particularly to early termination techniques for low-density parity-check (LDPC) ...  
WO/2018/085596A1
In described examples, an apparatus (600) includes: a first power transistor (B-FET) having a first current conduction path coupled between an input (VIN) for receiving a supply voltage and a node (VMID) and a first gate terminal coupled...  
WO/2018/082300A1
Provided are a wireless transmitter and a control method therefor, and a computer storage medium. The wireless transmitter comprises a phase lock module and a power amplifier, wherein the phase lock module is configured to perform up-fre...  
WO/2018/084981A1
A circuit including: a power amplifier configured to provide amplified signals to a load; an impedance matching network disposed between the power amplifier and the load, the impedance matching network comprising an adjustable impedance ...  
WO/2018/083797A1
A differential amplification circuit (11) is provided with: differential input terminals (INa, INb); first and second amplification transistors (M1, M2); a common connection node (21c) electrically connected to source electrodes of the f...  
WO/2018/084774A1
A spin oscillator device (1) comprising a first spin Hall effect nano-oscillator, SHNO (2), having an extended multilayered magnetic thin-film stack (2), wherein a nano-constriction, NC, (6) is provided in said magnetic film stack (2) pr...  
WO/2018/081883A1
Method and implementation of a detector of rapid pulses in the power supply voltage of integrated circuits, which involves conditioning the rapid pulse applied to the power supply voltage to trigger the security alarm, more specifically ...  
WO/2018/083387A1
The parallel reception system (SYS) comprises a plurality of receiving devices (DIS1-DISN), each comprising an amplifying circuit (CA) in a frequency transformation stage coupled with the antenna and configured to perform a frequency tra...  
WO/2018/082650A1
Concepts and schemes pertaining to information coding for mobile communications are described. A processor of an apparatus encodes data to provide encoded data. The processor also transmits the encoded data to a network node of a wireles...  
WO/2018/082299A1
A Ku band frequency conversion circuit and a frequency converter, comprising a first radio frequency amplification module (10), a first filtering module (20), a second radio frequency amplification module (30), a second filtering module ...  
WO/2018/083870A1
A current protection circuit (11, 24, 34, 44), provided with an MOS transistor (T1, T31), a current detector (8, 42), an off driving unit (9, 23), and a back gate control unit (7, 32). The MOS transistor is serially connected between an ...  
WO/2018/083893A1
The present invention improves the detection accuracy of a timing error in a semiconductor integrated circuit provided with a storage element that operates in synchronization with a clock signal. A delay unit delays a data signal by two ...  
WO/2018/083422A1
The invention relates to an anti-pinch system (10) for a motor-vehicle opening (20), this system including a capacitive sensor (40) and being characterised in that it includes at least one device (50) for protecting the detection field (...  
WO/2018/083647A1
According to certain embodiments, a transmit node in a wireless communications system includes a first universal rate-compatible polar encoder and a transmitter. The first universal rate-compatible polar encoder is configured for a famil...  
WO/2018/082811A1
The invention relates to the use of a field effect transistor in an open gate FET circuit, wherein the measurement sensitivity is increased in measurements of the smallest signals. This is achieved in that the field effect transistor is ...  
WO/2018/083907A1
A low pass filter, provided with: a coil 20 for which a band shaped conductor 22 is wound a plurality of times around a prescribed axis line 20a; a capacitor 30 for which one terminal is connected to the conductor 22, and the other termi...  
WO/2018/083039A1
An operating device for a vehicle component, in particular a human-machine interface (HMI) for vehicles is provided with a housing (10), which has a front wall that has a front face in particular with a display surface and a rear face fa...  
WO/2018/084889A1
An apparatus for detecting difference in operating characteristics of a main circuit by using a replica circuit is presented. In one exemplary case, a sensed difference in operating characteristics of the two circuits is used to drive a ...  
WO/2018/085268A1
A layer sequence is proposed that comprises first and second layers that are deposited atop one another in alternation, wherein the first layers (SC1, SC2) comprise SiC1 -xHx and the second layers (SOC1, SOC2) comprise SiOC(H).  
WO/2018/082286A1
Provided are an encoding and decoding method and apparatus for a serial communication system based on SerDes technology. The method comprises an encoding step: dividing 18-bit common data into two pieces of 9-bit original data; respectiv...  
WO/2018/085410A2
A method of increasing a multiplication ratio of a charge pump, the multiplication ratio defining a relationship between an output voltage of the charge pump and an input voltage of the charge pump, comprising: analyzing a first efficien...  
WO/2018/084956A1
Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity check (LDPC) codes, and more particularly to a deeply-pipelined layered LDPC decoder architecture for high decoding throu...  
WO/2018/083936A1
Provided is a multilayer LC filter which has desired frequency characteristics, while being reduced in height. This multilayer LC filter is configured such that: when a laminate 1 is perspectively viewed from the lamination direction of ...  
WO/2018/082290A1
Provided is an efficiently decodable QC-LDPC code which is based on a base matrix of an irregular QC-LDPC matrix, the base matrix being formed by columns and rows, the columns being dividable into one or more columns corresponding to pun...  
WO/2018/085047A1
Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity check (LDPC) codes, and more particularly to non-linear log-likelihood ratio quantization techniques for low-density pari...  
WO/2018/085396A1
In described examples, an electronic circuit system has an input (IN1) for receiving an analog signal (NPES) having a frequency and comprising noise. The noise includes input referred noise, and the noise fluctuates in a range. The syste...  
WO/2018/084735A1
Provided is an efficiently decodable QC-LDPC code which is based on a base matrix of an irregular QC-LDPC matrix, the base matrix being formed by columns and rows, the columns being dividable into one or more columns corresponding to pun...  
WO/2018/084617A1
Disclosed are a method for dividing a transport block of a low density parity check (LDPC) code and an apparatus therefor. A method for dividing a transport block of an LDPC code according to the present disclosure can improve the perfor...  
WO/2018/083637A1
A method of detecting possible living body contact at an electrical contact surface, wherein the living body has a detectable characteristic initial impedance and a corresponding characteristic time constant defined by the initial impeda...  
WO/2018/082977A1
The invention relates to a sheet arrangement (101) comprising: a first sheet (1) and a second sheet (2), which are interconnected by means of at least one intermediate layer (3); an electro-optical functional element (4) comprising a fir...  
WO/2018/084007A1
A magnetoresistive effect device 100 is characterized in having: an MR unit 20 having an input port 9a, an input-side signal line 7, magnetoresistive effect elements 1a, 1b, and a magnetic field generation signal line 18; and an output u...  
WO/2018/085410A3
A method of increasing a multiplication ratio of a charge pump, the multiplication ratio defining a relationship between an output voltage of the charge pump and an input voltage of the charge pump, comprising: analyzing a first efficien...  
WO/2018/084986A1
A loop compensation circuit (500) includes a differential difference amplifier having a first transconductance stage (514) with a first input terminal and a second input terminal. The first input terminal is coupled to a voltage referenc...  
WO/2018/076933A1
The solution is applicable to the field of radio frequency communications. Provided are a millimeter wave fundamental-frequency oscillating circuit and a millimeter wave oscillator. The circuit comprises: a bypass capacitor; an output ma...  
WO/2018/076160A1
A digital-to-analog converter (DAC) capacitor array and an analog-to-digital converter, and a method for reducing power consumption of an analog-to-digital converter, wherein the DAC capacitor array comprises a plurality of parallel conn...  
WO/2018/079485A1
Provided is an elastic wave device that has low susceptibility to defects such as cracking in an elastic wave element substrate, and has excellent reliability. An elastic wave device 1 has a surface acoustic wave element 3 mounted on a m...  
WO/2018/081353A1
System and method of timing recovery for recovering a clock signal with reduced interference with clock phase correction by an adaptive equalizer. The equalizer in the timing recovery loop is dynamically adapted to the current channel ch...  

Matches 451 - 500 out of 551,710