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WO/2018/192252A1 |
A digital pre-distortion processing method and apparatus, the method comprising: acquiring an input signal of a power amplifier and an output signal of the power amplifier (S201); updating a pre-distortion coefficient, according to the a...
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WO/2018/192243A1 |
A display driver device (100), a display driver component, and a display device. A display driver device (100), a display driver component, and a display device. The display driver device (100) comprises: a display controller (101, 301, ...
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WO/2018/191967A1 |
Embodiments of the present disclosure relate to a radio frequency (RF) power amplifier (PA) and a corresponding method, device and computer readable storage medium. In example embodiments, an envelope control circuit is arranged in a mod...
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WO/2018/193804A1 |
An amplified high-frequency signal from a pre-amp (10) is divided by a semi-coaxial high-frequency cavity power divider (30). A plurality of high-frequency signals obtained by means of the dividing are inputted into a post-amp (40), each...
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WO/2018/192674A1 |
A technique relates to a superconducting device. A first mixing device has a first mixing port and a second mixing port. A second mixing device has another first mixing port and another second mixing port. The first and second mixing dev...
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WO/2018/194970A1 |
A method for offset calibration may include decoupling a modulator input of a first path from a first stage output, coupling a second path output to the modulator input, applying a common-mode voltage to a second path input, receiving a ...
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WO/2018/192098A1 |
An interface circuit and an electronic device. The interface circuit comprises a power supply input end, an access recognition circuit (10), a voltage detection circuit (20), a switch circuit (30), a control circuit (40), and a power sup...
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WO/2018/193338A1 |
In accordance with the present disclosure, one embodiment includes a memristor that is caused to be in a particular resistance state by a voltage applied across terminals of the memristor. A first logical input and a second logical input...
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WO/2018/194538A1 |
A zero cross detection circuit is included in a system circuit for accurately detecting a zero cross event from an alternating current power source in the system circuit. The detecting zero cross event is monitored to accurately time a c...
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WO/2018/194977A1 |
Disclosed are electronic devices for detecting contact or close proximity to an object to be detected. An electronic device includes a capacitive sensor enclosed by a housing and a controller coupled to the capacitive sensor, where the c...
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WO/2018/193830A1 |
The present invention provides an elastic wave device capable of effectively suppressing an unnecessary wave even if a plurality of IDT electrodes having different electrode finger pitches are provided on the same piezoelectric substrate...
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WO/2018/194998A1 |
A deep neural network ("DNN") module can compress and decompress neuron-generated activation data to reduce the utilization of memory bus bandwidth. The compression unit can receive an uncompressed chunk of data generated by a neuron in ...
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WO/2018/193933A1 |
Provided is an elastic wave device with which it is possible to suppress stopband response. An elastic wave device 1 comprising a piezoelectric substrate 2 and an IDT electrode 6 provided on the piezoelectric substrate 2. The IDT electro...
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WO/2018/193707A1 |
[Problem] The purpose of the present invention is to provide an information processing device and the like with which it is possible to prevent an increase in circuit size. [Solution] This information processing device 1 is provided with...
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WO/2018/192640A1 |
The present invention concerns encoding devices and methods, and decoding devices and methods, wherein an encoding device comprises a first coder FC (31) configured to generate m FC-output- bit-sequences by in m polar coding blocks (31 1...
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WO/2018/195350A1 |
Some or all of a comparator circuit of an analog-to-digital converter (ADC) circuit can be efficiently repurposed or reused for residue amplification for efficient noise-shaping, e.g., in a noise-shaping feedback configuration. A preampl...
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WO/2018/193378A1 |
Embodiments include a logic gate system comprising a first micro-cantilever beam arranged in parallel to a second micro-cantilever beam in which a length of the first micro- cantilever beam is shorter than a length of the second micro-ca...
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WO/2018/193527A1 |
An overcurrent detection circuit (50) is provided with: a di/dt detection circuit (10) that detects di/dt of a current Ie flowing in an emitter of an IGBT (121); a control circuit (14) that detects whether or not the current Ie is an ove...
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WO/2018/194231A1 |
The present invention relates to a differential mode converting device and a measuring device using the same, and can comprise: a target resistor for measuring a resistance value; an input mode converting unit, which receives, in a singl...
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WO/2018/193161A1 |
An apparatus for generating a spatially extended audio signal, the apparatus configured to:analyse at least one audio signal to determine spectral content of the at least one audio signal;determine whether to spectrally extend the at lea...
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WO/2018/193724A1 |
An output circuit (100) is provided with: a transistor P1 having a source connected to VDDH and a gate to which a signal (SI1) is supplied; and a transistor P2 having a source connected to the drain of the transistor P1, a drain connecte...
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WO/2018/191908A1 |
Methods, systems, and devices for wireless communication are described for dynamic frozen bits of polar codes for early termination and performance improvement. A wireless device may receive a signal comprising a codeword encoded using a...
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WO/2018/194753A1 |
Various aspects of this disclosure describe measuring timing slack using an endpoint criticality sensor on a chip. A sensor circuit is attached to sensitive endpoints on the chip (e.g., logical gates in a timing critical path) so that th...
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WO/2018/193746A1 |
A radar system (1) is provided with: a transmitting unit (8) which transmits to a target T a radar wave corresponding to a gradually increasing/gradually decreasing chirp frequency; and a frequency converting unit (18) which subjects a r...
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WO/2018/193150A1 |
A sequential circuit with timing event detection is disclosed. The sequential circuit has an input that is asserted to the output during the second clock phase of a two phase clock signal. A timing event detector is coupled to the sequen...
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WO/2018/192790A1 |
The oscillator circuit comprises first and second integrator units (100, 200) with a first capacitor (110) charged at a first integration node (121) and a second capacitor (210) charged at a second integration node (221). A comparator un...
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WO/2018/190494A1 |
Disclosed are a fingerprint sensor module realized by placing a TFT array on a thin film using a process for manufacturing flexible displays, and a fingerprint recognition apparatus having same. The fingerprint sensor module comprises: a...
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WO/2018/191217A1 |
Integrated circuits described herein implement an x-input logic gate. The integrated circuit includes a plurality of Schottky diodes that includes x Schottky diodes and a plurality of source-follower transistors that includes x source-fo...
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WO/2018/188608A1 |
Embodiments of the present disclosure provide a combined multiplexer and a signal transmitting and receiving method therefor. The combined multiplexer is located in a wireless communication device. An antenna for transmitting and receivi...
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WO/2018/189234A1 |
A trifilar transformer (1000) comprising: a first (1001), a second (1002) and a third winding (1003), wherein one winding (1003) is mutually coupled to each of the other two windings (1001, 1002), and wherein said other two windings (100...
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WO/2018/188127A1 |
Disclosed is a storage interface. The storage interface is connected between a main controller and a storage device, and may comprise: a first programmable input/output unit, used for performing phase inversion on a clock signal output b...
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WO/2018/188017A1 |
A level conversion circuit and a fingerprint recognition device. The level conversion circuit comprises: a complementary signal generating unit (10), a high voltage pulse generating unit (20), and a converting and latching unit (30). The...
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WO/2018/188719A1 |
An integrated transformer arrangement for combining output signals of multiple differential power amplifiers to a single-ended load. The integrated transformer arrangement comprises a first transformer branch comprising an inductor loop....
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WO/2018/188946A1 |
A method for producing a high-frequency power at a predefined frequency, in particular between 3 and 180 MHz, which can be supplied to a plasma load (49), comprises the method steps of: a. generating an analogue signal by supplying digit...
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WO/2018/190915A1 |
This disclosure describes systems, methods, and devices related to acknowledgement in bonded channels. A device may determine one or more code words. The device may determine an interleaver configuration. The device may divide symbols ov...
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WO/2018/191080A1 |
A controller for use in a power converter includes a control circuit coupled to generate a low side drive signal to control switching of a low side switch, and generate an ON signal and an OFF signal in response to a feedback signal repr...
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WO/2018/191154A1 |
A circuit for slew rate control for a high-side switch is disclosed. The circuit comprises a sample and level-shift circuit. The sample and level-shift circuit is connected to the high-side switch. The circuit further comprises a samplin...
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WO/2018/188424A1 |
Multichannel signal encoding and decoding methods and a codec. The encoding method comprises: determining a down-mixed signal of a first channel signal and a second channel signal in a multichannel signal and reverberation gain parameter...
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WO/2018/191683A2 |
A circuit (300) includes series-coupled delay buffers (110a, 110b) and logic gates (310a, 310b). Each logic gate (310a, 310b) includes first and second inputs (330, 332). The first input (332) of each logic gate (310a, 310b) is coupled t...
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WO/2018/189312A1 |
A transmission apparatus, in particular for use in a Low Throughput Network, comprises an FEC encoder configured to encode payload data into FEC code words each having a predetermined code word length, and a frame forming section configu...
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WO/2018/190401A1 |
A digitalization device (1) of the present disclosure is provided with: a first pulse delay unit (10); a second pulse delay unit (20); and a summing output unit (40). The first pulse delay unit is provided with a plurality (two to the nt...
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WO/2018/189288A1 |
An asynchronous state machine (30) for a phase/frequency detector (12) operative in a phase locked loop (10) includes a short pulse suppression circuit (40, 50, 60, 70, 80) operative to suppress output pulses of duration on the order of ...
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WO/2018/188501A1 |
The present application provides a digital-to-analog converter capable of reducing quiescent current overhead and reducing static noise. The digital-to-analog converter comprises: a first current source module that is used to supply a cu...
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WO/2018/191683A3 |
A circuit (300) includes series-coupled delay buffers (110a, 110b) and logic gates (310a, 310b). Each logic gate (310a, 310b) includes first and second inputs (330, 332). The first input (332) of each logic gate (310a, 310b) is coupled t...
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WO/2018/189579A1 |
The invention relates to a method for automatically adjusting one or more tunable passive antennas and a single-input-port and single-output-port tuning unit. The invention also relates to an apparatus for radio communication using this ...
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WO/2018/190890A1 |
A hand-held controller includes a handle extending in a longitudinal direction. The handle is shaped and dimensioned to be grasped by a user's hand. A trigger protrudes from an outer surface of the handle and moves relative to the handle...
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WO/2018/191119A2 |
An amplifier may include a final output stage switchable among a plurality of modes comprising a mode which is enabled by coupling an output driver to an output of the final output stage and a preconditioning circuit coupled to the outpu...
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WO/2018/191164A1 |
A gate driver circuit for driving a high-side switch is disclosed. The gate driver circuit comprises a sample and level-shift circuit. The sample and level-shift circuit is connected to the high-side switch. The gate driver circuit furth...
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WO/2018/188674A1 |
A novel key switch with a touch display function, comprising a base (1), and a lid (2) covering the base; an opening is formed on the lid (2); the base (1) and the lid (2) are combined to form an accommodating cavity; a guide core (3) an...
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WO/2018/189578A1 |
The invention relates to a method for automatically adjusting one or more tunable passive antennas and a single-input-port and single-output-port tuning unit. The invention also relates to an apparatus for radio communication using this ...
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