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Matches 701 - 750 out of 553,583

Document Document Title
WO/2018/126906A1
The present disclosure describes various examples of a method, an apparatus, and a computer-readable medium for wireless communications (e.g., 5G NR) using hybrid automatic repeat request (HARQ). For example, one of the methods includes ...  
WO/2018/129526A1
Aspects of the disclosure relate to a channel coding and decoding algorithm that provides for generalized polar codes, including the concatenation of a plurality of component codes via one-step polarization. In a further aspect, selectio...  
WO/2018/127730A1
A relaxation oscillator circuit includes a current mirror configured to receive the input current from the and generate a plurality of starved currents, a Schmitt trigger configured to be current starved by a first starved current of the...  
WO/2018/127725A1
A method of tuning antenna match is provided. The method may include providing a matching network of inductors and capacitors configured to match an impedance of an antenna, monitoring a voltage of the matching network, and adjusting an ...  
WO/2018/128420A1
The method and system for converging a 5th-generation (5G) communication system for supporting higher data rates beyond a 4th-generation (4G) system with a technology for internet of things (IoT) are provided. The method includes intelli...  
WO/2018/126427A1
A digital-to-analog converter (DAC) (100) for converting an M bit digital value to an analog signal includes a capacitive DAC (104) and a resistive DAC (116). The capacitive DAC (104) is configured to convert N most significant bits of t...  
WO/2018/127950A1
The present invention comprises: an internal-code error correction decoding unit (133) that generates a first decoded signal, for each unit frame, by performing error decoding of an internal code in respect to a received signal, and that...  
WO/2018/128367A1
Disclosed in the present specification is a method for performing channel encoding. The method can comprise the steps of: interleaving information bits; and encoding the interleaved information bits by using a polar code. The information...  
WO/2018/127788A1
Embodiments of the present disclosure provide methods and apparatuses for data processing in a communication system. For example, the method comprises: generating, based on an intended performance, an error detection code to be used; dis...  
WO/2018/127839A3
Triboelectric-based sensors used to receive touch-based input from a user and control electronic devices are described. A triboelectric-based sensors may also incorporate a haptic feedback device, such as an actuator, co-located on the s...  
WO/2018/129096A1
Systems and methods according to one or more embodiments are provided for a hum reduction circuit implemented to provide a ground path between an audio generating device and a powered headset. In one example, a system includes a jack con...  
WO/2018/127277A1
An oscillator circuit (10) for generating quadrature-related first and second oscillation signals having equal frequencies comprises a first oscillation circuit (VCO_I) configured to generate the first oscillation signal having a first c...  
WO/2018/127196A1
Concepts and schemes pertaining to shift coefficient and lifting factor design for NR LDPC code are described. A processor of an apparatus may generate a quasi-cyclic-low-density parity-check (QC-LDPC) code and encode data using the sele...  
WO/2018/126914A1
Provided are a method and device for coding of a quasi-cyclic low-density parity-check code, and a storage medium. The method comprises: determining an expansion factor z and a base check matrix Hb; and using the determined z and Hb to p...  
WO/2018/129305A1
Decoding and encoding methods, systems, and devices for wireless communication are described. One method may include receiving a codeword over a wireless channel, the codeword being encoded using a polar code, identifying a set of repeat...  
WO/2018/127729A1
A source follower for a capacitive sensor device having a sense node and a shield node is provided. The source follower may include a transistor, and a switch array selectively coupling the transistor between the sense node and the shiel...  
WO/2018/127094A1
The present application relates to a data transmission method and apparatus. The method comprises: a first device receives data from a second device, the data being borne on time-frequency resources; the first device receives instruction...  
WO/2018/127771A1
Systems and methods for multi-stage downlink control information transmission in a manner that supports existing polar codes are provided. In some embodiments, a method of operation of a radio access node in a cellular communications net...  
WO/2018/127183A1
A method of new radio physical broadcast channel (NR-PBCH) bit mapping is proposed to improve for NR-PBCH decoding performance under Polar codes. NR-PBCH carries 32 information bits and 24 CRC bits. Specifically, NR-PBCH uses 512-bit Pol...  
WO/2018/128764A1
Certain aspects of the present disclosure generally relate to a multi-output amplifier (400) implemented using a capacitive attenuator (414). For example, the multi-output amplifier (400) generally includes a first capacitive attenuator ...  
WO/2018/126840A1
Methods, systems, and devices for encoding and decoding are described. To encode a vector, an encoder allocates information bits of the vector to channel instances of a channel that are separated into groups. The groups may vary in size ...  
WO/2018/127607A1
According to certain embodiments, a method is provided for fast layered decoding for Low-density Parity-Check (LDPC) codes with a Parity-Check Matrix (PCM) that includes at least a first layer and a second layer. The method includes read...  
WO/2018/127198A1
A data processing method and device. The data processing method comprises: a transmitter determines, according to a data feature representing an information bit sequence to be transmitted and a preconfigured parameter corresponding to th...  
WO/2018/129452A1
A microcontroller includes an analog-to-digital (ADC) controller circuit, an ADC converter circuit, and a multiplexer configured to multiplex output of the ADC converter circuit and a data source to the ADC controller circuit.  
WO/2018/127723A1
An ADC method and system implement a comparison stage of SAR ADC directly in the analog domain rather than the digital domain, without resolving the output word Dout. This means that the number of comparisons, and thus the numbers of req...  
WO/2018/127726A1
A self-clocked SAR ADC sensor circuit includes an ADC having a capacitor array with a plurality of capacitors connected through a respective plurality of switches, a comparator, an SAR module, and a delay element circuit for ring oscilla...  
WO/2018/128236A1
Provided is a power supply device for plasma generation which supplies a high frequency signal amplified to have energy for plasma generation, the power supply device comprising: a frequency generator for generating a signal having a fre...  
WO/2018/127839A2
Triboelectric-based sensors used to receive touch-based input from a user and control electronic devices are described. A triboelectric-based sensors may also incorporate a haptic feedback device, such as an actuator, co-located on the s...  
WO/2018/128873A1
A receiver processes a data signal and provides an acknowledgement within a turnaround time through use of code block alignment, reduced complexity or increased processing time. In a first embodiment, a radio access network (RAN) node en...  
WO/2018/128506A3
In the configuration of a PEASK modulation/demodulation scheme, a low-power wideband pre-emphasis amplitude shift keying modulation/demodulation communication system can be provided, comprising: a pre-emphasis amplitude shift keying modu...  
WO/2018/126706A1
The present disclosure relates to a frequency-tunable frequency source and system, method and electronic apparatus related thereto, and in particular to a frequency-tunable frequency source having an input terminal for receiving an input...  
WO/2018/128435A3
A method for encoding a quasi-cyclic low-density parity-check (LDPC) code which supports a multi-base code according to an embodiment of the present invention includes: a step for selecting a base code for generating a parity-check matri...  
WO/2018/128968A1
A transmission line transformer (10) having a time delay network (12) having a signal terminal (16) and a pair of output terminals (221, 222) connected to the signal terminal through a corresponding one of a pair of time delay elements (...  
WO/2018/129147A1
Systems, methods, and instrumentalities are disclosed for error check-based synchronization. Physical Broadcast Channel (PBCH) data may be determined. A scrambling (e.g., a first scrambling) of the PBCH data may be scrambled via a sequen...  
WO/2018/128782A1
An integrated front-end module (FEM) includes at least one power amplifier (PA) coupled to an antenna without inclusion of a switching element in a transmit signal path in the FEM between an output of the PA and the antenna. The FEM furt...  
WO/2018/119741A1
A data access method, and flash memory apparatus. The flash memory apparatus can reduce the length of valid information bits in data to be encoded, and reconstruct the data to be encoded by padding with configured padding information whe...  
WO/2018/120346A1
A method and device for improving the output accuracy of a digital-to-analogue converter. The method comprises: calculating output errors of a digital-to-analogue converter according to the output accuracy and input errors of the digital...  
WO/2018/125516A1
A BAW resonator (1) comprises a piezoelectric layer (2) located between a top electrode (4) and a bottom electrode (3) and comprises a dielectric layer (9) located between the bottom electrode (3) and an additional electrode (11), wherei...  
WO/2018/123201A1
A differential-output D/A converter according to the present disclosure is provided with: decoders (2p, 2n) for converting inputted data into thermometer code; a positive-side capacitor array (3p, 3Ap, 3Bp, 3Cp) comprising a plurality of...  
WO/2018/125046A1
A divider-less fractional digital phase locked loop (PLL) is disclosed and can include a time-to-digital converter (TDC) to receive a reference clock signal and a digitally control oscillator (DCO) clock signal, and generate a phase diff...  
WO/2018/122848A1
This invention provides electromechanical resonators based on metal chalcogenide nanotubes. The invention further provides methods of fabrication of electromechanical resonators and methods of use of such electromechanical resonators.  
WO/2018/122866A1
The invention provides a universal semiconductor switch. The universal semiconductor switch includes a switching arrangement having an input and an output, at least one trigger circuit operably coupled to the switching arrangement and a ...  
WO/2018/125364A1
A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a Voltage Controlled Oscillator (VCO) signal; and a frequency estimation circuit configured to receive the quan...  
WO/2018/123382A1
A circuit module (101) is provided with: a substrate (1) having a main surface (1a); a first component (6) mounted on the main surface (1a); and a sealing resin section (3) that covers at least the side surface of the first component (6)...  
WO/2018/123609A1
The present disclosure pertains to an imaging element and a control method for the imaging element, an imaging device, and an electronic device that are capable of downsizing the imaging element and saving power of the imaging element. F...  
WO/2018/126130A1
A fixed frequency class-D audio amplifier (100) includes the L-C output filter (114) in a high order feedback loop. An audio amplifier integrated circuit (116) includes an output driver (112), an output terminal, a first input terminal, ...  
WO/2018/121469A1
Disclosed in the present invention are a system and a method for high-precision clock delay calibration. The calibration system comprises a NAND gate, an AND gate, a time delay chip, a multiplexer and a processing module; the multiplexer...  
WO/2018/125232A1
Aspects of a digital phase-lock loop (DPLL) with an adjustable delay between an output clock and a reference clock in accordance with phase noise compensation are generally described herein. An apparatus may include processing circuitry ...  
WO/2018/126142A1
A system (100) (and associated method) includes an input flip-flop (120), a counter (130), and a clock tree (110). The input flip-flop (120) includes a clock input terminal configured to be coupled to a device clock (90), or a clock gene...  
WO/2018/123447A1
Provided is an acoustic wave device in which internal interference between signals is suppressed. The acoustic wave device is provided with: a first element substrate 1 and a second element substrate 2 that are at least partially piezo-e...  

Matches 701 - 750 out of 553,583