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WO/2011/156379 |
A passive frequency divider in a CMOS process. More specifically, an electrical distributed parametric oscillator to realize a passive CMOS frequency divider with low phase noise. Instead of using active devices, which are the main sourc...
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WO/2011/154351 |
The present invention relates to a method and an apparatus for distance measurement between a first and a second station (S1; S2). In this case, this relates to reception of a second signal (SG2), which is sent by the second station (S2)...
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WO/2011/155095 |
Disclosed is an unbalanced to balanced converter, comprising a balanced transmission line, further comprising a pair of transmission lines (14, 15); an unbalanced transmission line (13); and two lead-out transmission lines (19, 20) that ...
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WO/2011/154674 |
A first detection circuit is provided comprising an optocoupler having an input for receiving an electrical signal and an output to which the electrical signal is transferred from the input; amplification means for amplifying the electri...
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WO/2011/155235 |
Disclosed are: a dual band surface acoustic wave filter which can be mounted on a circuit board together with a high-frequency switch to constitute a composite high-frequency component together with the high-frequency switch and which ca...
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WO/2011/154549 |
There is provided an amplifier arrangement comprising a main push pull amplifier (100) connected to receive an input signal and generate an amplified version of the input signal and an additional amplifier (624) that is a scaled down ver...
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WO/2011/154769 |
A server is caused to run-length encode grid regions of a grid, to which an applicability area of a set of data has been mapped, to obtain encoded information about the applicability area. The encoded information about the applicability ...
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WO/2011/155796 |
A method of de-mapping non-binary Galois field symbols from physical layer code-words in a data communication system, in which at least one physical layer code-word includes portions mapped from more than one non-binary Galois field symb...
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WO/2011/154459 |
A method for capacitive sensing comprises the steps of tagging a transmitting signal by modulating a sub-carrier on said signal using state of the art modulation techniques; demodulating said subcarrier out of useful/received signal to p...
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WO/2011/155893 |
Capacitive sensor system for a vehicle, which system comprises a signal generator, a signal detector and a processing device. The sensor system further comprises an earth antenna adapted to serving as a virtual external earth for the sys...
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WO/2011/156745 |
Preferred embodiments of the invention provide WOM coding methods and electronic devices with error correcting codes that provide single, double and triple error correction. Preferred codes of the invention also the following property: i...
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WO/2011/156745 |
Preferred embodiments of the invention provide WOM coding methods and electronic devices with error correcting codes that provide single, double and triple error correction. Preferred codes of the invention also the following property: i...
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WO/2011/155796 |
A method of de-mapping non-binary Galois field symbols from physical layer code-words in a data communication system, in which at least one physical layer code-word includes portions mapped from more than one non-binary Galois field symb...
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WO/2011/155891 |
Capacitive sensor system for a vehicle, comprising a chassis earth, a signal generator, a signal detector and a processing unit, the signal generator being adapted to generating a sensor signal with a frequency and an amplitude applied b...
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WO/2011/155390 |
Disclosed is an oscillation element wherein a magnetoresistive element provided with a tunnel barrier layer achieves both the high oscillation output and high Q value. Also disclosed is a method for manufacturing the oscillation element....
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WO/2011/156644 |
Programmable devices, hierarchical parallel machines and methods for providing state information are described. In one such programmable device, programmable elements are provided. The programmable elements are configured to implement on...
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WO/2011/156622 |
Methods and apparatus for a gray-coded phase rotating frequency divider. A phase selector is provided that includes two or more selectors, each selector configured to receive multiple clock phases and output a respective clock phase base...
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WO/2011/153776 |
A phase locked loop (PLL), voltage control device and voltage control method are provided. The PLL comprises a phase detector (402), a filter (404), a voltage control module (406) and an oscillator (408). The voltage control module (406)...
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WO/2011/154468 |
A capacitive sensing circuit is disclosed, wherein the transimpedance amplifier in front of the mixer in prior art is removed respectively replaced by an amplifier with low gain and consequently high dynamic range. The mixer DC offset vo...
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WO/2011/155007 |
In a power source detection circuit, a comparison circuit for detection (104) has inputted thereto an input signal (102) and a reference signal (103) by an input switching signal generating circuit (112) in order to compare both the inpu...
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WO/2011/156502 |
An improved rail-to-rail (R-R) input stage circuit with dynamic bias control is described. Input stage circuit includes a differential pair circuit, a level shifted differential pair and a bias control circuit. The differential pair circ...
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WO/2011/154467 |
A capacitive sensing circuit is disclosed, wherein the mixer is directly connected to the sense electrode. The AC transimpedance amplifier in front of the mixer in prior art is removed and replaced by a differential DC transimpedance amp...
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WO/2011/155333 |
When distributing various types of clock signals to a plurality of laminated semiconductor chips, the clock signals are efficiently supplied without reducing the selectivity of the clock signals. Clock signal selecting circuits (15, 18, ...
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WO/2011/154778 |
A method and a electronic circuit, the method includes: sending to a switching circuit, to a state retention power gating (SRPG) circuit and to a first power source a control signal indicating that the SRPG circuit should operate in a fu...
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WO/2011/154469 |
The present invention proposes to compensate the effect of the seat heater by either direct measurement of the current coupled into the seat heater or by indirect compensation by introducing an additional electrode into the system. This ...
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WO/2011/156379 |
A passive frequency divider in a CMOS process. More specifically, an electrical distributed parametric oscillator to realize a passive CMOS frequency divider with low phase noise. Instead of using active devices, which are the main sourc...
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WO/2011/154931 |
An integrated circuit, including, a die with an electronic circuit embedded thereon; wherein the electronic circuit includes a differential power amplifier and pads to electronically interface with the electronic circuit; a packaging enc...
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WO/2011/156644 |
Programmable devices, hierarchical parallel machines and methods for providing state information are described. In one such programmable device, programmable elements are provided. The programmable elements are configured to implement on...
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WO/2011/156393 |
These various embodiments serve to facilitate interlaced amplitude pulsing using a hard-tube type pulse generator having at least one energy-storage unit each comprising at least one energy-storing capacitor. Generally speaking, this com...
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WO/2011/154378 |
The present invention relates to a household appliance (1) comprising a control panel (2), more than one capacitive type touch sensor (3) integrated to the control panel (2), providing application of functions like opening, closing or ot...
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WO/2011/154763 |
An integrated circuit device (100) comprises at least one clock monitor (130). The at least one clock monitor (130) comprises a timer (210) arranged to receive a clock signal (120), generate a first timing signal (212) arranged to toggle...
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WO/2011/156607 |
Disclosed are circuits, techniques and methods for removing one or more harmonics from a waveform that has been mixed with a local oscillator. In one particular example, such a waveform may also be mixed with a second local oscillator at...
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WO/2011/155532 |
A flip-flop circuit (FF10) related to the present invention is provided with master latch circuits (LAT11 and LAT12), slave latch circuits (LAT13 and LAT14), C-element circuits (CE11 to CE14), and inverter circuits (INV11 to INV14). The ...
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WO/2011/154626 |
The present invention relates to a motor vehicle control interface comprising: a touch-sensitive tile (2) having a front face (3); a housing (4) housing said touch-sensitive tile (2), said housing (4) having - an opening delimited by an ...
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WO/2011/155600 |
In the disclosed oscillator, a wiring pattern that conducts with a pair of electrode pads, which electrically connect a piezoelectric vibrating reed, and a plurality of connection pads, which electrically connect the aforementioned piezo...
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WO/2011/156771 |
Integrated circuits that support dual-edge clocking are provided. Integrated circuits may include phase-locked loops that generate square-wave clock signals. The clock signals may be provided from off-chip equipment through input-output ...
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WO/2011/156038 |
A sub-VT FPGA uses a low swing, dual-VDD interconnect scheme to reduce FPGA area per LUT, delay at a constant energy, and energy at a constant delay relative to a conventional design at low voltage. These improvements are made possible b...
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WO/2011/156018 |
Techniques are disclosed for improving the dynamic performance of digital-to-analog converters (DAC), by compensating for the unique delay characteristics of each bit in the DAC summing junction to equalize the delays. In one example cas...
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WO/2011/156379 |
A passive frequency divider in a CMOS process. More specifically, an electrical distributed parametric oscillator to realize a passive CMOS frequency divider with low phase noise. Instead of using active devices, which are the main sourc...
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WO/2011/155863 |
A Viterbi decoder with a channel for evaluating the current signal-to-noise ratio which comprises, connected in series, a branch metrics calculation unit, a path metrics calculation and memory unit, a unit for generating an information s...
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WO/2011/156393 |
These various embodiments serve to facilitate interlaced amplitude pulsing using a hard-tube type pulse generator having at least one energy-storage unit each comprising at least one energy-storing capacitor. Generally speaking, this com...
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WO/2011/154774 |
An integrated circuit device (105, 405, 505) comprising at least one calibration module (170) for calibrating an impedance of at least one on-die interconnect line driver (120) in order to adaptively match an impedance between the at lea...
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WO/2011/156771 |
Integrated circuits that support dual-edge clocking are provided. Integrated circuits may include phase-locked loops that generate square-wave clock signals. The clock signals may be provided from off-chip equipment through input-output ...
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WO/2011/155144 |
Disclosed is a decoder capable of improving the sound quality of a decoded sound signal in an encoding method which combines encoding appropriate for speech signals and encoding appropriate for music signals in a hierarchical structure. ...
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WO/2011/152978 |
A radio frequency (RF) power amplifier system adjusts the supply voltage provided to a power amplifier (PA) adaptively, responsive to the measured or estimated power of the RF output signal of the PA. The RF PA system includes a power am...
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WO/2011/152083 |
An integrated circuit is provided with a first transimpedance amplifier and a second transimpedance amplifier. In the integrated circuit, either the first transimpedance amplifier or the second transimpedance amplifier is in an operation...
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WO/2011/151103 |
A circuit 1 comprises: an FPGA 2, which has an FLL circuit 5; a reference clock generator 4 of a first frequency or a reference clock input for receiving a reference clock of the first frequency; a programmable oscillator 3, which output...
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WO/2011/153333 |
Circuits comprising asynchronous linear pipelines and one-phase pipelines, and methods of forming asynchronous linear pipeline circuits and converting them to one-phase pipeline circuits are provided. Additional circuits, systems and met...
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WO/2011/152881 |
A method and apparatus is disclosed for voltage-controlled oscillator selection in a multi-mode system having multiple voltage-controlled oscillators. Part of oscillator selection is a calibration operation that utilizes maximum and mini...
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WO/2011/150760 |
Disclosed are a method, an apparatus and a system for transmitting information bits, relating to the field of communication technology. The method includes the following steps: coding, according to a coding matrix and a coding formula, A...
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