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Matches 101 - 150 out of 548,175

Document Document Title
WO/2018/000530A1
A calibration system and method for a voltage-controlled oscillator in a phase-locked loop. The calibration system comprises: a gain regulation unit which is connected to an input end of a voltage-controlled oscillator, and is used for i...  
WO/2018/004480A1
In the present invention, an analog input signal (X(n)) is processed by a Peak to Average Ratio Reduction (PARR) block to diminish the difference between peak amplitudes and average amplitudes of the analog input signal (X(n)). After, a ...  
WO/2018/002931A1
A system for wireless power transfer of on-road vehicles is provided herein. The system includes a plurality of base stations; a power transmission line located beneath a surface of a road having a plurality of segments, each segment hav...  
WO/2018/005795A1
A dynamic matching system for plasma generation that maintains a near-constant driving point impedance across an entire plasma operating range is provided. The matching system includes a Resistance Compression Network (RCN), impedance tr...  
WO/2018/000330A1
A method and system for preprocessing a signal of an electronic chip. The method comprises the following steps: sampling signal data of an electronic chip (101); analyzing and processing the sampled data to acquire the rate of change of ...  
WO/2018/000839A1
A new on-line monitoring unit for an ultra-wide voltage and a control circuit therefor. Compared with an ordinary on-line monitoring unit, it is not necessary to reserve a delay unit to replace an original trigger in the ordinary on-line...  
WO/2018/002504A1
The invention relates to a hybrid structure (100) for a surface acoustic wave device, comprising a useful layer (10) of piezoelectric material having a free first surface (1) and a second surface (2) disposed on a support substrate (20) ...  
WO/2018/001595A1
The application is related to a forward error correction mechanism in an optical coherent communication system (CS) comprising a FEC encoder (FE) and a FEC decoder (FD) on the basis of a low density parity check, LDPC, code. The FEC enco...  
WO/2018/001667A1
The invention relates to a method for synchronizing an inspection device (10), wherein the inspection device (10) is designed to test at least one first control device and the inspection device (10) comprises at least: one first computin...  
WO/2018/004807A1
A latch-based power-on checker (POC) circuit for mitigating potential problems arising from an improper power-up sequence between different power domains (e.g., core and input/output (I/O)) on a system-on-chip (SoC) integrated circuit (I...  
WO/2018/005727A1
Methods and apparatus for a body diode conduction sensor configured for coupling to a switching element. In embodiments, the sensor comprises first and second voltage divider networks coupled to a voltage source and a diode coupled to th...  
WO/2018/002745A1
The invention relates to a method of automatic adjustment of a single-input-port and single-output-port tunable matching circuit, for instance a single-input-port and single-output- port tunable matching circuit coupled to an antenna of ...  
WO/2018/004941A1
An integrated circuit for implementing a Reed-Solomon encoder circuit is provided. The encoder circuit may include partial syndrome calculation circuitry and matrix multiplication circuitry. The partial syndrome calculation circuitry may...  
WO/2018/004986A1
A transmitter (100) is provided with a plurality of pull-up legs (165) and a plurality of pull-down legs (170). A controller (140) controls the pull-up legs and the pull-down legs so that a constant output impedance is provided while sup...  
WO/2018/001146A1
A ring voltage-controlled oscillator, comprising: a conversion unit (100), a plurality of stages of cascaded delay units (200) and a plurality of stages of cascaded isolation buffering units (300). The conversion unit (100) receives a vo...  
WO/2018/002723A1
The present invention relates to a lighting laminated glazing (100) comprising: • - a first transparent glazing (1), preferably of mineral glass; • - a second glazing (1'), preferably of mineral glass; • - an intermediate layer (8)...  
WO/2018/001376A1
Provided is a harmonic suppression method, a corresponding low-noise amplifier (20, 30, 40), and a communication terminal. In the harmonic suppression method, an isolation unit (23, 33, 43) is arranged between a harmonic suppression unit...  
WO/2018/004496A1
The present invention relates to latch circuit (1) which is connected between a power source and a load, which can be adjusted such that it will be latched/not latched depending on the configuration of the switches during application of ...  
WO/2018/003378A1
A filter device (2) is provided with: a first filter (20) configured from series resonators and parallel resonators; a first inductor (L1) connected in parallel between a first terminal (11) and the first filter (20); a second inductor (...  
WO/2018/003268A1
Provided is a ladder-type elastic wave filter device (21) comprising parallel resonators (151-154) and series resonators (101-105) configured from an IDT electrode (22) that is formed on a substrate (220) having a piezoelectric layer (22...  
WO/2018/004826A1
A processing system, and associated input device and method are disclosed suitable for reducing a receiver size within the input device. The processing system comprises a delta-sigma modulator comprising one or more input nodes configure...  
WO/2018/005342A1
In an example, there is disclosed an apparatus, comprising: a data store comprising a hash table having for at least some rows a hash entry indexed by a hash value, and comprising a hash chain of one or more pointers to a history buffer,...  
WO/2018/003273A1
A quadplexer (1) is provided with a filter (12) and a filter (22) having a higher passband frequency than the filter (12). The filter (12) comprises series resonators (121s-125s) arranged on a first route and parallel resonators (121p-12...  
WO/2018/004800A1
An apparatus is described. The apparatus includes a stacked switch circuit having protection circuitry to prevent shoot through current when the switch is in an off state and respective voltages at the terminals of the switch change such...  
WO/2018/001453A1
A variable gain amplifier (1) is configured to amplify an input signal (Ivga_ in) with a variable gain, resulting in a linear-in-db output signal (Ivga_out). The variable gain amplifier (1) comprises a linear-in-db control current genera...  
WO/2018/002753A1
A triboelectric-based sensor may be used to receive touch-based input from a user and control electronic devices. The triboelectric-based sensors may also provide sufficient power to operate circuitry coupled to the sensor that performs ...  
WO/2018/004569A1
In accordance with embodiments of the present disclosure, a method for operating a playback path comprising a first dynamic range enhancement subsystem and a second dynamic range enhancement subsystem, wherein an audio signal generated b...  
WO/2017/223114A1
A combination of a block-oriented encoder and decoder with a modified dataset identifier that is associated with an encoded block size are used to perform block-based encoding and decoding operations. The encoding process may generate op...  
WO/2017/221508A1
A ringing suppression circuit (5, 21, 31, 41) is provided in a node (2) equipped with a communication circuit (6) that communicates with another node (2) by transmitting a differential signal via a pair of communication lines (3P, 3N), a...  
WO/2017/219251A1
A trapezoidal broadband piezoelectric filter, consisting of a series of first resonators connected in series, a series of second resonators connected in parallel, an impedance matching device located near an input end or an output end of...  
WO/2017/221292A1
A parallel drive circuit (50) has a first semiconductor switch element (1) and a second semiconductor switch element (2). A first drain terminal (1b) of the first semiconductor switch element (1) is connected in parallel to a second drai...  
WO/2017/220217A1
The invention relates to a drive method for a first power semiconductor chip (1, 12) comprising a first switchable power semiconductor (T1, T) and a first freewheeling diode (D1, D) and for a second power semiconductor chip (1, 13) compr...  
WO/2017/219124A1
A common capacitive touch sensor may have a two dimensional array of transparent conductive strips going from edge to edge on a substrate layer or sheet of a touch sensor. According to some aspects, there is provided a capacitive touch s...  
WO/2017/220906A1
The present invention relates to a method for optimizing the low-frequency sound rendition of an audio signal, implementing variations in a plurality of parameters (Ρ1, P2, P3, PN) of said audio signal according to the volume level (V1,...  
WO/2017/223095A1
Massively parallel, block-based encoding and decoding technology that includes an encoded block format uses a plurality of processing cores to perform block-based encoding and decoding operations. The encoded block format includes a head...  
WO/2017/221887A1
This invention is provided with: an AT-cut crystal piece including a first main surface (12a) and a second main surface (12b) facing each other and having long edges in the x-axis direction and short edges in the z-axis direction of a qu...  
WO/2017/221089A1
The invention relates to a method for automatic adjustment of a single-input-port and single-output-port tunable matching circuit, for instance a single-input-port and single-output- port tunable matching circuit coupled to an antenna of...  
WO/2017/223572A1
In various implementations, an enclosure may be utilized to secure component(s) to location(s), such as an overhead portion of a structure (e.g., a ceiling) for a variety of applications, such as creating a communications network. For ex...  
WO/2017/222831A1
Methods and apparatuses for user sound exposure limiting are disclosed. In one example, an accumulated sound dose exposure from a headset speaker is determined for a plurality of sequentially monitored time intervals during a current lis...  
WO/2017/222751A1
Various embodiments of methods and systems for closed loop multimode sleep clock frequency compensation in a portable computing device are disclosed. An exemplary embodiment leverages a modem to determine a frequency shift on a sleep clo...  
WO/2017/219700A1
A level switching circuit and an electronic device comprising the circuit. The level switching circuit comprises: a first inverter (INV0), a coupling capacitor (C0), a second inverter (INV1), a biasing resistor (R0), and a low-frequency ...  
WO/2017/220131A1
The present disclosure relates to a wireless communication network node (1) comprising an antenna arrangement (2), a transmitter arrangement (3) that is arranged to transmit output signals, and a receiver arrangement (4) that is arranged...  
WO/2017/220450A1
The invention relates to a device having at least one region (14) that can be illuminated and having an operating device, comprising a cover (12), a circuit board (30), at least one lighting means, and at least one reflector element (40)...  
WO/2017/222801A1
Some aspects of the disclosure relate to a pre-fetch mechanism for a cache line compression system that increases RAM capacity and optimizes overflow area reads. For example, a pre-fetch mechanism may allow the memory controller to pipel...  
WO/2017/221768A1
The present invention comprises: at least one voltage conversion unit 122 that converts, to a lower voltage, the voltage of supplied power supplied from an external apparatus; and at least one amplifier 12 that, operating on the supplied...  
WO/2017/222990A1
Proposed is a layer structure (1100, 1030) comprising a crystalline piezoelectric III-N layer (1110, 1032) epitaxially grown over a metal layer which is epitaxially grown over a rare earth oxide layer on a semiconductor (1102, 1002). The...  
WO/2017/222620A1
An adaptive clock distribution (ACD) system (100) with a voltage tracking clock generator (VTCG) (108) is disclosed. The ACD system includes a tunable-length delay (TLD) circuit (104), to generate a TLD clock by adding a preselected dela...  
WO/2017/222568A1
In accordance with embodiments of the present disclosure, a multi-mode switching power converter may include a power inductor, a first switch coupled between a first terminal of the power inductor and a first supply terminal having a fir...  
WO/2017/220138A1
A system and method for phase alignment of multiple PLLs are disclosed. The system comprises a plurality N of PLLs (PLL_1...PLL_N) and a plurality N of phase detectors (DET_1...DET_N). The plurality N of phase detectors and the plurality...  
WO/2017/221054A1
Embodiments of a transmitter having an architecture that reduces power consumption and complexity are disclosed. In some embodiments, a transmitter comprises a modulator comprising an actuator, modulation circuitry, and an adaptor. The a...  

Matches 101 - 150 out of 548,175