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Matches 301 - 350 out of 548,340

Document Document Title
WO/2017/208747A1
The present invention comprises: preparing an aggregate substrate (10); and forming through-holes (20) and an electrode layer (400) in the aggregate substrate, wherein the electrode layer includes via electrodes respectively provided in ...  
WO/2017/208307A1
The present invention is provided with: a first protection transistor (Q1), the emitter of which is connected to a first node (1); a first diode (D1) connected between the collector of the first protection transistor (Q1) and an output t...  
WO/2017/210495A1
A method is provided for fabricating piezoelectric plates. A sacrificial layer is formed overlying a growth substrate. A template layer, with openings exposing sacrificial layer surfaces, is formed over the sacrificial layer. An adhesion...  
WO/2017/209837A1
Certain aspects of the present disclosure relate to techniques and apparatus for improving decoding latency and performance of Polar codes. An exemplary method generally includes generating a codeword by encoding information bits using a...  
WO/2017/209844A1
A low clock power data-gated flip -flop is provided. The data-gated flip-flop includes an exclusive OR component including a first exclusive OR input, a second exclusive OR input, and a first exclusive OR output. The first exclusive OR i...  
WO/2017/206425A1
A flexible circuit board (50a), a biological information sensing module, and an electronic device (100). The electronic device (100) comprises: a protective cover plate (10) comprising a first surface (11) and a second surface (12) oppos...  
WO/2017/210035A1
Examples disclosed herein relate to controlling volume on an immersive display device. One example provides a near-eye display device comprising a sensor subsystem, a logic subsystem, and a storage subsystem storing instructions executab...  
WO/2017/206075A1
Disclosed are a clock generator circuit and a clock signal generation method. The method comprises: using a direct current bias circuit in a first clock source, superimposing a first direct current voltage on a first clock signal output ...  
WO/2017/209986A1
An example a phase-locked loop (PLL) circuit (100) includes a sampling phase detector (103) configured to receive a reference clock and a feedback clock and configured to supply a first control current and a pulse signal. The PLL further...  
WO/2017/210205A1
Certain aspects of the present disclosure relate to techniques and apparatus for increasing decoding performance and/or reducing decoding complexity. An exemplary method generally includes obtaining a payload to be transmitted, partition...  
WO/2017/206481A1
Disclosed are drive-by-wire headphones, comprising a USB plug, a headphone cable, a left-ear receiver, a right-ear receiver, and a volume regulator. The USB plug is provided with a power supply pin, a ground pin, and two signal pins. The...  
WO/2017/204007A1
The present invention provides a feature with which it is possible to effectively suppress an increase in computation scale when applying maximum likelihood detection (MLD) to a multi-level modulation scheme. A likelihood calculation uni...  
WO/2017/203173A1
The invention relates to a method for healing defects in a layer (10) of composition ABO3 where A consists of at least one element from: Li, Na, K, H, Ca, Mg, Ba, Sr, Pb, La, Bi, Y, Dy, Gd, Tb, Ce, Pr, Nd, Sm, Eu, Ho, Zr, Sc, Ag and Tl, ...  
WO/2017/204704A1
Described is a method performed by an encoder of a base station system (100) of a wireless communication network, for handling a bit stream for transmission over a transmission link (165) between a remote unit (160) and a base unit (170)...  
WO/2017/202304A1
A start-up and shut-down circuit, comprising: a PMOS tube, a switch, a triode and an RC parallel circuit, wherein a source electrode of the PMOS tube is connected to an external power supply input end, and a drain electrode thereof serve...  
WO/2017/203187A1
The invention relates to an integrated circuit (3) comprising a plurality of first chips (1, 1'), each of which includes a high-voltage depletion mode transistor, and comprising a second chip (2) that includes a low-voltage enhancement m...  
WO/2017/204002A1
The present invention pertains to a signal processing device and a signal processing method that enable robust reproduction of data recorded at high density. The frame sync (FS), which represents the header of a frame, is restored by, fr...  
WO/2017/203103A1
An apparatus comprising a processor and memory including computer program code, the memory and computer program code configured to, with the processor, enable the apparatus at least to: based on a predetermined dark current component for...  
WO/2017/204889A1
An eVC including coarse and fine tuning networks. The coarse tuning network includes a circuit: receiving a RF input signal from a RF generator; outputting a RF output signal to a reference terminal or load; and receiving a DC bias volta...  
WO/2017/203840A1
A ringing suppression circuit (5, 21, 31) is provided to a branch point (4) at which a transmission line (3) for transmitting a differential signal branches off, the ringing suppression circuit suppressing ringing generated due to transm...  
WO/2017/204921A3
A device includes an amplifier and calibration circuitry coupled to the amplifier. The calibration circuitry is configured to receive calibration values. The calibration circuitry is also configured to generate an output value in respons...  
WO/2017/203624A1
The purpose of the present invention is to achieve size reduction and simplification of the circuit configuration of an intelligent power module (IPM) through phase synchronization of the IPM. The IPM pertaining to the present invention ...  
WO/2017/203571A1
Provided are a wire (4) for which one end is connected to the output terminal of a transistor (3); a transmission line (5) for which one end is connected to the other end of the wire (4); a wire (8) for which one end is connected to the ...  
WO/2017/202626A1
A sensor is for measuring skin conductance. An amplifier is used to convert the skin conductance into an analog output voltage which is then converted into the digital domain, so that the increase in tonic skin conductance and the phasic...  
WO/2017/204705A1
A Transmitting Node (TN) 102 and a method therein for providing enhanced channel coding of a packet transmitted in a communications network 100. The TN applies, to payload data, an outer channel encoder resulting in a plurality of outer ...  
WO/2017/201826A1
A digital-to-analog converter, comprising N rows of transistors. The number of transistors in each row is halved compared with a previous row. Each transistor comprises a conducting end, an input end, and an output end. Input ends of the...  
WO/2017/204346A1
A filter (22A) is provided with a series arm circuit connected between an input/output terminal (22n) and an input/output terminal (22m), and a parallel arm circuit (120A) connected between a node (x) and the ground. The parallel arm cir...  
WO/2017/203039A1
There is provided a method of controlling a switching valve (30). The switching valve (30) includes a plurality of series-connected switching elements (32)and a plurality of auxiliary circuits (34). Each auxiliary circuit (34) is connect...  
WO/2017/203919A9
A duplexer (1A) is provided with: a 90° hybrid (30) that is connected to an antenna terminal (110); a 90° hybrid (40) that is connected to a terminating resistor (70); a transmission side filter (10A) that is connected to the 90° hybr...  
WO/2017/203741A1
The present invention enables a second- or higher-order TCF to be reduced in a resonator. A resonator is provided with: a vibration part having a silicon substrate, one or more electrodes each formed so as to have a surface facing a fron...  
WO/2017/204621A1
Balun circuit arrangement with a balanced port side having two balanced terminals and an unbalanced port side having an unbalanced terminal. A first series connection of a first inductive impedance element (L1) and a first capacitive imp...  
WO/2017/205618A1
A fully integrated GaN driver comprising a digital logic signal inverter, a level shifter circuit, a UVLO circuit, an output buffer stage, and (optionally) a FET to be driven, all integrated in a single package. The level shifter circuit...  
WO/2017/201819A1
A light controlled timer, comprising a timer socket (2) and a timer plug (1). The timer socket (2) is connected with an input/output device. The timer plug (1) comprises a setting disc (13), an upper housing (11) provided with a window, ...  
WO/2017/204347A1
A filter module (20) is provided with: a filter circuit (22) that comprises switches (221SW and 224SW) and switches passbands in response to said switches (221SW and 224SW) conducting or not conducting current; and an impedance matching ...  
WO/2017/204970A1
Over-voltage protection systems and methods are disclosed. In one aspect, a biasing circuit is added to a pre-existing clamp required by the Universal Serial Bus (USB) Type-C specification at a configuration control (CC) pin. The biasing...  
WO/2017/205433A1
Dynamic history multistream long range compression (DHC) techniques are described for efficiently compressing multiple, prioritized data streams received over a channel. A history buffer is associated with each received stream and a DHC ...  
WO/2017/203919A1
A duplexer (1A) is provided with: a 90° hybrid (30) that is connected to an antenna terminal (110); a 90° hybrid (40) that is connected to a terminating resistor (70); a transmission side filter (10A) that is connected to the 90° hybr...  
WO/2017/203892A1
A layered electronic component (100) comprises a layered body (1) and an external electrode. The layered body (1) has a rectangular parallelepiped shape, and is provided with a first pattern conductor (1P) and a first via conductor (1V)....  
WO/2017/205030A1
An input receiver is provided with a pass transistor that is controlled to pass an input signal to an inverter only while a first binary state for the input signal equals a low voltage. The input receiver also includes a source follower ...  
WO/2017/203757A1
Fluctuation in the temperature characteristics of the resonance frequency is suppressed in a step for adjusting resonance. The invention has: a base; a first electrode and a second electrode; and a piezoelectric film provided between the...  
WO/2017/204921A2
A device includes an amplifier and calibration circuitry coupled to the amplifier. The calibration circuitry is configured to receive calibration values. The calibration circuitry is also configured to generate an output value in respons...  
WO/2017/201763A1
A sampling apparatus, comprising a switched capacitor circuit. In the switched capacitor circuit, first ends of a first switch (S11) and a second switch (S11') are both connected to an input signal (Vin); a second end of the first switch...  
WO/2017/203186A1
The invention relates to an integrated circuit (3) comprising a housing (4) and a plurality of connection pins, a first chip (1) that includes a high-voltage depletion mode transistor, and a second chip (2) that includes a low-voltage en...  
WO/2017/204902A1
A phase discontinuity mitigation implementation within a phased lock loop (PLL) improves throughput of a radio access technology. The throughput is improved by maintaining a phase of the PLL while powering off some devices of the PLL, su...  
WO/2017/201832A1
Provided are a digital-to-analog conversion circuit and a data source integrated circuit. The digital-to-analog conversion circuit comprises first MOS transistors, the number of which is equal to the number of bits of an input digital qu...  
WO/2017/204390A1
A sample validity determination method and apparatus for a digital predistortion apparatus are disclosed. The main purpose of the present embodiment is to provide a sample validity determination method and apparatus for a digital predist...  
WO/2017/204348A1
A filter (22A) is provided with a series arm circuit (11) connected between an input/output terminal (22m) and an input/output terminal (22n), and a parallel arm circuit (12) connected between a node (x1), which is on a path connecting t...  
WO/2017/203976A1
The present disclosure pertains to a compression encoding device and method, a decoding device and method, and a program, which enable provision of lossless compression technique at a higher compression rate. According to the present inv...  
WO/2017/202416A1
The invention relates to a method for analog-to-digital conversion and for converting analog input signals into a digital data stream, wherein most significant bits Dn-1 are produced within a cycle time TAD/DA by means of at least one AD...  
WO/2017/205096A1
Adaptively controlling drive strength of multiplexed power from supply power rails (204(N)) in a power multiplexing system (200) to a powered circuit (208) is disclosed. A power multiplexing circuit (201) in the power multiplexing system...  

Matches 301 - 350 out of 548,340