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Matches 351 - 400 out of 555,660

Document Document Title
WO/2018/228514A1
Disclosed are an encoding method, a device, communication equipment, and a communication system. The method comprises: using a low-density parity-check (LDPC) matrix to encode an input bit sequence, where the LDPC matrix is produced on t...  
WO/2018/231023A1
This disclosure relates to a communication technique which fuses a 5G communication system with IoT technology to support higher data transmission rates after a 4G system, and system thereof. This disclosure can be applied to intelligent...  
WO/2018/227998A1
Disclosed in the present invention is a temperature compensation circuit for a radio frequency power amplifier; the temperature compensation circuit comprises: a temperature control circuit and a negative feedback circuit; the temperatur...  
WO/2018/228592A1
An interleaving processing method and device for polar codes. The method comprises: determining N bits to be encoded, where N is a positive integer (S210); acquiring a first sequence of serial numbers of N polarization channels, wherein ...  
WO/2018/230112A1
This ΔΣ modulator is provided with a first adder that adds a plurality of RF signals of different frequencies, a loop filter, a second adder, a quantizer, a difference unit, and a distortion compensator. The loop filter has pass bands ...  
WO/2018/230442A1
This bonded substrate comprises a quartz substrate, and a piezoelectric substrate which is bonded onto the quartz substrate and on which a surface acoustic wave propagates, the bonding comprising a covalent bonding at a bonding interface...  
WO/2018/229064A1
A polar encoder kernal (102) is described. The polar encoder kernal (102) is configured to receive one or more bits from a kernal information block (105) having a kernal block size of N; and output one or more bits from a kernal encoded ...  
WO/2018/229856A1
A drive circuit (100) is provided with a signal generation circuit (50), comparator (6a), comparator (6b), and short-circuit determining unit (8). The signal generation circuit (50) generates, as an output signal, a differential amplific...  
WO/2018/227744A1
A method to explicitly indicate the version information while still supporting soft combining is disclosed. A polar code encoder maps q bits to q positions of q sub-channels, q is a positive integer; wherein the q bits are used to indica...  
WO/2018/227604A1
A method to explicitly indicate the version information while still supporting soft combining is disclosed. A polar code encoder maps q bits to q positions of q sub-channels, q is a positive integer; wherein the q bits are used to indica...  
WO/2018/227347A1
Embodiments of the present invention relate to the technical field of communications. Disclosed are a method and device for reducing the power consumption of a PA, allowing the power consumption of the PA to be reduced to the greatest ex...  
WO/2018/228143A1
A control method for a sensor key, a mobile terminal, and a computer readable storage medium. The method comprises the following steps: when the sensor key receives a starting instruction, an infrared emitter emitting an infrared ray (21...  
WO/2018/230359A1
This power generation switch has: a holder part; a power generation part that has a fixed end fixed to the holder part and a free end vibrating freely, that generates electric power by the free end vibrating freely, and that has a magnet...  
WO/2018/229068A1
A polar decoder kernal (111) is described. The polar decoder kernal (111) is configured to: receive one or more soft bits from a soft kernal encoded block (113) having a block size of N and output one or more recovered kernal information...  
WO/2018/228380A1
Disclosed are a coding method and a communication device. The method of the embodiments of the present invention comprises: constructing a check equation according to a correlation between a first sub-channel and a second sub-channel whi...  
WO/2018/229073A1
A polar decoder kernal (111) is described. The polar decoder kernal (111) includes a processing unit (2201) having: at least one input configured to receive at least one input Logarithmic Likelihood Ratio, LLR, (2202, 2203); a logic circ...  
WO/2018/229071A1
A polar coder circuit (600, 1600) is described. The polar coder circuit (600, 1600) comprises one or more datapaths (601, 1601, 1602, 1603); and at least one logical three-dimensional, 3D, memory block (602, 603, 1605) coupled to the one...  
WO/2018/232002A1
Various embodiments include apparatus and methods that have a multiple phase generator. The multiple phase generator can include multiple delay devices coupled with a set of phase mixers having a specified mixing ratio to generate signal...  
WO/2018/230229A1
The present invention achieves an amplifier, represented by a TIA, in which band characteristics are optimized, the probability of oscillation is reduced, and that exhibits little variation in band characteristics. This amplifier, which ...  
WO/2018/227681A1
A coding method and apparatus, a communication device, and a communication system. The method comprises: coding an input bit sequence by using low-density parity-check (LDPC) matrices, the LDPC matrices being obtained based on a base gra...  
WO/2018/232351A1
An electrical filter is disclosed. The electrical filter can include a conductive concrete structure including at least one of a conductive carbon material, a magnetic material, or a conductive metallic material. The conductive concrete ...  
WO/2018/229977A1
The present invention is provided with a poly-phase filter (5), which generates a first differential signal on the basis of a first signal amplified by a first transistor (2-1), outputs the first differential signal from a first output t...  
WO/2018/230992A1
The present disclosure relates to a communication scheme for convergence of an IoT technology and a 5G communication system for supporting a higher data transmission rate beyond a 4G system, and a system therefor. The present disclosure ...  
WO/2018/229703A1
Systems, methods, and computer-readable media are disclosed for performing reduced latency error decoding using a reduced latency symbol error correction decoder that utilizes enumerated parallel multiplication in lieu of division and re...  
WO/2018/231556A1
An integrated circuit comprising an array of logic tiles, arranged in an array of rows and columns. The array of logic tiles includes a first logic tile to receive a first external clock signal wherein each logic tile of a first pluralit...  
WO/2018/230338A1
The present technique relates to a clock enabler circuit capable of preventing a whisker from occurring in an output clock. A gate signal generation unit generates an input clock-enabling gate signal on the basis of an input clock and an...  
WO/2018/228773A1
An optical receiver circuit (100) has a first photodiode (102) and a second diode (103) and an amplifier circuit (104-108) connected to the diodes. The photodiodes are arranged so that the second photodiode receives substantially the sam...  
WO/2018/231100A1
The invention relates to the field of coding/decoding information. The technical result consists in increasing the effectiveness of anti-noise coding/decoding of information by increasing the volume of information transmission/reception ...  
WO/2018/231148A1
According to embodiments of the present invention, a circuit is provided. The circuit includes forming a first electrical device having a first region of a first conductivity type, forming a second electrical device having a second regio...  
WO/2018/228771A1
An electro-acoustic RF filter allowing improved filter skirts is provided. The filter has a flank between a transmission band and a rejection band and a ladder type like topology. A first inductive element and a second inductive element ...  
WO/2018/228772A1
A TIA circuit (1) has an input terminal (11), and an odd number of at least three inverting amplifier stages (A1, A2, and A3) linked in series to the input terminal. A reference voltage source (16) is connected to the source of the trans...  
WO/2018/230196A1
A drive device 100 is equipped with: a gate drive unit 20 which has gate drive circuits 21, 22 which respectively drive the gates of switching elements 11, 12 that are connected in series with one another; a negative-side power supply VC...  
WO/2018/229610A1
A system includes a set of delay circuits logically coupled in a chain configuration, a plurality of flip-flop circuits logically coupled to the delay output of the each of the delay circuits respectively, forming tiers of flip-flop circ...  
WO/2018/227492A1
A button device (10) for use in an electronic equipment and an electronic equipment. The button device (10) comprises a parallel plate capacitor (11), wherein pole plates (112, 118) of the capacitor (11) may change shape when pressed in ...  
WO/2018/230235A1
Provided are a latch circuit and a flip-flop circuit that have superior single event upset (SEU) resistence. The latch circuit according to the present invention having single event upset (SEU) resistence is configured such that, with re...  
WO/2018/226221A1
A non-transitory computer-readable storage medium comprising instructions stored thereon. When executed by at least one processor, the instructions may be configured to cause a computing system to at least determine, for a first segment ...  
WO/2018/224213A1
The invention relates to a controlled load apparatus having a load (10), a control electronics system (12), which is connected to the load (10) by means of at least one conductor (14) in such a way that the load (10) can be switched and/...  
WO/2018/224144A1
A phase controllable Phase Locked Loop, PLL (100) for generating an output signal is disclosed. The PLL comprises a phase frequency detector (200) comprising two latches (210, 220). Each latch comprises a clock input (Clk), a reset input...  
WO/2018/224538A1
The invention relates to a parallel ADC circuit comprising a reference voltage ladder providing a plurality of reference voltages, comparators, each of the comparators comprising two inputs, one coupled to an input terminal receiving a s...  
WO/2018/225143A1
There are provided: an amplifier (3) for amplifying a signal including a first signal and a second signal having a frequency different from that of the first signal; an input-side bias circuit (6) of which one end is connected to a signa...  
WO/2018/225929A1
The present invention relates to a passive conjunction circuit (50) for an analog-to-digital converter, ADC, (20), wherein the passive conjunction circuit (50) comprises a first input node (11) configured for receiving an analog input si...  
WO/2018/224190A1
The invention relates to an assembly component (1) for a motor vehicle, wherein the assembly component (1) is assigned an electronics unit (5) with at least one capacitive sensor (7), and the electronics unit (5) is arranged spaced apart...  
WO/2018/224982A1
According to some embodiments, a method in a wireless device comprises obtaining a set of information bits for wireless transmission and dividing the set of information bits into one or more subsets of information bits. For each subset, ...  
WO/2018/226419A1
Some embodiments of the invention are directed to enabling a user to modify the manner in which one or more settings specified by a predefined template for a particular sound source are applied, so as to provide the user with greater con...  
WO/2018/227124A1
A load control device for controlling power delivered from an alternating-current power source to an electrical load may comprise a controllably conductive device, a control circuit, and an overcurrent protection circuit that is configur...  
WO/2018/226557A1
A deinterleaver device, a method for deinterleaving, an interleaver device, and a method for interleaving are disclosed. The method for deinterleaving includes : providing a memory and a stream count for a frame; virtually dividing the m...  
WO/2018/224540A1
A device wafer comprises a silicon substrate, a piezoelectric layer arranged on and bonded to the silicon substrate and a structured metallization on top of the piezoelectric layer. The metallization forms functional device structures pr...  
WO/2018/226019A1
A method for encoding a quasi-cyclic low-density parity-check (LDPC) code according to an embodiment of the present invention comprises: a step of generating a multi-edge LDPC code matrix which comprises a high rate code matrix and a sin...  
WO/2018/227133A1
Certain aspects of the present disclosure provide quasi-cyclic low-density parity-check (QC-LDPC) codes having pairwise orthogonality of adjacent rows of the corresponding base matrices, and a new decoder (e.g. layered decoder) that expl...  
WO/2018/225083A1
The present invention relates to SiC MOSFET which has fast switching times of nearly 20ns to 50ns. To control the voltage and current overshoot of the SiC MOSFET during the switching transient an active gate driver is required. The inven...  

Matches 351 - 400 out of 555,660