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Matches 751 - 800 out of 13,092

Document Document Title
WO2001056154A3
A digital filter is disclosed, which is characterised, in that at least one of the multipliers in sequential multiplication procedures and/or at least one of the adders in sequential adding procedures, may be fed data representing variou...  
WO/2001/097376A1
The invention relates to a digital comb filter, which comprises n filter stages, whereby each filter stage has a retaining member located at the input of the filter stage. Said retaining member doubles the sampling rate by outputting eac...  
WO/2001/097475A1
An adaptive channel equalizer with adaptive coefficients for compensating for long delays multipaths and distortions. A training sequence is periodically sent over the channel and the adaptive coefficients of the equalizer are periodical...  
WO2001045253A3
The aim of the invention is the offset compensation of a digital signal (r), especially a communications signal that is transmitted in a cordless digital communications system. According to the invention, a recursive digital filter is us...  
WO2001052546A3
A filter structure is provided that facilitates the use of the filter as either a continuous delay Farrow filter or a selectable delay polyphase filter. The less complex polyphase filter is used when the desired scale substantially corre...  
WO/2001/089086A1
Modeling a target spectrum (S) is provided by determining (21) filter parameters (p¿i?,q¿i?) of a filter which has a frequency response approximating the target spectrum (S), wherein the target spectrum is split in at least a first par...  
WO/2001/089087A1
An equalizer substantially eliminates a ghost of a received main signal by (i) applying coefficients b (where b may be equal to one) to the received main signal and the ghost in order to modulatethe received main signal and the ghost so ...  
WO/2001/089085A1
A small-sized and power-saving matched filter circuit is provided. A succeeding stage of a matched filter includes a group of n hold circuits (H21, H22,..., H2n) to which the output signals (Dout1) from a preceding stage are coupled in p...  
WO/2001/086808A1
A digital filter is disclosed, the filter comprising means for determining of a partial filter input initial condition, using a partitioned filter input signal (5010), and partitioned filter input coefficients (5055), means for determini...  
WO2001025731A3
The present invention relates to a method for weighing items and in particular to a method of filtering signals representing the weight of an item. The invention is applicable in all measuring instruments which indicate an average value ...  
WO2001043285A3
The present invention is directed to a reconfigurable finite impulse response (FIR) filter that processes data tap values with canonical sign digit (CSD) coefficients. The FIR filter according to the present invention includes a shift gr...  
WO/2001/084707A2
A apparatus for computing coefficient values for configuring a digital filter for compensating for non-linearity of an RF/IF device. The apparatus includes a reference signal generator, connected to an input of the RF/IF device, for gene...  
WO/2001/084734A2
A matched filter requiring no high-speed processor and which consumes less power is disclosed. Partial filters 301 - 30N obtained by dividing number of matched filter taps by N are provided with a controller 341 for controlling which par...  
WO/2001/076115A1
A method for determining correlation using a matched filter in which despreading operation is performing by fixing received data and scanning a despread code. The despread results are integrated for each of the symbol parts before and af...  
WO/2001/073947A1
An arbitrary sample rate conversion apparatus is described. This apparatus includes a buffer (10) for forming blocks of input samples having a first sample rate. For each block of input samples a subfilter is selected from a polyphase fi...  
WO/2001/071931A2
A digital tuner (70) for maximizing tuning range for a particular intermediate frequency includes an analog-to-digital converter (78) operating at an input clock frequency to sample an analog input signal (76) and output a multi-bit digi...  
WO/2001/071874A2
A two-stage filter (20) for a circuit protection device. The filter includes a first filtering device (22) connected to receive an input signal v, the first filtering device (22) generating an intermediate signal v1, (1), where k is a sa...  
WO/2001/065485A1
In response to an incoming signal, a coefficient is determined by delay means (10, 11), coefficient multiplication means (20, 21, 22), summing means (30, 31, 32), and offset means (40). Coefficient multiplication means (23) multiplies th...  
WO/2001/065692A1
An apparatus for frequency content separating an input signal, said apparatus comprising a plurality of frequency splitting stages, each stage including one or more up-converter and down-converter pairs, an up-converter and down-converte...  
WO/2001/065713A1
A signal filter comprises a plurality of adding elements (21), each of which has first and second inputs and an output and is operable to provide an output signal representative of the sum of a pair of input signals. The filter also incl...  
WO/2001/063464A1
A wave digital filter which includes a plurality of memoryless adapters (42) each having two or more ports, each port including an input and an output, and at least one controlled gate (44) which delays the propagation of a value into at...  
WO/2001/063867A1
A receiver comprising A/D converters (1-1 to 1-4) for converting received analog signals (I1, Q1, I2, Q2) into digital signals, a quantization error reducing signal generator (2) for generating quantization error reducing signals for ran...  
WO/2001/057877A1
A sampling system includes an input terminal for receiving a data signal having a signal component and possibly a noise component. A sampler samples the data signal at a sample rate set in responsive to a control signal. A noise detector...  
WO/2001/058017A2
An area-efficient finite impulse response filter having permuted bit-order functional elements that provide substantially straight and direct interconnects with minimized length between adjacent elements. A functional element is coupled ...  
WO/2001/056154A2
A digital filter is disclosed, which is characterised, in that at least one of the multipliers in sequential multiplication procedures and/or at least one of the adders in sequential adding procedures, may be fed data representing variou...  
WO/2001/056167A2
A simplified algorithm for digital signal interpolation and a novel architecture to implement the algorithm in an integrated circuit ('IC') with significant space constraints are presented. According to the embodiments of the present inv...  
WO/2001/056157A1
A band pass filter (80) includes a pair of filters (82, 83) having different center frequencies and a difference amplifier (84) coupled to the outputs of the filters. The filters preferably have response curves that intersect at -3 dB. T...  
WO/2001/056156A1
An electrical signal is applied to a band pass filter (42), a first notch filter (43), and a second notch filter (44) in any order. The center frequencies of the notch filters straddle the pass band of the band pass filter. The notch fil...  
WO/2001/054312A1
A space profile determining section (102) determines the distribution of strength of the received signal with respect to the direction of arrival of a signal, namely, determines the space profile or space information by using the receive...  
WO/2001/052546A2
A filter structure is provided that facilitates the use of the filter as either a continuous delay Farrow filter or a selectable delay polyphase filter. The less complex polyphase filter is used when the desired scale substantially corre...  
WO2000065713A3
Sample rate converters are known, and are used to convert a signal with a first sample rate (sampling frequency) into a signal with a second sample rate (sampling frequency). To obtain a flexible sample rate converter with sampling frequ...  
WO/2001/048924A1
A band pass filter (50) includes a pair of notch filters (51, 52) having different notch frequencies and a difference amplifier (54) coupled to the outputs of the notch filters. The notch filters preferably have response curves that inte...  
WO/2001/047143A1
A lattice filter (201) determines a backward prediction error and a backward reflectance by using an input signal sequence. A tap coefficient calculating section (202) calculates a tap coefficient by using a reference signal and a backwa...  
WO/2001/046953A1
An arrangement is disclosed for receiving a digital signal from a transmission medium. The arrangement comprises a variable equalizer (6) for equalizing a received signal so as to obtain an equalized signal, and a bit-detector (12) for d...  
WO/2001/045268A1
An oversampling circuit and a digital/analog converter which have small circuit scales and the component costs of which are reduced. The oversampling circuit comprises a multiplying section (1), four data holding sections (2-1 to 2-4), f...  
WO/2001/045269A1
An oversampling circuit and a digital/analog converter which have small circuit scales and the component costs of which are reduced. Data inputted at predetermined intervals is multiplied by four multiplicators by means of a multiplier (...  
WO/2001/045253A2
The aim of the invention is the offset compensation of a digital signal (r), especially a communications signal that is transmitted in a cordless digital communications system. According to the invention, a recursive digital filter is us...  
WO/2001/045267A1
An oversampling circuit and a digital/analog converter which have small circuit scales and the component costs of which are reduced. The oversampling circuit comprises four D flip-flops (10-1 to 10-4), four multipliers (12-1 to 12-4), th...  
WO/2001/043285A2
The present invention is directed to a reconfigurable finite impulse response (FIR) filter that processes data tap values with canonical sign digit (CSD) coefficients. The FIR filter according to the present invention includes a shift gr...  
WO/2001/042798A1
A filterbank comprises a plurality of multipliers (M¿o?...M¿M-1?) connected to receive respective samples (x(n)...x(n-M+1) of an input signal and operable to multiply the samples by respective coefficients (c¿0?(k)...c¿M-1?(k)) to pr...  
WO/2001/041320A1
An oversampled filter bank structure that can be implemented using popular and efficient fast filter banks to allow subband processing of an input signal with substantially reduced aliasing between subbands. Even subbands (SB0, SB2, SB4,...  
WO/2001/039032A1
A method and system is disclosed for design an implementation of fixed-point filters from floating-point filters. A design sequence (120) for designing a fixed-point filter for a system is selected. A low-order floating-point filter (130...  
WO/2001/038943A1
A feedback control system for 1-bit digital signal processing comprises different operation means (23) for calculating the difference between the input from an external device (22) and the measured variable measured by sensing means (25)...  
WO2000074438A3
A digital hearing aid uses a digital filter using coefficient multipliers and with digital signal processing algorithms, which can be implemented with a minimum amount of dedicated circuitry, which may be contained in an integrated circu...  
WO/2001/035525A1
A parallel digital matched filter is constructed which performs numerous simultaneous correlations of a received spread spectrum signal against various replica offsets of its spreading sequence. This allows for the rapid acquisition (12)...  
WO/2001/033712A1
There is disclosed a digital filter cell capable of processing in a first mode a first signal having real data components only and processing in a second mode a second signal having real data components and imaginary data components. The...  
WO/2001/033730A1
An echo compensation device for a duplex transmission system comprises an echo compensator (10), for creating a digital echo compensation signal (yec), based upon a digital transmitted signal (y), which is combined with a digital receive...  
WO/2001/031783A1
A Finite Impulse Response (FIR) filter circuit (60) includes delay elements (63, 64, 66), multipliers (71, 72, 73, 74), a summing device (78), and a digital integrator (69) at the output of the FIR filter circuit (60). A method for proce...  
WO/2001/028091A1
Receiver systems often use filter combinations of resampling filters and matched filters to decimate the input signal and to adapt it to the pulse form of the sender signal. Due to the independent functions these two filters fulfil, they...  
WO/2001/028120A1
A mobile station is provided for receiving a spread spectrum, code division transmission from at least one transmitter, such as a base station. The mobile station contains a receiver for outputting data samples, and further contains a mu...  

Matches 751 - 800 out of 13,092