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Matches 451 - 500 out of 4,883

Document Document Title
JPWO2004105247A
A feeding back pass (307) is formed between the output (310c) of a fixed counting-down circuit (305), and the control terminal (310b) of reversal / reversed vessel (304). A connector (306) is provided in a feeding back pass (307), a feed...  
JP3592376B2  
JP2004318727A
To provide an analog monitor circuit which is suitable for an ASIC, requires a smaller number of external components and is low in cost.The analog monitor circuit is provided with a register 31, an accumulator 33 provided in the register...  
JP2004320515A
To provide two poles analog monitor voltage generating circuit in which positive/negative voltages can be outputted from an output of ASIC with a single power source.In a digital/analog converter, a D-flip flop 2 holds data when BRM1 out...  
JP3585114B2
To provide a frequency divider that can selectively output a fundamental wave without increasing number of signal lines for frequency divider control. The frequency divider is provided with a frequency divider integrated circuit 1 that f...  
JP2004304381A
To provide a counting device and a counting method capable of drastically reducing power to be consumed in an internal circuit and stabilizing a counting operation by power from an input pulse.Read operation processing and write operatio...  
JP3578690B2  
JP3575980B2  
JP3573824B2  
JP2004260566A
To provide a timing adjuster in which a required time can be set accurately without using a capacitor for adjusting the time and drift of a set adjusting time is reduced.An input signal Vina is converted into a digital signal by an AD co...  
JP3566342B2
PURPOSE: To provide a parallelly operated high-speed counter for making high- speed counting possible by parallelly operating the two counters of two system for the high-speed counting impossible by one counter. CONSTITUTION: This counte...  
JP2004254338A
To provide a counting device which satisfies fail safe counting performance not performing rash counting output in a failure time, and is excellent in reliability.The device comprises a counter 100 which generates an output, when countin...  
JP3563198B2
To control counting of an up-down counter circuit with two input terminals. When input signals given to two input terminals 1, 2 both set to a low level, a value of the counter is reset to '0'. When an input signal of either of the two i...  
JP3559396B2  
JP2004242283A
To provide a frequency divider circuit, a PLL circuit and a semiconductor integrated circuit in which high-speed operation is realized, and a desired frequency dividing ratio is obtained without generating switching noise.The circuit of ...  
JP2004236193A
To generate a precise fraction frequency division signal irrespective of precision of a decimal part of a frequency-divided number.A cumulative adder 7 performs cumulative addition of a decimal value f set in an f setting part 8 in respo...  
JP2004229326A
To provide a synthesizer and a signal analyzer which perform edge arrangement of exact and high resolution without necessity of system clock of frequency very higher than frequency of a synthetic clock signal.It comprises a system clock ...  
JP2004228812A
To provide a frequency divider which can operate with low consumption power at high speed.Two-frequency dividers 10 and 30-50 are each constituted of a D flip-flop composed of an NMOS source coupled logic and having an NMOS transistor gr...  
JP3552426B2  
JP3548925B2  
JP3550868B2
To reduce the minimum variable width while keeping nearly constant a maximum variable range of the variable delay circuit. The variable delay circuit is made up of a counter CNT, current sources SW1, SW2-SWn, controlled by the counter CN...  
JP3550853B2
To reduce circuit scale and to reduce costs through elimination of a subtracter by providing a D flip-flop in place of an overflow detector. When the output of a D flip-flop 5 for delaying the carry output of a j-bit adder 4 equipped wit...  
JP3544791B2
To decrease malfunctions due to timing deviation by providing a 2-input OR circuit to a post-stage of a flip-flop and obtaining an OR between an output of the flip-flop and a clock signal, while using a buffer so as to set the same delay...  
JP2004200872A
To provide a counter circuit operating at a desired phase independently of an initial state such as in power rising.A reset pulse generating circuit (3) performs decoding when a counter output (SB1) is a prescribed value Y-a and outputs ...  
JP3540589B2
To provide a clock multiplying circuit which can make a frequency comparison fast, has a short lock-in time, is stable and has less jitter for generating a clock signal of high frequency with a large multiplication number from an input c...  
JP2004519958A
The fraction frequency divider in which a program is possible makes finer dividing ability more possible than the conventional integer frequency divider to output frequency. The fraction frequency divider in which the program of the pres...  
JP2004165757A
To provide a device capable of suppressing a clock frequency to low because a circuit operates at the frequency of an input clock, and reducing the power consumption of the circuit and heat generation associated therewith.The circuit for...  
JP2004153547A
To change a frequency dividing ratio of a clock signal without enlarging a circuit scale.Whenever a reference clock signal is inputted from a reference clock signal source 20, output signals of stages Q2 and Q3 of a counter changing outp...  
JP2004146925A
To prevent malfunction caused in an unstable state until a value of write data from an external unit is defined.The pulse generator is provided with: a counter 104 for counting clocks; a comparator 105 for detecting coincidental comparis...  
JP2004129254A
To provide a frequency multiplier for an external clock signal, a multiplication method, an output buffer for data, and a semiconductor device provided with the multiplier and the output buffer.The frequency multiplier is provided with: ...  
JP3517331B2
To measure a counting rate by removing noise to prevent erroneous counting due to noise. A counting rate is measured by normal measuring means with a feedback type counting rate meter comprising an up/down counter 1, a pulse generator 2 ...  
JP3510737B2
To allow the circuit to easily detect a phase difference of two kinds of signals (horizontal synchronization signal HS and reference clock signal). A decoder 12 decodes a count of a counter 11, counting the number of reference clock sign...  
JP3510903B2
PURPOSE: To provide a high-speed adder (provided with a subtractor) and a counter constituted of a programmable lookup table in a programmable logic device. CONSTITUTION: A conventional lookup table 10 is divided into smaller lookup tabl...  
JP2004507962A
A digital variable clocking circuit is offered. A variable clocking circuit generates the output clock signal which has an output clock frequency equal to the frequency of the input clock signal by which was set up to receive an input cl...  
JP2004062580A
To provide a counter system and a method for counting, which enables the operator to measure the number of rotation of various repeated motions per unit time using a single measuring device by making the measuring device to specified sen...  
JP2004056717A
To provide a semiconductor device for clock generator, a system board, and a multi-phase clock generating circuit in which stable operations of a circuit is made possible and an output clock signal of a uniform duty ratio is obtained by ...  
JP2004054932A
To provide hardware base utilization measuring apparatus used in a computer system having one or a plurality of central processing units.The hardware based utilization measuring apparatus and a corresponding method is used in the compute...  
JP2004056464A
To provide a frequency correction circuit for precisely correcting a clock signal of an oscillation frequency with a simple structure without adjusting the oscillation frequency in an oscillation circuit.Into the TBC(time-base counter)10...  
JP2004048729A
To provide a clock frequency divider and a clock frequency dividing method in a delay locked loop in which a frequency of an inputted external clock is automatically divided into a low frequency band or a high frequency band and an optim...  
JP2004038457A
To provide a semiconductor circuit device for making it unnecessary to synchronously arbitrate an interface between a block synchronizing with a source clock and an integrated circuit part operating with a frequency different from the so...  
JP2004038971A
To prolong the life by performing increment by a flash memory and reducing erasure frequency.A counter is implemented by using a method for minimizing bit transition from 1 to 50 and implemented by m+n bit. Bits of the counter are groupe...  
JP3491372B2
PURPOSE: To establish a failure sensing method for input capture circuit, which can make failure sensing at a low cost without enlarging the magnitude of the circuit configuration. CONSTITUTION: An input capture circuit is equipped with ...  
JP2004015153A
To provide a counter capable of acquiring an accurate value of the number of pulse trains externally received in a short time and to provide a counter system.The counter 1 for receiving pulse trains from the outside of the counter to cou...  
JP2004005009A
To change the average frequency of a clock signal independently from a reference clock signal.A reference clock signal generating circuit 1 generates a reference clock signa. A dividing circuit 2 divides the reference clock signal by a n...  
JP3479145B2
PURPOSE: To obtain an apparatus for measuring the distance accurately using an ultrasonic receiving signal. CONSTITUTION: An ultrasonic oscillator 1 is connected with a transmitting circuit 2 and a receiving circuit 3 connected with an A...  
JP3471268B2
To provide a logic circuit capable of securing a wide timing margin in control signals even under a high-speed operation and improving operation accuracy. The control signals tA, tB, tC and tD successively rise at each half clock of an e...  
JP3468964B2
To prevent malfunction of a prescaler for the operation delay of a swallow counter and to enable a high speed operation. A swallow counter is provided with a malfunction prevention circuit part 42. When all the set value data A1 to A7 su...  
JP3470189B2
PURPOSE: To arbitrarily set a display range of a count value and a display digit of a decimal point by converting data of each digit to display data, and also, setting decimal point data to the display data at the time when its digit is ...  
JP2003533084A
(57) When the frequency of a summary input signal changes a lot than the dividing coefficient of the divider cell of a frequency divider, the power consumption of a frequency divider can decrease effectively. A low frequency input signal...  
JP2003309466A
To provide a cascadable divide-by-two binary counter circuit for use as a synchronous divider circuit in a phase lock loop.This binary counter circuit 120 is composed of a D-FF (D flip- flop) 122 and cascaded. An AND gate 124 is responsi...  

Matches 451 - 500 out of 4,883