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JP3236235B2 |
To test an optional toggle flip-flop by frequency-dividing and outputting inputted clock signals or outputting them without frequency-dividing them based on control signals inputted from the outside. A first circuit 10 generates and outp...
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JP2001339291A |
To improve the reliability of data with simple arrangement as to a data count processing apparatus.A correcting process part 24 corrects a count value according to the comparison result of a comparing circuit part 23 which compares a cou...
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JP3233773B2 |
PURPOSE: To attain stable measurement even when an input clock signal having a redundant form is selected in the case of self-monitor by initializing again a synchronization detection circuit when the clock signal is selected and resetti...
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JP2001324543A |
To provide a failure detecting circuit and a failure detecting method capable of detecting a failure during a normal operation, unlike in the past, in a counter circuit.An adder 2 adds a constant 1 to its output each time a counter 1 cou...
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JP2001292058A |
To provide a clock frequency divider that generates a frequency division clock at a duty ratio with high accuracy even when a frequency division value of any integer is set. An even number/odd number discrimination section 201 discrimina...
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JP2001267911A |
To provide a frequency divider circuit that can be operated at a high frequency band.The frequency divider circuit 100 is provided with an output emitter follower circuit 20 at its output stage. An oscillated signal extracted from nodes ...
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JP2001228274A |
To arbitrarily configure electronic counters of various types.A one-chip microcomputer 12 is provided which incorporates a ROM 13 and a RAM 14. A data corresponding to a variable of a program which is inputted through a communication par...
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JP2001202231A |
To simplify the constitution by using a counter as least as possible. This parallel data counting device for counting the total number of data of 1 included in a prescribed clock period in parallel data c constituted of plural bits input...
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JP2001186012A |
To solve a problem of a conventional frequency divider circuit, that it requires large current consumption because many gate circuits are required to set a plurality of frequency division ratios resulting in increased circuit configurati...
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JP2001168878A |
To provide a traffic shaping device by which a flexible and fine-tuned shaping operation is executed.This traffic shaping device 100 is provided with a detecting part 110 for detecting the VPI of an ATM cell, a storage memory 120 for sto...
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JP3175574B2 |
To provide a time measuring apparatus which can measure a time interval between each of a plurality of signals to be measured and a measurement reference signal and hold each measuring result even when the plurality of signals are genera...
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JP2001156623A |
To provide a counter circuit not needing a large scale gate circuit, suitable for semiconductor circuit integration or conducting a high-speed operation with respect to an n-bit counter and an image processing unit as well as optical det...
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JP2001148197A |
To provide an assembly in which sure number of storage operation for an EEPROM can be increased. An EEPROM 10 has memory cells of (n+1) pieces. The device is provided with a control circuit 36, the contents of (n-1) stages of a binary co...
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JP3168514B2 |
To accurately count clock signals at a high speed. A counter circuit 11 is constituted of a 7-stage shift register circuit, consisting of 7 flip-flop circuits 121-127 that receive clock signals CL of count objects in parallel and an EXOR...
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JP2001136064A |
To provide a frequency signal generator employing a PLL circuit that can optionally set a frequency of an output frequency signal. An arithmetic circuit 12 that gives a frequency division ratio G to a frequency divider 6 of a PLL circuit...
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JP3166458B2 |
PURPOSE: To provide a timer circuit capable of conducting counting in a plurality of ways. CONSTITUTION: This timer circuit is provided with a processing circuit 1 setting the clock, edge detection enabling signal, load enabling signal, ...
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JP2001127618A |
To realize a clock signal generating circuit that can generate a clock signal with an optional frequency division ration. The clock signal generating circuit that applies frequency- division to a system clock, is provided with an adder t...
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JP2001127620A |
To provide a timer with self-diagnostic function. The timer with self-diagnostic function is provided with a plurality of timer circuits each of which is provided with a counter 111 that receives a count signal and conducts counting, 1st...
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JP2001127619A |
To solve a problem of a conventional counter circuit that the circuit scale is increased by the increase in circuits because a carry circuit for forcibly incrementing the count by one at reset and an OR circuit for adding a pulse outputt...
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JP3160225B2 |
To prevent a decrease in accuracy due to shift of a rate that is caused by the shift of oscillation capacity of oscillation frequency in correspondence with a change in stray capacitance excluding oscillating means when a clock block is ...
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JP2001085991A |
To obtain a clock frequency divider that properly controls a phase relation between data that are a processing object and an output clock so as to attain sure data transmission in the case of frequency-dividing an input clock and outputt...
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JP3149995B2 |
PURPOSE: To provide a pulse monitoring circuit which can monitor the operation of a monitored circuit which outputs the monitored pulse signals of different pulse interval cycle times in the same constitution and in a smaller packing spa...
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JP3125562B2 |
PURPOSE: To correct the error to be generated in the clock cycle for data processing by providing plural time signals TS by an image sensor 10. CONSTITUTION: A reference clock Sr which shows the reference time of a time signal TS is gene...
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JP3123931B2 |
To provide a time measuring system enabling measuring shorter time than the system clock with a smaller circuit size. This time measuring system has a delay element for providing necessary resolution in each termination signal line of a ...
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JP2000353157A |
To suppress the variation frequency of a bus value by allowing a function block which has a local counter to refer to the contents of the high- order N bits of a master counter through a master counter value reference bus.To refer to cou...
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JP3116644B2 |
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JP2606458Y2 |
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JP2000307418A |
To sufficiently derive the performance of an IC circuit and to decide the final value of a counter fast by eliminating the influence of a propagation delay time transmitted from a counter-side IC to a decision-side IC. The multi-chip typ...
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JP2000293258A |
To provide an oscillation stable circuit with higher efficiency. The positive amplitude of the output signal 102 of a transmission circuit 1 is detected by a buffer 2 and negative amplitude is detected by an inverter 3. The number of out...
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JP3098769B2 |
A system, for counting the occurrence of a plurality of system events and for prioritizing the order in which count values are to be incremented, receives a plurality of data signals (15) where each signal is associated with a system eve...
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JP2000286696A |
To obtain a frequency dividing circuit which is reduced in number of components, improved in layout efficiency, and can generate frequency dividing signals of about 50% in duty ratio. A frequency dividing circuit gives the logically-oper...
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JP2000286695A |
To provide a divider circuit which is suitable to divide a reference clock into the one-over-integer value that is not equal to the n-th power of 2 by feeding the output of a logical gate that provides AND between this output and a reset...
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JP2000278117A |
To reduce the power consumption of a count circuit without impairing its substantial function. This count circuit 111 is provided with a circuit 20 that detects whether or not initial data R3, R4 of prescribed high-order bits among initi...
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JP2000269742A |
To obtain a stable oscillation waveform, free of distortion in an oscillation circuit, using a quartz oscillator. The resistance values of resistive elements 25 and 26 are set to be identical, and an inverter 20 for oscillation and ampli...
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JP3088302B2 |
An asynchronous reading circuit improves reliability of data read from a binary counter. Count data generated by a binary counter 101 according to a counting clock is converted into a gray code by a gray encoder. The count data represent...
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JP3083871B2 |
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JP2000236267A |
To easily improve the generation accuracy of a remote-control carrier signal without using a reference clock by a high-speed oscillator or sharply increasing the circuit scale. This circuit is equipped with a carrier counter 12, an inver...
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JP3076328B1 |
To prevent a scale of a decode circuit from being increased even when a parallel expansion number is increased by devising a header assignment method in the case of transition from a hunting state to a preliminary synchronization state s...
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JP2000224026A |
To provide a frequency-diving circuit by with which a frequency- divided signal is synchronized with a clock signal without delays. This frequency-dividing circuit is provided with D-type flip flops DFF1-DFF3 and DFF1a-DFF3a and a delay ...
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JP2000196441A |
To prevent occurrence of a harmonic noise from a frequency divider circuit not in operation. In the case of obtaining any frequency among 1, 5, 9, 10 kHz as a reference signal, any of frequency divider circuits 10-20 is operated and a 1s...
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JP2000174614A |
To minimize the propagation delay time by giving a clock signal and all output signals of D flip-flop circuits of a preceding stage to an input side of each AND circuit provided respectively for a clock input terminal of each D flip-flop...
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JP2000151390A |
To output a clock signal which has a prescribed duty and is synchronized with an input signal by forming the clock signal having the desired duty, based on the output signal of a latching means latching an input signal with a reference c...
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JP2000148255A |
To obtain the frequency dividing circuit which can obtain a dynamic range of sufficient output frequencies with a small number of bits and the uniformity when the frequency division ratio is represented in a logarithmic graph and the uni...
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JP3043720B2 |
To obtain a method for facilitating tests by a frequency divider circuit that verifies a timing, even at test operation by adding a test circuit to the frequency divider circuit so as to reduce a test pattern and to obtain the frequency ...
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JP3038624B2 |
PURPOSE: To provide a counter device for the number of printed sheets, inexpensive and highly reliable, installed in a printer. CONSTITUTION: Data requiring the backup such as the number of printed sheets are stored in a plurality of sit...
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JP3036940B2 |
PURPOSE: To avoid an inverted phase output caused when the relation of phases of an input clock and a reference pulse is inverted in a clock frequency divider circuit. CONSTITUTION: This circuit is provided with a 1st flip-flop 1 applyin...
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JP2000115272A |
To count the number of symbols based on a byte clock by making a counted value to coincide with the number of symbols by increasing or decreasing the counted value of a main counter by every specified data byte.A start signal is received...
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JP2000504907A |
(57) [Summary] Quality requirements for the counter may set a limit on the maximum frequency that can be applied to the counter. This also limits the resolution. According to the present invention, a generator for generating M second clo...
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JP3026387B2 |
PURPOSE: To provide a clock supplying circuit which can supply clock pulses having no deviation due to a delay to logic circuits and does not limit a user's designing area and an integrated circuit having this circuit. CONSTITUTION: A cl...
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JP2000068819A |
To synchronize the rising edges of an input clock and counter output without providing an initial value reset mechanism by selecting one of the outputs of first and second latch circuits and outputting the output data. When an input cloc...
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