| Document |
Document Title |
|
JPH1168552A |
To automatically make a flip-flop circuit in non-frequency division mode capable of being pulled in frequency division mode. This circuit 100 is equipped with (n) number of flip-flop circuits F1 to Fn, which are cascade-connected, so tha...
|
|
JPH1168553A |
To provide a high speed as well as also surely perform state transition of a sequencer main body by providing a sampling circuit or the like, which samples a counter output in a timing that is asynchronous with a counter output timing an...
|
|
JPH1141299A |
To attain the suppression of power consumption and the reduction of EMI noises by performing data transfer while making the frequency of a clock signal into 1/2. The frequency of a data timing signal TM is divided into 1/2 by a flip-flop...
|
|
JPH1141633A |
To provide a dial pulse detection method and dial pulse detector by which an accurate dial pulse digit is recognized even when a dial pulse has chattering. A rising of a dial pulse is detected and an MPU discriminates a level of the dial...
|
|
JP2590367Y2 |
|
|
JP2853894B2 |
A frequency divider includes three or more master-slave type flip-flop's (10,20,30) which are connected to each other to construct a 1/N frequency divider, in which two or more outputs whose periods are the same but phases are different ...
|
|
JPH1131965A |
To obtain a stable output which can freely be varied in duty ratio. Data corresponding to a high-level and a low-level period of a clock signal are held in registers 10-1 and 10-2. When those data match the counted value of a counter 30,...
|
|
JP2850002B2 |
An electronic counter such as for use in the odometer of a motor vehicle is provided comprising an array (10) of m rows and n columns of single flip-flop data latches and a central shifting unit (14). The central shifting unit (14) compr...
|
|
JPH118549A |
To provide a counter circuit with which a correct counter value can be read out, without stopping a counter and high-speed processing is enabled. Each time a counter clock CLK is inputted, the counter value of counter is updated. Each fl...
|
|
JP2843526B2 |
PURPOSE: To improve the propagation speed of a carry signal by a synchronizing counter constituted of the multi-stage organization of unit counters. CONSTITUTION: Each unit counter 80 is provided with a multiplexer 60 for selectively tra...
|
|
JPH114160A |
To frequency-divide an input clock by n/m ((n) and (m) are set to be arbitrary natural numbers and it is set to be n
|
|
JPH114161A |
To omit a backup battery and to miniaturize a device by using a memory element. A DC power circuit 2 connects an encoder 7 to an input port 4 of an MPU 3 via an encoder line 12 and changes an AC power supply 1 into a DC power supply. The...
|
|
JP2588270Y2 |
|
|
JP2843461B2 |
PURPOSE: To surely eliminate a low-order rank level when a card is successively used by performing a write operation by the case of a high-order rank level every time all the cases of the low-order rank level are activated and eliminatin...
|
|
JP2588271Y2 |
|
|
JP2842004B2 |
In an apparatus for testing a counter circuit, a test pattern is used to drive the counter circuit to obtain an output pattern. The output pattern is compared with an expected pattern in synchronization with the test pattern, thereby det...
|
|
JP2840905B2 |
A comparator is provided in the counter circuit to compare the counted value of clocks by a counter with the value of a register in which a target changing value of a comparison register which sets a value to be compared with the counted...
|
|
JP2838596B2 |
A high-speed counter capable of counting the number of randomly incoming pulses is constructed by serially connecting a plurality of toggle flip-flop circuits, each of which is activated by input pulses and constructed from an rf-SQUID a...
|
|
JP2838878B2 |
PURPOSE:To prevent the shape of the leading edge of the frequency division output of a second frequency division circuit from being set differently at every cycle by offsetting the change of a current on an output buffer by the influence...
|
|
JP2829965B2 |
|
|
JP2830713B2 |
PURPOSE:To improve the yield of production and to cut down the cost of production in a true frequency inspection process by removing a mulfunctioning article before the true frequency inspection process is conducted CONSTITUTION:When the...
|
|
JP2824908B2 |
A numerical value setting device which accomplishes a numerical value setting or registering operation whether a power supply is interrupted or restored during its operation has a set value registering timer. The set value registering ti...
|
|
JP2584320Y2 |
|
|
JP2818412B2 |
|
|
JPH10290156A |
To easily and efficiently test a multi-stage counter. A carry output CO of a pre-stage counter is given to an enable input EN of a next stage counter via an OR gate. A DFF 3 is set in response to a test input A to set each counter forcib...
|
|
JP2581051Y2 |
A key signal input circuit for a microcomputer including a microprocessor and a single input port. The microcomputer outputs, in sequence at a constant interval, a plurality of grid signals, receives different key signal inputs successiv...
|
|
JPH10247850A |
To reduce a circuit configuration area with the addition of a flip-flop by adopting the configuration that one flip-flop is not added to a frequency divider of a modulator prescaler, in order to provide a frequency division number of 1/(...
|
|
JP2793226B2 |
|
|
JP2793524B2 |
To provide a time measuring system which has accuracy in measurement within the cycle of a system clock, and its measuring method. This system is constituted, being equipped with a high-speed counter 1, an adder 2, and a controller 3, an...
|
|
JP2791906B2 |
|
|
JP2778527B2 |
PURPOSE: To prevent the input of an addend from getting lost by taking priority over latch and clear and delaying count enable(CE) for one bit when the differentiated output of count/latch enable(CE/LE) is matched concerning the integrat...
|
|
JP2776999B2 |
|
|
JP2772611B2 |
|
|
JPH10163858A |
To ensure a stable operation of a counter device even to an input signal that has an optional clock cycle by counting the number of clocks included in the input signal set in an optional time interval, storing the count value of the rise...
|
|
JP2767789B2 |
|
|
JPH10154929A |
To prevent the occurrence of malfunction due to fluctuation in an input level by extending the operating region with respect to the input level. An input signal S1 from a voltage controlled oscillator (VCO) 4 is given to an input termina...
|
|
JPH10150359A |
To improve the precision of a signal waveform by selecting a count-up signal corresponding to a register optionally as a timing signal for output signal inversion so as to make a multichannel scale unchange and to obtain a minute duty ra...
|
|
JPH10150360A |
To obtain a window clock signal without the use of a double frequency signal in an active phase by frequency-dividing a main clock signal, generating an AND signal, and converting the AND signal into two signals whose phases are deviated...
|
|
JP2758284B2 |
|
|
JP2758564B2 |
PURPOSE: To increase the processing speed of a frequency dividing device for frequency-dividing the standard signal with a fractional ratio having each integer of a numerator and a denominator. CONSTITUTION: The output pattern of a frequ...
|
|
JPH10132834A |
To enable surely diagnosing whether there is abnormality of an interconnection from a wheel speed sensor and a waveform shaping circuit which shapes the waveform of a wheel speed pulse. A signal line 5 which connects a wheel speed sensor...
|
|
JPH10135820A |
To inspect operation of an address counter without read/write operation to a memory array. A count of an address counter 11 is being increased sequentially depending on a clock, the number of clocks(CLK) is counted till a carry is output...
|
|
JP2754170B2 |
PURPOSE: To reduce jitters by providing a counter for counting an input clock number in the high phase and low phase of output clocks and adjusting the length of the phases while keeping fixed relation with input clocks. CONSTITUTION: Th...
|
|
JPH10126233A |
To realize the clock-generating circuit, in which the number of externally mounted components is reduced without increasing the scale of an IC and count accuracy of a counter is improved. Flip-flop circuits TFF1, TFF2 generate 1/2-freque...
|
|
JP2748401B2 |
|
|
JPH10107617A |
To obtain a frequency divider which operates in a wide frequency band and on a broad input level by outputting a signal with constant amplitude despite the amplitude value of an input signal and making an output signal the input signal o...
|
|
JPH10107616A |
To reduce current consumption when used at a low frequency and to adjust a frequency when one frequency dividing circuit is used at a plurality of frequencies by having at least either a means that switches current source current in seve...
|
|
JPH10107618A |
To use an operating frequency band of the frequency divider up to an operation limit by detecting a frequency division error without the use of a band pass filter. The circuit is provided with first and second frequency dividers 2, 3 wit...
|
|
JP2741737B2 |
|
|
JP2741708B2 |
PURPOSE:To reduce the number of terminals for testing to realize the size reduction of a chip package or utilize the terminals efficiently by utilizing the unused terminals for other functions by generating the preset data in the chip. C...
|
