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Matches 101 - 150 out of 4,883

Document Document Title
WO2004068273A3
A digital counter (e.g., Fig. 1) that uses non-volatile memories (12, 14, 16, 18, ...) as storage cells, wherein the storage cells are sub-divided into two groups, one for the implementation of a rotary counter (20, 22) that keeps track ...  
WO2004068706A3
A counter for synthesizing clock signals with minimal jitter analyzes an ongoing count to determine whether the rising edge of an output clock should be triggered by the rising edge or falling edge of an input clock signal and to further...  
WO2003019781A3
Apparatus (50) for generating an output signal (fdiv) whose frequency is lower than the frequency of an input signal (CK1, fvco). The apparatus (50) comprises a chain of frequency dividing cells (51-56), wherein each of the frequency div...  
WO/2004/077676A1
The invention relates to a phase-locking circuit (1, 5, 7, 14), wherein a frequency counter (10) is provided in addition to a phase divider (5) which is preferably programmable and which is arranged in the feedback path of the PLL, said ...  
WO/2004/068273A2
A digital counter (e.g., Fig. 1) that uses non-volatile memories (12, 14, 16, 18, …) as storage cells, wherein the storage cells are sub-divided into two groups, one for the implementation of a rotary counter (20, 22) that keeps track ...  
WO/2004/068706A2
A counter for synthesizing clock signals with minimal jitter analyzes an ongoing count to determine whether the rising edge of an output clock should be triggered by the rising edge or falling edge of an input clock signal and to further...  
WO/2004/032325A1
The invention relates to a digital counter in addition to a corresponding counting method. Said digital counter comprises a first digital counting device (1) with a first counter segment (1a) for one or more low value bits, in addition t...  
WO2002069499A3
An in-phase clock signal CLK-I drives a first pair of connected data flip-flops (DFFs) (302) and (308), with feedback through a NOR gate (310) and output through an in-phase OR gate (320). The output signal OUT-I is a clock signal with a...  
WO/2003/073607A1
MEMS-based, computer system, clock generation and oscillator circuits and LC-tank apparatus for use therein are provided and which are fabricated using a CMOS-compatible process. A micromachined inductor (L) and a pair of varactors (C) a...  
WO/2003/058817A1
A prescaler circuit comprising n DFF circuits (n≥3); a first multi-input logic gate circuit having two or more inputs; and a second multi-input logic gate circuit, wherein the output terminals of the first multi-input logic gate circui...  
WO/2003/032495A1
The invention concerns a dual-mode divider counter circuit for a frequency synthesizer comprising several 1:2 dividers of asynchronous type connected in series, a phase selector block (11) interposed between two of the 1:2 dividers (10, ...  
WO/2003/023965A2  
WO/2003/019781A2
Apparatus (50) for generating an output signal (fdiv) whose frequency is lower than the frequency of an input signal (CK1, fvco). The apparatus (50) comprises a chain of frequency dividing cells (51-56), wherein each of the frequency div...  
WO2002080369A3
A programmable fractional frequency divider enables a finer resolution of output frequency than conventional integer frequency dividers. The programmable fractional frequency divider of this invention allows for the programmability of bo...  
WO/2002/080369A2
A programmable fractional frequency divider enables a finer resolution of output frequency than conventional integer frequency dividers. The programmable fractional frequency divider of this invention allows for the programmability of bo...  
WO/2002/069499A2
An in-phase clock signal CLK$m(Y)I drives a first pair of connected data flip-flops (DFFs) (302) and (308), with feedback through a NOR gate (310) and output through an in-phase OR gate (320). The output signal OUT$m(Y)I is a clock signa...  
WO2002029973A3
A programmable divider includes a synchronous counter (202) configured to process an input clock signal and produce first output signals in response the input clock signal. A number of logic devices (210, ...,21N) are coupled to the sync...  
WO/2002/029973A2
A programmable divider includes a synchronous counter (202) configured to process an input clock signal and produce first output signals in response the input clock signal. A number of logic devices (210, ...,21N) are coupled to the sync...  
WO/2002/019526A1
A digital variable clocking circuit is provided. The variable clocking circuit is configured to receive an input clock signal and to generate an output clock signal having an output clock frequency equal to the frequency of the input clo...  
WO/2001/084710A1
The power consumption of a frequency divider can effectively be reduced when the frequency of the input signal varies by more than the division factor of a divider cell in the frequency divider. A low frequency input signal requires a lo...  
WO/2001/054267A1
A radio FM receiver is provided with a voltage-controlled oscillator which can be connected via a frequency 2-divider to a quadrature combination circuit for transforming down the frequencies of received radio signals and for supplying q...  
WO/2001/054282A1
The present invention relates to a frequency divider having an adjustable divider ratio (TV). Such circuits are subject to requests for ever higher clock frequencies. For fulfilling said requests, the inventive circuit generates the outp...  
WO/2001/050610A1
A method and an apparatus relating to a PLL circuit for frequency synthesizer applications. By using a composite PFD large and small phase variations between a reference signal and the divider output are compensated for. The composite ph...  
WO/2001/039144A1
The invention relates to a method for operating a multistage counter in only one counting direction. The inventive method comprises the following steps: changing the count value of a single-stage auxiliary counter that can only be change...  
WO/2001/029969A1
Frequency measurement units (10, 21, K0) which count reference clocks (Cb) are provided. The frequency measurement units count the reference clocks during periods shifted from each other. An adder (14) is provided which adds the counts o...  
WO/2001/029839A1
A method and apparatus for updating and storing a counter value. In response to each of a plurality of N counter update signals, a binary memory cell is selected (350) from a plurality of binary memory cells and the state of the selected...  
WO1998039845A3
A counter circuit includes a series of registers driven by two phase shifted clocks. A clock generator in the counter circuit generates four asymmetrical clock signals to drive each of the registers. The registers are formed from input a...  
WO/2000/052827A1
The inventive system and method is characterized in that the method of detection can be configured by varying the size and/or the position of a time slot to be taken into consideration for the detection and/or by varying the relevant bit...  
WO/2000/018010A1
The invention relates to an RS flip-flop and to an RS flip-flop provided with a clock input, and to a frequency divider to be implemented therewith. To produce for example a fast divider generating a clock signal with a symmetrical pulse...  
WO/2000/010251A1
A digital counter and method for counting are implemented which minimize fatigue-related failure in the storage element for the count value. The counting sequence is chosen such that the transitions within individual storage elements are...  
WO/1999/062176A1
The invention relates to a method for operating a multi-stage counter (11) in one counting direction only, comprising the following steps: altering the count value of a single-stage counter (1) which can only be altered in one direction ...  
WO/1999/027650A1
A method of accumulating and maintaining the accumulated data comprises steps of maintaining an intermediate count in a first memory device (12), reading a plurality of count values from a second memory device (14), determining a greates...  
WO/1999/013578A1
The invention relates to a counting device for the non-linear counting of events. According to the invention, a code generator generates a series of code numbers in such a way that the code numbers occur with varying frequency. Every cod...  
WO/1999/013474A1
The invention concerns a method for recording a binary word (BW) using electrically erasable and programmable memory cells (C¿i,j?) organised in word lines (WL¿i?), which consists in providing at least two word lines (WL¿i?, XWL¿i?) ...  
WO/1998/039845A2
A counter circuit includes a series of registers driven by two phase shifted clocks. A clock generator in the counter circuit generates four asymmetrical clock signals to drive each of the registers. The registers are formed from input a...  
WO/1997/033373A1
The present invention provides an encoder (100) including a processing circuit which generates an output code according to an encoding algorithm, a counter circuit for incrementing a counter value such that only one bit of the counter va...  
WO/1997/030518A1
Quality requirements on a counter may set a limit to the highest frequency that can be applied to the counter. This will also limit the resolution. According to the invention there is provided a counter comprising a generator for generat...  
WO/1997/028605A1
A shared counter (32) performs multiple counting functions in an electronic circuit, such as a memory integrated circuit. An input selection circuit (21) selects one of M input data sets at a given time to be provided as counter initiali...  
WO/1996/005657A1
An electronic counter device ("e.c.d.") comprising: (i) a counter input for receiving data representing successive counts; (ii) means for accumulating the counts received through said input; (iii) at least one count display for displayin...  
WO/1993/020618A1
Power dissipation of a CMOS circuit such as a microprocessor is reduced by dynamically slowing down the microprocessor clock (CLKOUT) during selected system operations such as hold, wait or ATperipheral bus access cycles. The microproces...  
WO/1993/019346A1
A high security counting system is shown for counting events represented by an event signal. The counting system includes a nonerasable programmable read only memory (15) which is programmed by a programmer (14) under the control of a co...  
WO/1991/018395A1
In a circuit array with M-rows and N-columns a logical element (10) is arranged at each intersection between a row and a column. The first input of the logical element is connected to a corresponding row (m; element of M) and its second ...  
WO/1991/011726A1
A binary counter (60) provides for resolution doubling by producing a wavetrain (Q0) which represents the zero-order bit of the counter and has the same frequency as the clock input (REFCLOCK).  
WO/1990/007232A1
A programmable counter or frequency divider includes the combination of a fixed modulus prescaler (110) and a programmable divider (120, 130, 140, 150, 160) in which the prescaler provides more than a single clock phase to the programmab...  
WO/1990/005413A1
A high speed digital programmable frequency divider (10') capable of frequency division by even and odd integers is disclosed herein. The frequency divider (10') of the present invention includes a waveform generator (20') for providing ...  
WO/1988/000775A1
An electronic counter such as for use in the odometer of a motor vehicle is provided comprising an array (10) of m rows and n columns of single flip-flop data latches and a central shifting unit (CSU) (14). The CSU (14) comprises a row o...  
WO1987007968A3  
WO/1987/007968A2
A multi-mode counter network and a method of testing the operation of the multi-mode counter network. The multi-mode counter network comprises a counter circuit formed of a plurality of counter registers and a multiplexer circuit formed ...  
WO/1987/007992A1
A look ahead terminal counter and a method for generating a terminal count output signal. The counter comprises a plurality of counter registers connected to counter enable circuitry for sequencing the registers at a predetermined counte...  
WO/1987/005453A1
A counting circuit which counts the number of pulses asynchronously input during a predetermined period of time includes a counter (C') which counts the number of input pulses, a register (D) which stores the pulses emitted from the coun...  

Matches 101 - 150 out of 4,883