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Matches 301 - 350 out of 4,888

Document Document Title
JP2010118981A
To change a counter that counts signals to be counted, without changing wiring of signals to be counted to a count input circuit, or to supply signals to be counted to be supplied to one counter input circuit to a plurality of counters i...  
JP2010114581A
To provide a small-scale counter circuit having a high error detection rate.The counter circuit includes: a first counter which counts a numerical value to output a count value; a second counter which is synchronized with the first count...  
JP2010114888A
To provide a circuit for enhancing a duty cycle resolution by reducing jitter of an output clock signal.A counter for synthesizing clock signals with minimal jitter analyzes an ongoing count to determine whether the rising edge of an out...  
JP2010109606A
To provide a counter circuit having a simple circuit configuration, reducing an inspection time and suppressing cost increase.The counter circuit for counting a clock signal outputted from an oscillator and counting time has a fuse 13 fo...  
JP4458699B2  
JP4448128B2  
JP2010074637A
To provide a reliable up/down counter with a simple circuitry without using an external clock.The up/down counter device 10 outputs an up/down state signal (C) from two-phase pulse signals (A), (B) input to an up/down decoder 12 and gene...  
JP4434889B2  
JP4434277B2  
JPWO2008056551A1
分周クロック信号のサイクル時間が一定で、 消費電力やレイアウト面積が小さく、設計・ 検証コストが小さい有理数分周回路を提供す る。分周比がN/M(M、Nは正の整数...  
JP2010041466A
To perform high-precision variable frequency division by setting a variable frequency division ratio in a simple circuit configuration.A 1/P frequency divider 12 subjects an input clock ck to 1/P frequency division. A phase shifter 13 sh...  
JP2010011389A
To achieve a frequency divider, in a simple configuration and with high accuracy, such as a baud rate generator that does not use any dedicated oscillator, wherein an error of a frequency to be divided is allowed.As a frequency divider, ...  
JP4386725B2  
JP2009290775A
To provide a re-timing circuit and a frequency dividing system capable of preventing malfunction when the timing of a synchronous edge in a clock signal coincides with that of an edge in an input signal.The re-timing circuit including a ...  
JP2009543470A
The modulus counting-down circuit stage (MDS) includes the 1st and the 2nd stage. MDS receives the number control signal S of modulus 除 which determines by any the MDS shall operate between 2 division mode or trichotomy mode. The stage...  
JP4371046B2  
JP2009540339A
With radiation detector 10 of flight time-type poistron-emission-tomography (PET) scanner 2, radiation detection part 20 generates signal 22 showing a radiation detection phenomenon. Digital delay element 40 interconnection of the operat...  
JP4356487B2  
JP2009222431A
To provide a coulomb counter which reduces a circuit scale, makes the dynamic range and current resolution of a measuring current variable for optimization and outputs counted values with few errors.The coulomb counter outputs the counte...  
JP2009218877A
To reduce a power consumption in an always-on counter circuit.A counter circuit has a first counter of m bits which counts values of a predetermined bit width to be stored according to an input clock, a clock transmission control circuit...  
JP2009194459A
To provide a monitoring circuit which can perform monitoring, using a comparatively small area and in a simple manner.A monitoring circuit comprises a circuit for controlling resources which is supplied to a function block, a capacitor c...  
JP4303528B2  
JP2009165064A
To provide a frequency dividing circuit and frequency dividing method capable of synchronizing all frequency divided signals and outputting the frequency divided signals synchronized with the same edge of a clock signal in signals freque...  
JP4299850B2  
JP4296690B2  
JP2009152886A
To enable generation of clock signal of a desired frequency from one reference signal in a clock generating circuit for generating a clock signal multiplied or divided in frequency from the reference signal.The clock generating circuit 1...  
JP2009147936A
To provide a dual-modulus prescaler circuit which has a relatively simple structure according to a CMOS technology and operates at a very high frequency.The circuit includes an assembly formed of two D-type flip-flops 12, 13, and two NAN...  
JP2009135854A
To sufficiently prolong a service life in updating the number of times of rewriting without limiting memory regions to be used as a counter.A data conversion unit 34-1 divides data to be written to, for example, a non-volatile memory 32 ...  
JP2009130822A
To align parallel data in accordance with bit shift of a synchronizing pattern, in simple circuit configuration, without increasing a circuit scale, power consumption and latency.A synchronizing pattern is detected by a synchronizing pat...  
JP2009518990A
A clock generation machine (1, 54, 111, 120, 130) with which an electric counter circuit (30, 40, 80) generates a plurality of clock signals (21*24, 121*125, 131*134), Sampling equipment (32, 81) which samples a clock signal (21*24, 121*...  
JP2009094551A
To achieve a counter device which can enhance time precision of a counter and can facilitate timing verification and layout work of logic IC design.The counter device performing count operation by dividing the frequency of a clock signal...  
JP2009516980A
The present invention provides a pressure sensing device which uses a time * digital conversion circuit and it. A time delay variable region in which the circuit generates a standard signal which has a fixed time delay, and a sensing sig...  
JP2009088841A
To provide a pulse generator capable of changing a pulse generation condition in seamless manner even if generating/stopping output pulse signals based on a command signal from the outside of the generator.The pulse generator 100 compris...  
JP2009088953A
To attain a pulse input device by which the optimal accuracy and the optimal response time can be obtained according to a frequency of an input signal.The pulse input device detects the input signal as a pulse signal and notifies a host ...  
JP4246166B2  
JP4240657B2  
JP4214958B2  
JP4206151B2  
JP2008311998A
To exactly count clock signals whose frequencies or duties vary.The clock number count circuit 30 includes: an upcounter 1; a generation circuit 2, an arithmetic circuit 3; a terminal Pad1; and a terminal Pad2. The upcounter 1 inputs the...  
JP4199664B2  
JP2008545320A
In other bits, a programmable module type digital frequency divider does division of the input frequency by the integer divisor of m bit, and generates output frequency. An integer divisor carries out reinitialization of several meters o...  
JP2008301488A
To provide circuit and a method for programmable integer clock division with 50% duty cycle.The present invention relates to circuits and a method for dividing a frequency of an input signal by an integer divider value. The circuit gener...  
JP2008301325A
To prevent timing of output signals from being deviated in a synchronous type counter circuit by taking layout into account.A counter circuit outputs count values Q0-Q15 of MN bits using M (e.g., four) pieces of N-bit (e.g., 4-bit) synch...  
JP2008289179A
To accomplish an interlocked counter capable of adjusting a count value at all times in response to an interlocking signal output from another interlocked counter even when interlocked counters not communicating interlocking signals with...  
JP4180479B2  
JP4157940B2  
JP2008211460A
To provide a counter comprising an electronic circuit in which reset or alteration of count value by methods other than circuit destruction is impossible and can hold the value after the count value has reached a count limit value.In an ...  
JP4149634B2  
JP2008196917A
To provide an asynchronous type counter circuit performing verification to a supply pass of a clock signal without complicating a circuit, and improving a failure detection rate.This circuit is equipped with: a plurality of flip-flop cir...  
JP2008193235A
To provide a phase-compensated clock divider circuit controlling the frequency-divided clock to be always synchronized with a synchronizing signal, and preventing malfunction or delay in operation.The phase-compensated clock divider circ...  

Matches 301 - 350 out of 4,888