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JP2005223829A |
To provide a fractional frequency divider circuit which reduces its circuit scale and outputs a clock of a duty ratio 50%, and data transmission apparatus having the frequency divider circuit.A fractional frequency divider circuit includ...
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JP2005210332A |
To provide a timer counter capable of ensuring reliability of measurements even when it is difficult to provide timer counters of identical precision.The timer counter comprises a plurality of registers receiving data in response to a tr...
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JP2005210610A |
To provide an IF counting system which realizes an IF counter in a smaller circuit configuration, with regard to the IF counting system in the IF counter used in a radio receiver.An IF counter is comprised of: a down count type IF count ...
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JP3674982B2 |
PURPOSE: To reduce the scale of a variable delay circuit by providing a rate switching circuit which extracts the pulses outputted from the variable delay circuit every time the count value of a counter is equal to the prescribed value. ...
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JP2005518746A |
MEMS-based, computer system, clock generation and oscillator circuits and LC-tank apparatus for use therein are provided and which are fabricated using a CMOS-compatible process. A micromachined inductor (L) and a pair of varactors (C) a...
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JP2005159737A |
To speed up operating speed in a frequency dividing circuit in a variable frequency dividing circuit effective to a circuit that has a number of dividing stages and requires high-speed operation.There are provided a shift register compos...
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JP3643236B2 |
To reduce the memory capacity required for storing data. This apparatus is provided with an m-bit counter 15 for repeatedly performing the counting synchronously with a system clock, a capture pulse generator 13 to detect a change point ...
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JP3641810B2 |
PURPOSE: To obtain the preset counter having an initial setting function easily set by a user in which the number of initial setting items is limited. CONSTITUTION: This counter is provided with a switch section 13 used to initial- set a...
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JP2005045507A |
To provide a non-integer frequency divider that can be constituted by combining the circuits with simple functions and whose frequency division ratio can simply be set.This non-integer frequency divider has an adder 11 which adds a 1st s...
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JP2005037169A |
To provide a semiconductor integrated circuit allowing knowledge of power consumption of each functional block.This semiconductor integrated circuit has: first to third signal processing circuits 11-13 respectively operating in synchroni...
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JP3616261B2 |
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JP2005012515A |
To provide a variable frequency divider by eliminating a path with a greater capacity load such as a critical path and to achieve low power consumption.A feedback path 207 is formed between an output of a fixed frequency divider 205 and ...
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JP3609601B2 |
To easily confirm whether timer counter operation is normal or abnormal by incorporating a function for detecting the counter operation being abnormal according to the result of logical operation between the time of the timer counter cir...
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JP3601961B2 |
A dual-modulus prescaler (100) has improved performance for high-speed operation. A timing signal is developed from a flip flop circuit (106) two and one-half clock cycles before the last stage of the prescaler is clocked. The timing sig...
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JP3592376B2 |
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JP2004318727A |
To provide an analog monitor circuit which is suitable for an ASIC, requires a smaller number of external components and is low in cost.The analog monitor circuit is provided with a register 31, an accumulator 33 provided in the register...
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JP3585114B2 |
To provide a frequency divider that can selectively output a fundamental wave without increasing number of signal lines for frequency divider control. The frequency divider is provided with a frequency divider integrated circuit 1 that f...
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JP2004304381A |
To provide a counting device and a counting method capable of drastically reducing power to be consumed in an internal circuit and stabilizing a counting operation by power from an input pulse.Read operation processing and write operatio...
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JP3578690B2 |
To provide a variable cycle counter which is able to adjust phase frequently even if external conditions like a delay in signal transmission change during the operation and does not lower its operating frequency even if the number of dig...
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JP3575980B2 |
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JP3573824B2 |
PURPOSE:To improve the yield of a whole shift register circuit consisting of a thin film transistor by turning the shift register circuit into a redundant one. CONSTITUTION:A shift register SR row includes the shift registers SRAi-SRZi c...
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JP3566342B2 |
PURPOSE: To provide a parallelly operated high-speed counter for making high- speed counting possible by parallelly operating the two counters of two system for the high-speed counting impossible by one counter. CONSTITUTION: This counte...
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JP3563198B2 |
To control counting of an up-down counter circuit with two input terminals. When input signals given to two input terminals 1, 2 both set to a low level, a value of the counter is reset to '0'. When an input signal of either of the two i...
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JP3559396B2 |
A first amplifier circuit having a high frequency characteristic and a second amplifier circuit having a low frequency characteristic have first and second input terminals, respectively. The first and second amplifier circuits have first...
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JP2004242283A |
To provide a frequency divider circuit, a PLL circuit and a semiconductor integrated circuit in which high-speed operation is realized, and a desired frequency dividing ratio is obtained without generating switching noise.The circuit of ...
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JP2004228812A |
To provide a frequency divider which can operate with low consumption power at high speed.Two-frequency dividers 10 and 30-50 are each constituted of a D flip-flop composed of an NMOS source coupled logic and having an NMOS transistor gr...
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JP3552426B2 |
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JP3548925B2 |
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JP3550868B2 |
To reduce the minimum variable width while keeping nearly constant a maximum variable range of the variable delay circuit. The variable delay circuit is made up of a counter CNT, current sources SW1, SW2-SWn, controlled by the counter CN...
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JP3550853B2 |
To reduce circuit scale and to reduce costs through elimination of a subtracter by providing a D flip-flop in place of an overflow detector. When the output of a D flip-flop 5 for delaying the carry output of a j-bit adder 4 equipped wit...
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JP3544791B2 |
To decrease malfunctions due to timing deviation by providing a 2-input OR circuit to a post-stage of a flip-flop and obtaining an OR between an output of the flip-flop and a clock signal, while using a buffer so as to set the same delay...
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JP2004200872A |
To provide a counter circuit operating at a desired phase independently of an initial state such as in power rising.A reset pulse generating circuit (3) performs decoding when a counter output (SB1) is a prescribed value Y-a and outputs ...
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JP3540589B2 |
To provide a clock multiplying circuit which can make a frequency comparison fast, has a short lock-in time, is stable and has less jitter for generating a clock signal of high frequency with a large multiplication number from an input c...
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JP2004519958A |
A programmable fractional frequency divider enables a finer resolution of output frequency than conventional integer frequency dividers. The programmable fractional frequency divider of this invention allows for the programmability of bo...
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JP2004165757A |
To provide a device capable of suppressing a clock frequency to low because a circuit operates at the frequency of an input clock, and reducing the power consumption of the circuit and heat generation associated therewith.The circuit for...
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JP2004146925A |
To prevent malfunction caused in an unstable state until a value of write data from an external unit is defined.The pulse generator is provided with: a counter 104 for counting clocks; a comparator 105 for detecting coincidental comparis...
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JP3517331B2 |
To measure a counting rate by removing noise to prevent erroneous counting due to noise. A counting rate is measured by normal measuring means with a feedback type counting rate meter comprising an up/down counter 1, a pulse generator 2 ...
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JP3510737B2 |
To allow the circuit to easily detect a phase difference of two kinds of signals (horizontal synchronization signal HS and reference clock signal). A decoder 12 decodes a count of a counter 11, counting the number of reference clock sign...
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JP3510903B2 |
PURPOSE: To provide a high-speed adder (provided with a subtractor) and a counter constituted of a programmable lookup table in a programmable logic device. CONSTITUTION: A conventional lookup table 10 is divided into smaller lookup tabl...
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JP2004062580A |
To provide a counter system and a method for counting, which enables the operator to measure the number of rotation of various repeated motions per unit time using a single measuring device by making the measuring device to specified sen...
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JP2004056717A |
To provide a semiconductor device for clock generator, a system board, and a multi-phase clock generating circuit in which stable operations of a circuit is made possible and an output clock signal of a uniform duty ratio is obtained by ...
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JP2004054932A |
To provide hardware base utilization measuring apparatus used in a computer system having one or a plurality of central processing units.The hardware based utilization measuring apparatus and a corresponding method is used in the compute...
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JP3491372B2 |
PURPOSE: To establish a failure sensing method for input capture circuit, which can make failure sensing at a low cost without enlarging the magnitude of the circuit configuration. CONSTITUTION: An input capture circuit is equipped with ...
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JP3479145B2 |
PURPOSE: To obtain an apparatus for measuring the distance accurately using an ultrasonic receiving signal. CONSTITUTION: An ultrasonic oscillator 1 is connected with a transmitting circuit 2 and a receiving circuit 3 connected with an A...
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JP3471268B2 |
To provide a logic circuit capable of securing a wide timing margin in control signals even under a high-speed operation and improving operation accuracy. The control signals tA, tB, tC and tD successively rise at each half clock of an e...
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JP3468964B2 |
To prevent malfunction of a prescaler for the operation delay of a swallow counter and to enable a high speed operation. A swallow counter is provided with a malfunction prevention circuit part 42. When all the set value data A1 to A7 su...
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JP3470189B2 |
PURPOSE: To arbitrarily set a display range of a count value and a display digit of a decimal point by converting data of each digit to display data, and also, setting decimal point data to the display data at the time when its digit is ...
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JP2003533084A |
The power consumption of a frequency-divider can effectively be reduced when the frequency of the input signal varies by more than the division factor of a divider cell in the frequency divider. A low frequency input signal requires a lo...
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JP2003309466A |
To provide a cascadable divide-by-two binary counter circuit for use as a synchronous divider circuit in a phase lock loop.This binary counter circuit 120 is composed of a D-FF (D flip- flop) 122 and cascaded. An AND gate 124 is responsi...
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JP2003309465A |
To provide a semiconductor device capable of correcting step-out of a plurality of counters at optional timing.This semiconductor device has first and second control parts. The first and second control parts receive first and second cloc...
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