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Patent Searching and Data


Matches 351 - 400 out of 4,888

Document Document Title
JP2008172649A
To share a counter among a plurality of dividers with different division ratios and phases, and to reduce a logical amount and the power consumption of the whole divider circuit by making the division ratio and the phase of the divider i...  
JP2008172512A
To provide a frequency synthesizer capable of realizing frequency division of high precision while suppressing circuit increase, without using a PLL of a conventional configuration, and to provide a clock generation method.The frequency ...  
JP4122262B2  
JP4114722B2  
JP4111932B2  
JP4112699B2  
JP2008520154A
The present invention relates to the method and equipment which offer 1st at least one output signal (O_Q) that has the frequency which can lead dividing clock signal (CL1) frequency for an odd number integer. A digital value is shifted ...  
JP2008131071A
To provide a gray code counter, where the number of delay flip-flops is reduced and current consumption is reduced.The gray code counter has four DFFs 11, 12, 13, 14 for holding respective bits Q3, Q2, Q1, Q0 of a gray code, a reference ...  
JPWO2008065869A
[Subject] The rational number part circumference way where change of the cycle time of a 分周 clock signal is small, there are many opportunities for the minimum cycle time of a 分周 clock signal to be expanded according to a 分周 ...  
JPWO2008056551A
A rational number part circumference way where cycle time of a 分周 clock signal is constant, power consumption and layout area are small, and design / verification cost is small is provided. In a clock signal part circumference way wh...  
JP4081674B2  
JP4077483B2  
JP2008085543A
To provide a counter circuit capable of increasing the number of countable counts without increasing a hardware circuit scale.An n-bit hardware counter 12 sequentially counts output signals of a pulse string generating means 16 for gener...  
JP2008509590A
The frequency divider equipped with the 1st latch circuitry (10) and 2nd latch circuitry (10') by which intersection combination of the 2nd latch circuitry (10') is carried out in the 1st latch circuitry (10). Each latch (10, 10') contai...  
JP2008035452A
To provide a clock generating circuit in which an output clock of a weak side band can be obtained by relaxing periodicity even on such an output frequency generation condition that periodicity may occur.A counter 22 counts the number of...  
JP4046528B2  
JP4044819B2  
JP2008016931A
To provide a synchronization control method relaxing timing constraints of a global signal even when a high speed operating clock is in use.A detection circuit 12 detects an issue or a release of an operating signal (e.g. reset signal) f...  
JP4038222B2  
JP2007538473A
The two or more place of a wide range which has the 1st clock generation circuit, a frequency division circuit, and two or more multiplexers is a phase clock generation machine. The 1st clock generation circuit generates two or more 1st ...  
JP3998676B2  
JP2007528657A
As for the present invention, this divider has a latch (10) and the 2nd latch (20) of the 1st about a divider, and intersection combination of the 2nd latch (20) is carried out with the 1st latch. The 1st latch (10) has a clock input whi...  
JP3985588B2  
JP3980203B2  
JP2007243618A
To provide a frequency divider circuit for reducing the ratio of a large power consumption circuit, such as a buffer circuit, and avoiding the increase of power consumption due to a limited layout by placing the frequency divider circuit...  
JP2007235960A
To provide an integrated circuit device which generates a plurality of drowsy clock signals having different phases. The integrated circuit device includes a phase synchronizer configured to output a plurality of clock signals having dif...  
JP2007235578A
To provide a clock generation circuit which can be commonly used in a plurality of different broadcasting systems and achieve simplification and miniaturization of a circuit composition. While using a voltage controlled oscillator 11 wit...  
JP2007215213A
To provide a method for multiple-phase clock generation. In one embodiment, a multiple-stage voltage controlled oscillator ("VCO") (302) transmits a plurality of clock phases (ck0-ck5) to a clock divider (304) which produces the desired ...  
JP3962455B2
To provide a method for reducing the power consumption of a digital circuit while maintaining an operation with a high frequency. This is a clock mechanism which uses an outside clock signal with a frequency F, and generates an inside ma...  
JP2007208589A
To enable an n-division harmonic frequency divider (wherein, n is an integer of two or above) to be easily configured. The harmonic frequency divider 30 includes a harmonic mixer 32, a resonance circuit 34, and a buffer 36. The harmonic ...  
JP2007522712A
The phase locked loop composition containing the antenna coil, the antenna resonance capacitor, the rectifier, the voltage control ring oscillator, phase detector, and loop filter which cause a differential input signal is used for an un...  
JP2007521713A
The counter for compounding the clock signal equipped with the minimum jitter, In order to determine whether the trigger of the rising edge of an output clock must be carried out by the rising edge or falling edge of an input clock signa...  
JP3949995B2
To provide a counter circuit capable of forming a plurality of pulse signals of different periods, without increasing the circuit scale. The counter circuit comprises an initial value register single port RAM 5, having initial value regi...  
JP3940877B2
To provide a pulse output device that eliminates the need for error correction of an oscillation frequency and can realize synchronization with an execution period of (input data from) an external processing unit, such as a CPU and that ...  
JP3941376B2
To provide a signal distributing device and a signal distributing method by which waveform deterioration or delay, etc., caused by a wiring length between printed boards is hardly received in a unit where the multiple printed substrate a...  
JP3935901B2
To provide a programmable low-power high-frequency divider circuit. A fast latch includes: a NAND stage adapted to receive a clock signal and a data input signal; a clocked inverter stage wherein a first input of the clocked inverter sta...  
JP3930773B2
To provide a frequency correction circuit for precisely correcting a clock signal of an oscillation frequency with a simple structure without adjusting the oscillation frequency in an oscillation circuit. Into the TBC(time-base counter)1...  
JP3918276B2
To provide a failure detecting method capable of detecting failure of a timer and a bus line between a timer and capture resistor at low cost without enlarging the scale of a circuit for failure detection, and not requiring an interrupt ...  
JP2007124314A
To provide a frequency divider for preventing the occurrence of glitch.A first counter 21 of a divider circuit 2a is operated in synchronism with a rising edge of a reference clock signal ICK and generates a first division signal RCK, wh...  
JP2007104020A
To provide a pulse counter, where the different input system of pulses is commonalized.The pulse counter comprises: a common input terminal T connected via a cable CB1 connected to a terminal PMo of other devices, where pulses are output...  
JP2007074434A
To prevent erroneous latch of a count value read by a host control part.When (start timing of) a host control part latch signal 15 from the host control part 23 matches to sampling timing of a sampling clock 18, a reading register latch ...  
JP3891877B2
To change the average frequency of a clock signal independently from a reference clock signal. A reference clock signal generating circuit 1 generates a reference clock signa. A dividing circuit 2 divides the reference clock signal by a ...  
JP3893902B2
To provide an image forming device and a method for updating information in the device by which count data is updated speedily to a storage element such as a semiconductor memory. The count data is constituted by two-byte gray codes. The...  
JP3868505B2  
JP3869428B2
To provide a counting device which satisfies fail safe counting performance not performing rash counting output in a failure time, and is excellent in reliability. The device comprises a counter 100 which generates an output, when counti...  
JP3857916B2
To make it possible to be operated with a small signal amplitude and reduce power consumption in a two-modulus prescaler circuit available for a frequency synthesizer or the like. The prescaler circuit is provided with n pieces of (n≥3...  
JP3850367B2
To change a frequency dividing ratio of a clock signal without enlarging a circuit scale. Whenever a reference clock signal is inputted from a reference clock signal source 20, output signals of stages Q2 and Q3 of a counter changing out...  
JP2006314134A
To provide a high-speed counter circuit which produces digital counts, with a plurality of bits to control the timing of operations in a memory device.A counter circuit includes a series of registers driven by two phase shifted clocks. A...  
JP3847150B2
To provide a semiconductor integrated circuit, which can measure accurately frequencies and jitters of the built-in PLL (phase locked loop), and measurement method for its jitters. A master clock signal MCK obtained by N multiplication o...  
JP3825722B2
To provide a semiconductor circuit device for making it unnecessary to synchronously arbitrate an interface between a block synchronizing with a source clock and an integrated circuit part operating with a frequency different from the so...  

Matches 351 - 400 out of 4,888