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Matches 401 - 450 out of 4,883

Document Document Title
JP2006222515A
To provide a technology for preventing mis-update of registers in a real time clock module.The real time clock module is configured for the purpose of suppressing occurrence of hazard by including: a first register (43) capable of captur...  
JP2006201856A
To exclude the erroneous update of a register in a real time clock module.This semiconductor integrated circuit is configured of a real time clock module (16) for performing a count operation based on a first clock signal and a CPU to be...  
JPWO2004112250A1
統計情報を計数する複数の統計カウンタで構 成された統計カウンタ装置100に関し、統 計カウンタのビット数を動的に制御すること によりハード規模及び消費電力を削減す...  
JPWO2004105247A1
固定分周器(305)の出力(310c)と 反転/非反転器(304)の制御端子(31 0b)との間にフィードバックパス(307 )を形成する。フィードバックパス(3...  
JP2006174098A
To reduce a circuit scale in a frequency divider circuit capable of generating a dividing clock at an arbitrary division ratio.The frequency divider circuit comprises a counting circuit and a comparison circuit. The counting circuit coun...  
JP2006162257A
To provide an operating mode setting circuit for surely setting a test mode of various kinds, even when a manual evaluation tool is used.A logic circuit 11 is reset by a system reset signal SRST, while resetting FFs 17 and 18 and a count...  
JP3789063B2
To obtain a symbol clock regeneration circuit with a simple configuration that can conduct high-speed phase locking and generates a stable recovery symbol clock signal even in the case that a carrier frequency error is high and a phase o...  
JP2006148807A
To generate a clock signal of a desired frequency by dividing a frequency of the clock signal in an arbitrary frequency dividing ratio.An adder 108 inputs a numerator setting value N and the last added result from a register 109 and outp...  
JP2006140676A
To realize a method and an apparatus for diagnosing a pulse input circuit, using a simple constitution which will not conduct diagnosis due to temporary noises.The method of diagnosing a pulse input circuit respectively counts the number...  
JP3779500B2
To provide a burst-type RAM device having a double-data speed method and consisting of improved address generating and decoding circuits, and address generating method thereof. A burst-type RAM device has a memory cell array for storing ...  
JP3773250B2
To provide a synthesizer and a signal analyzer which perform edge arrangement of exact and high resolution without necessity of system clock of frequency very higher than frequency of a synthetic clock signal. It comprises a system clock...  
JP3771223B2
To provide a timing adjuster in which a required time can be set accurately without using a capacitor for adjusting the time and drift of a set adjusting time is reduced. An input signal Vina is converted into a digital signal by an AD c...  
JP2006513507A
It is a digital counter (for example, Fig. 1) using nonvolatile memory (12, 14, 16, 18, --) as a storage cell, A storage cell is subdivided by two groups and two groups are the counters for realization of the rotary counter (20, 22) whic...  
JP2006080917A
To provide a current mode type input logic gate circuit which can lower minimum power supply voltage without sacrificing rapidity and operates at lower voltage (e.g., ≤1 V), a latch circuit, a flip-flop circuit, a frequency dividing ci...  
JP3732556B2
To improve considerably a clock skew between a signal via a through- path and a frequency divided signal via a frequency divided path from a same clock signal source in the clock supply circuit. The circuit is provided with a clock signa...  
JP2006005431A
To provide a counter circuit having no error even if an operation is initiated at a random timing and capable of reducing power consumption.If an operation control signal EN is provided, a frequency dividing clock generator 10 outputs a ...  
JP3727206B2
To provide a clock changing circuit which changes clocks even though clocks before and after changing include jitter and also, control input signals for write and read are not inputted from the outside. This circuit detects a clock CLK-1...  
JP2005333567A
To provide a trigger signal generating circuit which is operable at high speed for generating a frequency-divided clock having a duty ratio of 50%.1st to Pth (P is an integer) sub-counters (SC1-SCP) provided in parallel and capable of co...  
JP2005333652A
To provide a technology relating to state correction for error correction.In a state circuit, a first flip-flop is connected to a second flip-flop. A state correction circuit is connected to the output of the second flip-flop. A third fl...  
JP3715290B2
To improve qualities of a video controller and a product incorporated with the video controller and to reduce a required effort and cost. This video synchronization testing method comprises: a process for constructing a display mode tabl...  
JP3714875B2
To provide a gray code counter, with which skip counting is enabled and the number of bit transitions in skip counting is two at all the time. This gray code counter is provided with a gray code counter 2 in the configuration of 5 bits f...  
JP2005283408A
To provide a counting device for further contracting a measuring error of a predetermined period.A level of a clock signal CLK in rise and descent edge of a signal TERM being a measuring object of the predetermined period is detected by ...  
JP2005287007A
To provide a multi-mode radio apparatus which makes a circuit scale small by sharing frequency dividers and combining them upon setting the number of frequency division and by eliminating a phase error of an output.A frequency dividing p...  
JP3703347B2
To provide a frequency divider circuit from which a frequency division ratio of 2 over odd numbers with a simple circuit configuration. The frequency divider circuit comprises a flip-flop multi-stage circuit G consisting of n-sets of fli...  
JP2005260529A
To compare outputs of a plurality of counters without malfunctioning a count value when the outputs of a plurality of counters operating by different frequencies (asynchronously) are compared.When a count value a1 of a first counter 10 o...  
JP2005251370A
To provide a delay locked loop in which jitter is reduced during a high frequency operation, generation of a hole during the initialization operation of the delay locked loop is suppressed and a reset command signal normally functions.Th...  
JP3691310B2
To provide a frequency measuring circuit which provides high measurement precision even in the case of a short counting period or a reference clock having a low frequency. In the frequency measuring circuit, plural frequency measuring un...  
JP2005233885A
To provide a meter controller capable of shortening the times of second clock oscillation and of estimating the oscillation time.The meter controller is provided with a reference clock oscillator which generates a reference clock for mea...  
JP3688683B2
To generate a precise fraction frequency division signal irrespective of precision of a decimal part of a frequency-divided number. A cumulative adder 7 performs cumulative addition of a decimal value f set in an f setting part 8 in resp...  
JP2005223829A
To provide a fractional frequency divider circuit which reduces its circuit scale and outputs a clock of a duty ratio 50%, and data transmission apparatus having the frequency divider circuit.A fractional frequency divider circuit includ...  
JP2005210332A
To provide a timer counter capable of ensuring reliability of measurements even when it is difficult to provide timer counters of identical precision.The timer counter comprises a plurality of registers receiving data in response to a tr...  
JP2005210610A
To provide an IF counting system which realizes an IF counter in a smaller circuit configuration, with regard to the IF counting system in the IF counter used in a radio receiver.An IF counter is comprised of: a down count type IF count ...  
JP3674982B2
PURPOSE: To reduce the scale of a variable delay circuit by providing a rate switching circuit which extracts the pulses outputted from the variable delay circuit every time the count value of a counter is equal to the prescribed value. ...  
JP2005518746A
MEMS-based, computer system, clock generation and oscillator circuits and LC-tank apparatus for use therein are provided and which are fabricated using a CMOS-compatible process. A micromachined inductor (L) and a pair of varactors (C) a...  
JP2005159737A
To speed up operating speed in a frequency dividing circuit in a variable frequency dividing circuit effective to a circuit that has a number of dividing stages and requires high-speed operation.There are provided a shift register compos...  
JP2005129211A
To provide a shift register control circuit for completely turning off the transistor of the control circuit.The bidirectional shift register circuit includes a plurality of shift resisters, input and output terminals, and a plurality of...  
JP3643236B2
To reduce the memory capacity required for storing data. This apparatus is provided with an m-bit counter 15 for repeatedly performing the counting synchronously with a system clock, a capture pulse generator 13 to detect a change point ...  
JP3641810B2
PURPOSE: To obtain the preset counter having an initial setting function easily set by a user in which the number of initial setting items is limited. CONSTITUTION: This counter is provided with a switch section 13 used to initial- set a...  
JP2005094753A
To provide a programmable low-power high-frequency divider circuit.A fast latch includes: a NAND stage adapted to receive a clock signal and a data input signal; a clocked inverter stage wherein a first input of the clocked inverter stag...  
JP2005508108A
It is equipment (50) for generating the output signal (fdiv) which has frequency lower than the frequency of an input signal (CK1, fvco). Have equipment (50) and the chain of a dividing cell (51 to 56) each of a dividing cell (51 to 56),...  
JP2005505979A
Some 1: 2 asynchronous dividers to which the present invention was connected in series (10, 12), It is related with 2 Mohd dividing counting circuit equipped with phase selector Brock (11) inserted between two dividers [1: 2] (10, 12), a...  
JP2005045507A
To provide a non-integer frequency divider that can be constituted by combining the circuits with simple functions and whose frequency division ratio can simply be set.This non-integer frequency divider has an adder 11 which adds a 1st s...  
JP2005037169A
To provide a semiconductor integrated circuit allowing knowledge of power consumption of each functional block.This semiconductor integrated circuit has: first to third signal processing circuits 11-13 respectively operating in synchroni...  
JP3616261B2  
JP2005012515A
To provide a variable frequency divider by eliminating a path with a greater capacity load such as a critical path and to achieve low power consumption.A feedback path 207 is formed between an output of a fixed frequency divider 205 and ...  
JP3609601B2
To easily confirm whether timer counter operation is normal or abnormal by incorporating a function for detecting the counter operation being abnormal according to the result of logical operation between the time of the timer counter cir...  
JP2004364123A
To provide a frequency division ratio output device for a frequency divider with simple configuration, which sets a frequency division ratio to a value that is not higher than a decimal point and outputs the frequency division ratio.This...  
JPWO2004112250A
In order to reduce a hard scale and power consumption by controlling the number of bits of a statistics counter dynamically about statistics counter terminal 100 which comprised a plurality of statistics counters which calculate statisti...  
JP3601961B2  
JP2004343530A
To improve qualities of a video controller and a product incorporated with the video controller and to reduce a required effort and cost.This video synchronization testing method comprises: a process for constructing a display mode table...  

Matches 401 - 450 out of 4,883