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Matches 501 - 550 out of 6,225

Document Document Title
JPWO2010050098A1
本発明にかかるクロック分周回路11は、N /Sにより規定された分周比に基づいて、入 力クロック信号のS個のクロック・パルスの うち、(S−N)個分のクロック・パル...  
JPWO2010050097A
The clock part circumference way which generates the clock signal which makes it possible to perform the right communication operation expected in communication with the circuit which operates with the clock of different frequency is pro...  
JPWO2010050098A
Based on the 分周 ratio specified by N/S, clock part circumference way 11 concerning the present invention carries out the mask of the clock pulse for (S*N) 個 among S clock pulses of an input clock signal, and generates the output cl...  
JP2012039296A
To provide a counter circuit where jitters are equivalent to those of a synchronous type counter, the counter circuit making it possible to change the pulse width of the output wave of an output signal.The counter circuit comprises: shif...  
JP2012503443A
A latch includes three circuits. The first circuit drives a first output (QB) to a first level when a first input (D) and a first clock phase (CK) are both low, to a second level when D and CK are both high, and provides high impedance (...  
JP2012014183A
To provide a driving circuit of a semiconductor display device, that can provide an excellent image with high definition and high resolution without image unevenness regardless of the variation in TFT characteristic, and to provide a sem...  
JP4856458B2  
JP2012501110A
According to this indication, a multi-module counting-down circuit (MMD) circuit constituted so that it might operate with the number of high frequency contains a plurality of 2 of a cascade which 分周 an input clock signal and generat...  
JP4851956B2  
JP2012500596A
[Means for Solution] A local oscillator is provided with a programmable frequency counting-down circuit combined with an output of VCO. A frequency counting-down circuit can be set in order to carry out a frequency part circumference by ...  
JPWO2010004747A
The part circumference way for multi-phase clock signals which data latch time can secure enough also in a multi-phase clock signal with high frequency is provided, For example, the main latch circuitry (10) which generates a reversal da...  
JPWO2010004747A1
高い周波数を持つ多相クロック信号において もデータラッチ時間が十分確保できる多相ク ロック信号用の分周回路を提供するように、 例えば8相クロック信号のうち2本のク...  
JP2011250057A
To provide a divider circuit which can generate and output a phase synchronized output signal and inverted signal thereof.A divider circuit 1 consists of a clock signal generation part 10, a frequency-divided signal generation part 20, a...  
JP4833241B2  
JP2011234352A
To suppress an operation defect of a frequency divider circuit.A frequency divider circuit includes a shift register which generates and outputs 2×X (X is a natural number of 2 or more) pieces of pulse signals in accordance with a first...  
JP4816953B2  
JP2011205630A
To provide a pulse signal output circuit that operates stably and a shift register including the pulse signal output circuit.The pulse signal output circuit includes a first to tenth transistors. The ratio W/L of the channel width W to t...  
JP4792272B2  
JP2011199363A
To provide a control apparatus that can be manufactured at low cost, while reducing malfunctions, and to provide an image forming apparatus.A control apparatus 30 generates a rise a2 of an output signal Sig2 with a delay of a predetermin...  
JP4780144B2  
JP2011188026A
To reduce power consumption by reducing an operation voltage in a clock frequency divider circuit.The clock frequency divider circuit includes: a counter for counting an input clock signal to form a D-ary count value; a counter for count...  
JP2011182364A
To provide a CMOS inverter type high-frequency divider with low current consumption for use in radio communication devices and the like.The divider includes a first to fourth inverter 4, 5, 6, and 7 with a latch function each of which in...  
JP4763049B2  
JP2011164688A
To reduce power consumption of a cumulative addition circuit.The cumulative addition circuit includes an addition circuit, a counter, and a clock gating control circuit. The addition circuit performs cumulative addition of data of prescr...  
JP2011524113A
A circuit which generates one which has the reduced skew from an input signal, or more output clock signals is provided. An input signal has the changes drawn from changes of an original clock which have different frequency from frequenc...  
JP4756135B2  
JP2011158872A
To provide an electro-optical device capable of using a region of a gate line drive circuit efficiently and preventing the rising speed of a gate line selection signal from decreasing (rising delay), and a shift register circuit composed...  
JP4743227B2  
JP2011151672A
To frequency-divide an input pulse train changing a period, and to suppress the jitter of the frequency-divided pulse train as much as possible.A frequency division device 1 takes a positive integer having mutually different first variab...  
JP2011151476A
To provide a synchronization circuit capable of correctly synchronizing a counter of an arbitrary value using gray codes, while suppressing increase of a circuit scale, and to provide a synchronization method.This synchronization circuit...  
JPWO2009125580A1
可変遅延回路は、基準クロックに対しアナロ グ信号に応じた可変遅延を与え、遅延クロッ クを生成する。位相検出部は、遅延クロック と基準クロックの位相差を検出し、位相...  
JP2011147107A
To inexpensively acquire a synchronizing generator which allows synchronization to be instantaneously established and a synchronous condition to be held with high precision for a relatively long time.This synchronizing generator includes...  
JP2011147165A
To provide a semiconductor device equipped with a register control delay lock loop (DLL) capable of reducing current consumption caused by unnecessary toggling of DLL clock.The semiconductor device comprising an internal circuit that use...  
JP4734510B2  
JPWO2009116398A1
マスク回路(10)で、入力されたマスク信号(50) 応じてクロックSのクロックパルスをマス することによりクロックBを生成して出力 、マスク制御回路(20)で、クロックBを...  
JP2011142503A
To provide a variable frequency dividing circuit which performs higher-speed frequency dividing operation.The variable frequency dividing circuit is provided with: a plurality of flip-flop circuits CT0-CT5 which receive a clock signal cl...  
JP4724506B2  
JP2011135297A
To improve the maximum operating frequency by reducing power consumption in a flip-flop circuit.A first data holding circuit (18) of a master-side element (100) and a second data holding circuit (19) of a slave-side element (200), are co...  
JP4717233B2  
JP4719843B2  
JP4713050B2  
JP4702718B2  
JP4684919B2  
JP2011514701A
A digital logic circuit includes a plurality of transistors of a same conduction type. In at least one embodiment, a first transistor has a source, gate and drain connected to a first circuit node, a second circuit node and a first power...  
JP2011086363A
To provide a driving circuit reducing malfunctions in the circuit in which a thin film transistor is changed into either an enhancement-type transistor or a depletion-type transistor.In a pulse output circuit, a circuit for raising the p...  
JP4672584B2  
JP4668430B2  
JP4668591B2  
JP2011071732A
To provide an integrated circuit device which can reduce delay time of serial data.The integrated circuit device 10 includes a shift register 18 which includes first to Nth (N is an integer of 2 or larger) registers 121, ..., 12N, is inp...  
JP2011071995A
To provide a counter circuit, apparatus including the same and counting method.A counter circuit includes a buffer section and a ripple counter. The buffer section generates at least one lower-bit signal by latching at least one input cl...  

Matches 501 - 550 out of 6,225