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Patent Searching and Data


Matches 551 - 600 out of 6,237

Document Document Title
JP4587620B2  
JP4583933B2  
JP2010258642A
To solve the problem of a conventional prescaler circuit that cannot perform high-accuracy frequency division at a high-speed operation.A prescaler circuit includes: an FF circuit 4 including a master-side latch circuit that generates an...  
JP2010258761A
To obtain an output clock signal by frequency-dividing an input clock signal in a frequency dividing ratio, that is represented with optional rational numbers, by enabling an output clock signal to rise in falling of the input clock sign...  
JP4560039B2  
JP4556730B2  
JP2010192625A
To provide a semiconductor device which enhances the stability of circuit operation and enables reduction in power consumption.The semiconductor device is provided with a frequency-dividing circuit which has floating body type PD-SOI-MOS...  
JP2010193373A
To provide a frequency divider capable of increasing an operation frequency in a simple circuit configuration. In the case where an operation control signal ENB is shifted to 'H' level and a clock signal VCO and a frequency dividing sign...  
JP2010192019A
To provide a shift register changing the order of scanning signal lines while suppressing increase in circuit area or increase in current consumption.Each stage constituting the shift register includes: a thin-film transistor TS for incr...  
JP4533599B2  
JP4536007B2  
JP2010187356A
To provide a frequency divider circuit capable of suppressing generation of a signal of an unwanted frequency.The frequency divider circuit includes: a shift register capable of storing at least n-bit data configured to shift an input si...  
JP2010178120A
To increase a setup margin and to perform an operation at a higher speed.The dual modulus prescaler includes 9 pieces of flip-flops U12, U4-U11 cascade-connected in a ring shape and a NAND gate U3. The flip-flops U12, U4-U11 are arrayed ...  
JP2010177751A
To provide a clock frequency divider circuit that executes phase adjustment of an output clock signal during frequency division while considering the communication timing of an operation circuit, and to provide a clock frequency dividing...  
JP4497708B2  
JP4499009B2  
JP4494227B2  
JP2010130283A
To provide a counter circuit capable of switching delay time by easy circuit structure. The counter circuit is constituted of flip-flops of a plurality of stages, to the initial stage of which a clock is supplied from an oscillator and t...  
JP2010124228A
To maintain the high speed of selecting circuit operation regardless of the increase of a frequency division ratio. A fixed value of a fixed period according to a frequency division ratio is output from a decoder 3 to respective precedin...  
JP2010118981A
To change a counter that counts signals to be counted, without changing wiring of signals to be counted to a count input circuit, or to supply signals to be counted to be supplied to one counter input circuit to a plurality of counters i...  
JP2010113343A
To provide a gate driver and an operation method of the driver.The gate driver for use in a liquid crystal display device has a plurality of shift registers connected in series. Each of the shift registers is used to provide a gate-line ...  
JP2010114888A
To provide a circuit for enhancing a duty cycle resolution by reducing jitter of an output clock signal.A counter for synthesizing clock signals with minimal jitter analyzes an ongoing count to determine whether the rising edge of an out...  
JP2010103504A
To reduce current consumption in a frequency-division circuit, and particularly to reduce current consumption in a multistage frequency-division circuit.In a multistage frequency-division circuit 100, an input signal has a higher frequen...  
JP4452063B2  
JP2010087820A
To solve the following problems: in frequency-dividing a clock, a method for frequency-dividing the clock with the use of a frequency-dividing counter to generate a transmission clock for serial communication can generates a frequency cl...  
JP4448128B2  
JP2010074637A
To provide a reliable up/down counter with a simple circuitry without using an external clock.The up/down counter device 10 outputs an up/down state signal (C) from two-phase pulse signals (A), (B) input to an up/down decoder 12 and gene...  
JP4442425B2  
JP2010061800A
To provide a driving circuit of a display device composed of semiconductor TFTs and obtaining a proper amplitude of an output signal.The TFTs 101, 104 are turned ON by an input of a pulse thereto. After a potential of a node is increased...  
JP2010056888A
To provide a synchronization control circuit capable of further reducing an area or power consumption in comparison with conventional circuits.In a frequency divider circuit unit 26, a frequency-divided clock RSELO is generated by freque...  
JP4431134B2  
JPWO2008065869A1
【課題】分周クロック信号のサイクル時間の 変動が小さく、分周クロック信号の最小のサ イクル時間が分周比に応じて拡大される機会 が多く、消費電力やレイアウト面積が小...  
JP4425062B2  
JPWO2008056551A1
分周クロック信号のサイクル時間が一定で、 消費電力やレイアウト面積が小さく、設計・ 検証コストが小さい有理数分周回路を提供す る。分周比がN/M(M、Nは正の整数...  
JP2010041466A
To perform high-precision variable frequency division by setting a variable frequency division ratio in a simple circuit configuration.A 1/P frequency divider 12 subjects an input clock ck to 1/P frequency division. A phase shifter 13 sh...  
JP4416396B2  
JP4418614B2  
JP2010501155A
A high speed, low electric power, and broadband operation are possible, and it provides a frequency synthesis machine including a profit compensation method and a high-speed voltage controlled oscillator (VCO) zone calibration method. Th...  
JP2010011389A
To achieve a frequency divider, in a simple configuration and with high accuracy, such as a baud rate generator that does not use any dedicated oscillator, wherein an error of a frequency to be divided is allowed.As a frequency divider, ...  
JP4390353B2  
JP2009545262A
An apparatus and a method for counting input pulses during a specific time interval are provided. A clock edge recovery output signal is produced in response to an input gating signal and a clock signal containing the input pulses. The c...  
JP4383876B2  
JP4386725B2  
JP2009290641A
To provide a DDS circuit capable of improving resolution, without increasing the bit length of a tuning word, and to oprovide an electronic appliance.This DDS circuit has a DDS part 11 to output a sign-wave signal from a tuning word, bas...  
JP2009543470A
The modulus counting-down circuit stage (MDS) includes the 1st and the 2nd stage. MDS receives the number control signal S of modulus 除 which determines by any the MDS shall operate between 2 division mode or trichotomy mode. The stage...  
JP2009283065A
To save power of a clock circuit unit for controlling a DLL (Delay Locked Loop) circuit etc. which requires a start-up time before normal operation.A clock generating circuit is connected to a counter circuit which controls an operation ...  
JP2009278604A
To provide a counter, which reduces propagation time delay of the counter and minimizes data skew.An n-bit counter includes n counter blocks each including: a D-flipflop; a second MUX which selects any one of external data and a second o...  
JP2009278478A
To provide a counter circuit capable of rightly counting a high frequency signal in which hazard or the like may easily occur.A counter circuit includes: a frequency divider circuit 100 for generating frequency-divided clocks LCLKE, LCLK...  
JP4371046B2  
JP2009540762A
The bidirectional direct sequence spectral diffusion half duplex RF modem for transmitting and receiving an analog and digital pulse modulation is provided. The modem incorporates the correlation machine of a SAW base, in order to perfor...  

Matches 551 - 600 out of 6,237